Nikita Popov [Mon, 7 Feb 2022 11:37:21 +0000 (12:37 +0100)]
[Bitcode] Add missing test file
This was supposed to be part of
ec18030f5fc1f4a08326e65fe06c6f265a829f4c.
Nikita Popov [Mon, 7 Feb 2022 11:26:12 +0000 (12:26 +0100)]
[Bitcode] Handle invalid data layout gracefully
Valentin Clement [Mon, 7 Feb 2022 11:18:24 +0000 (12:18 +0100)]
[flang] Handle character constant for error code in STOP stmt
Handle character constant ofr error code in the STOP statement.
Depends on D118992
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan, schweitz
Differential Revision: https://reviews.llvm.org/D118993
Valentin Clement [Mon, 7 Feb 2022 11:17:02 +0000 (12:17 +0100)]
[flang] Add lowering for ASCII character constant
Lower character constant of KIND = 1 with the
`createStringLiteral` helper function.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan, schweitz
Differential Revision: https://reviews.llvm.org/D118992
Nikita Popov [Mon, 7 Feb 2022 10:51:19 +0000 (11:51 +0100)]
[Bitcode] Guard against out of bounds value reference
We should make sure that the value ID is in bounds, otherwise
we will assert / read out of bounds.
Nikita Popov [Mon, 7 Feb 2022 10:43:29 +0000 (11:43 +0100)]
[Bitstream] Check that there is enough space for blob
Instead of simply assuming that it will be zero. I double checked
that the bitstream reader doesn't have any special handling for
all-zero blobs, it will always write out the full contents.
Nikita Popov [Mon, 7 Feb 2022 10:15:43 +0000 (11:15 +0100)]
[Bitcode] Don't assert on invalid attribute group record
Report an error instead.
Nikita Popov [Mon, 7 Feb 2022 09:56:14 +0000 (10:56 +0100)]
[Bitstream] Reject implausibly large reservations
If we're trying to reserve more memory than bits in the stream,
reject this early to avoid OOM.
Valentin Clement [Mon, 7 Feb 2022 10:40:37 +0000 (11:40 +0100)]
[flang] Remove unused converter for now
AbstractConverter private variable is currently not used
and triggers a buildbot failure.
https://lab.llvm.org/buildbot/#/builders/180/builds/3119
This fixes the buildbot.
Sven van Haastregt [Mon, 7 Feb 2022 10:54:55 +0000 (10:54 +0000)]
[OpenCL] opencl-c.h: make attribute order consistent; NFC
For most builtins, `__purefn` always comes after `__ovld`, but the
read_image functions did not follow this pattern.
Igor Kirillov [Fri, 4 Feb 2022 13:26:10 +0000 (13:26 +0000)]
[OpenMP] kmp_atomic_float10_max_min.c test should only be executed on x86 platform
Differential Revision: https://reviews.llvm.org/D118988
Dimitry Andric [Fri, 4 Feb 2022 20:53:09 +0000 (21:53 +0100)]
[TSan] Handle FreeBSD specific indirection of libpthread functions
Similar to
60cc1d3218fc for NetBSD, add aliases and interceptors for the
following pthread related functions:
- pthread_cond_init(3)
- pthread_cond_destroy(3)
- pthread_cond_signal(3)
- pthread_cond_broadcast(3)
- pthread_cond_wait(3)
- pthread_mutex_init(3)
- pthread_mutex_destroy(3)
- pthread_mutex_lock(3)
- pthread_mutex_trylock(3)
- pthread_mutex_unlock(3)
- pthread_rwlock_init(3)
- pthread_rwlock_destroy(3)
- pthread_rwlock_rdlock(3)
- pthread_rwlock_tryrdlock(3)
- pthread_rwlock_wrlock(3)
- pthread_rwlock_trywrlock(3)
- pthread_rwlock_unlock(3)
- pthread_once(3)
- pthread_sigmask(3)
In FreeBSD's libc, a number of internal aliases of the pthread functions
are invoked, typically with an additional prefixed underscore, e.g.
_pthread_cond_init() and so on.
ThreadSanitizer needs to intercept these aliases too, otherwise some
false positive reports about data races might be produced.
Reviewed By: dvyukov
Differential Revision: https://reviews.llvm.org/D119034
Simon Pilgrim [Mon, 7 Feb 2022 09:58:47 +0000 (09:58 +0000)]
[DAG] visitINSERT_VECTOR_ELT - break if-else chain as they both return (style). NFC.
Simon Pilgrim [Mon, 7 Feb 2022 09:54:34 +0000 (09:54 +0000)]
[X86] combineShiftRightArithmetic - break if-else chain as they all return (style). NFC.
Simon Pilgrim [Mon, 7 Feb 2022 09:50:09 +0000 (09:50 +0000)]
[GlobalISel] Move getOpcode() calls inside assert() to avoid (void)s. NFC.
Tidier solution to the unused variable warnings - we already do this in other places in this file.
Zi Xuan Wu [Mon, 7 Feb 2022 09:26:13 +0000 (17:26 +0800)]
[CSKY] Add inline asm constraints and related codegen support
There are kinds of inline asm constraints and corresponding register class or register as following.
'b': mGPRRegClass
'v': sGPRRegClass
'w': sFPR32RegClass or sFPR64RegClass
'c': C register
'z': R14 register
'h': HI register
'l': LO register
'y': HI or LO register
It also adds codegen test for inline-asm including constraints, clobbers and abi names.
Simon Pilgrim [Mon, 7 Feb 2022 09:43:32 +0000 (09:43 +0000)]
[X86] Add fp80 copysign test coverage
Add PR41749 test coverage
Djordje Todorovic [Mon, 7 Feb 2022 09:37:55 +0000 (10:37 +0100)]
[SLPVectorizer] Fix "unused variable" build warning
Nikita Popov [Mon, 7 Feb 2022 09:34:34 +0000 (10:34 +0100)]
[Bitcode] Handle invalid abbrev number error more gracefully
Avoid report_fatal_error(), propagate the error upwards instead.
Nikita Popov [Fri, 4 Feb 2022 14:28:44 +0000 (15:28 +0100)]
[Bitcode] Add fuzzer for bitcode reading
Inspired by the discussion on D118694, this adds a straightforward
fuzzer for bitcode reading. Currently it will very quickly run into
OOM, because we do unconditional vector reservations with
user-provided sizes.
Brad Smith [Mon, 7 Feb 2022 09:04:39 +0000 (04:04 -0500)]
[Driver][OpenBSD] -r: imply -nostdlib like GCC
Similar to D116843 for Gnu.cpp
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D119071
Mariya Podchishchaeva [Thu, 3 Feb 2022 15:37:48 +0000 (18:37 +0300)]
[SYCL] Disallow explicit casts between mismatching address spaces
Reviewed By: bader
Differential Revision: https://reviews.llvm.org/D118935
Djordje Todorovic [Mon, 7 Feb 2022 08:32:09 +0000 (09:32 +0100)]
[GlobalIsel] Fix another "unused variable" warning
Djordje Todorovic [Mon, 7 Feb 2022 08:24:59 +0000 (09:24 +0100)]
Fix the warning after D118805
A variable was used within assert() only.
Valentin Clement [Fri, 4 Feb 2022 10:58:06 +0000 (11:58 +0100)]
[flang] Add test for quiet with local variable in STOP stmt
Depends on D118978.
Differential Revision: https://reviews.llvm.org/D118982
Valentin Clement [Mon, 7 Feb 2022 08:12:17 +0000 (09:12 +0100)]
[flang] Basic local variable lowering
This patch add lowering for simple local variable.
- The signatures in `ConvertType.h` have been simplified to take advantage of the `AbstractConverter`.
- The lowering make use of the `allocateLocal` from the `FirOpBuilder`.
This lowering is used in patch D118982
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan, jeanPerier, schweitz
Differential Revision: https://reviews.llvm.org/D118978
Luo, Yuanke [Mon, 7 Feb 2022 07:58:45 +0000 (15:58 +0800)]
[X86] Add test cases for fmul/fdiv with select.
Jun Zhang [Mon, 7 Feb 2022 04:04:13 +0000 (12:04 +0800)]
[NFC][Analyzer] Use range based for loop.
Use range base loop loop to improve code readability.
Differential Revision: https://reviews.llvm.org/D119103
luxufan [Tue, 25 Jan 2022 16:08:39 +0000 (00:08 +0800)]
[JITLink] Fix the incorrect relocation behavior for R_RISCV_BRANCH
In D116573, the relocation behavior of R_RISCV_BRANCH didn't consider that branch instruction like 'bge' has a branch target address which is given as a PC-relative offset, sign-extend and multiplied by 2.
Although the target address is a 12-bits number, acctually its range is [-4096, 4094].
This patch fix it.
Differential Revision: https://reviews.llvm.org/D118151
Kazu Hirata [Mon, 7 Feb 2022 06:18:35 +0000 (22:18 -0800)]
[llvm] Use = default (NFC)
Chuanqi Xu [Mon, 7 Feb 2022 04:47:14 +0000 (12:47 +0800)]
[NFC] Precommit test case for PR53357
zhongyunde 00443407 [Mon, 10 Jan 2022 01:18:57 +0000 (09:18 +0800)]
[DAGCombiner][AArch64] Enhance to support for scalar CSINC
Enhance to fold csel into csinc instruction.
Fix https://github.com/llvm/llvm-project/issues/53071
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D116915
Phoebe Wang [Mon, 7 Feb 2022 01:22:19 +0000 (09:22 +0800)]
[X86] Add pre-commit test for bit test optimization. NFC
Jacques Pienaar [Mon, 7 Feb 2022 01:21:48 +0000 (17:21 -0800)]
[mlir][bazel] Update post ControlFlow dialect split
Kazu Hirata [Mon, 7 Feb 2022 00:36:29 +0000 (16:36 -0800)]
[IR] Use default member initialization in GlobalValue (NFC)
Kazu Hirata [Mon, 7 Feb 2022 00:36:27 +0000 (16:36 -0800)]
[Transforms] Use default member initialization in LibCallSimplifier (NFC)
Kazu Hirata [Mon, 7 Feb 2022 00:36:25 +0000 (16:36 -0800)]
[Transforms] Use default member initialization in LoopVersioning (NFC)
Benjamin Kramer [Sun, 6 Feb 2022 13:06:34 +0000 (14:06 +0100)]
[mlir] Use SmallBitVector instead of SmallDenseSet for AffineMap::compressSymbols
This is both more efficient and more ergonomic to use, as inverting a
bit vector is trivial while inverting a set is annoying.
Sadly this leaks into a bunch of APIs downstream, so adapt them as well.
This would be NFC, but there is an ordering dependency in MemRefOps's
computeMemRefRankReductionMask. This is now deterministic, previously it
was dependent on SmallDenseSet's unspecified iteration order.
Differential Revision: https://reviews.llvm.org/D119076
River Riddle [Sun, 6 Feb 2022 23:10:03 +0000 (15:10 -0800)]
[mlir] Fix GpuToLLVM conversion pass after ControlFlow operations were split from Standard
Stella Laurenzo [Sun, 6 Feb 2022 05:50:27 +0000 (21:50 -0800)]
[mlir] Fixup python bindings after splitting cf ops from std.
River Riddle [Fri, 4 Feb 2022 04:59:43 +0000 (20:59 -0800)]
[mlir] Split out a new ControlFlow dialect from Standard
This dialect is intended to model lower level/branch based control-flow constructs. The initial set
of operations are: AssertOp, BranchOp, CondBranchOp, SwitchOp; all split out from the current
standard dialect.
See https://discourse.llvm.org/t/standard-dialect-the-final-chapter/6061
Differential Revision: https://reviews.llvm.org/D118966
Eugene Zhulenev [Sun, 6 Feb 2022 22:38:33 +0000 (14:38 -0800)]
[mlir] Add canonicalizer to remove redundant shape.cstr_broadcastable ops
Depends On D119025
Reviewed By: frgossen
Differential Revision: https://reviews.llvm.org/D119043
Congzhe Cao [Sun, 6 Feb 2022 21:55:20 +0000 (16:55 -0500)]
[LoopInterchange] Support loop interchange with floating point reductions
Enabled loop interchange support for floating point reductions
if it is allowed to reorder floating point operations.
Previously when we encouter a floating point PHI node in the
outer loop exit block, we bailed out since we could not detect
floating point reductions in the early days. Now we remove this
limiation since we are able to detect floating point reductions.
Reviewed By: #loopoptwg, Meinersbur
Differential Revision: https://reviews.llvm.org/D117450
Mehdi Amini [Sun, 6 Feb 2022 19:48:25 +0000 (19:48 +0000)]
Remove dead forward declaration (NFC)
Simon Pilgrim [Sun, 6 Feb 2022 19:40:08 +0000 (19:40 +0000)]
[KnownBits] Add support for X*X self-multiplication (update)
Rename the SelfMultiply argument to make it clearer that the argument must not be undef
Differential Revision: https://reviews.llvm.org/D108992
Simon Pilgrim [Sun, 6 Feb 2022 19:13:11 +0000 (19:13 +0000)]
[InstCombine] Add mul(x,x) tests showing miscompile
As raised by @efriedma on D117995 - the source must not be undef to demand any bits in mul(x,x) other than bit[1]
https://alive2.llvm.org/ce/z/Cxkjen
Craig Topper [Sun, 6 Feb 2022 18:44:05 +0000 (10:44 -0800)]
[DAGCombiner][RISCV] Allow rotates by non-constant to be matched for i32 on riscv64 with Zbb.
rv64izbb has a RORW/ROLW instructions that operate on the lower
32-bits of a 64-bit value and sign extend bit 31 of the result.
DAGCombiner won't match rotate idioms because the i32 type isn't Legal
on riscv64.
This patch teaches DAGCombiner to allow it if the type is going to
be promoted and the target has Custom type legalization for ISD::ROTL
or ISD::ROTR. I've restricted this to scalar types. It doesn't appear
any in tree targets other than riscv64 have custom type legalization
for rotates.
If this patch isn't acceptable, I guess I can match SRLW, SLLW, and OR
after type legalization, but I'd like to avoid that if possible.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D119062
Kazu Hirata [Sun, 6 Feb 2022 18:54:48 +0000 (10:54 -0800)]
[llvm] Fix header guards (NFC)
Identified with llvm-header-guard.
Kazu Hirata [Sun, 6 Feb 2022 18:54:46 +0000 (10:54 -0800)]
[Breakpoint] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
Kazu Hirata [Sun, 6 Feb 2022 18:54:44 +0000 (10:54 -0800)]
[CodeGen] Use = default (NFC)
Identified with modernize-use-equals-default
Kazu Hirata [Sun, 6 Feb 2022 18:54:42 +0000 (10:54 -0800)]
[Driver] Remove redundant string initialization (NFC)
Identified with readability-redundant-string-init.
Jared Irwin [Sun, 6 Feb 2022 17:36:12 +0000 (12:36 -0500)]
[lld-macho] Add -pagezero_size
Adds `-pagezero_size`. `-pagezero_size` commonly used for kernel development.
`-pagezero_size` changes the `__PAGEZERO` size, removing that segment if it is set to zero.
One of the four flags from {D118570}
Now with error messages and tests.
Differential Revision: https://reviews.llvm.org/D118724
Bjorn Pettersson [Wed, 2 Feb 2022 09:20:00 +0000 (10:20 +0100)]
[DAGCombiner] Fold SSHLSAT/USHLSAT to SHL when no saturation will occur
When the shift amount is known and a known sign bit analysis of
the shiftee indicates that no saturation will occur, then we can
replace SSHLSAT/USHLSAT by SHL.
Differential Revision: https://reviews.llvm.org/D118765
Bjorn Pettersson [Wed, 2 Feb 2022 09:08:26 +0000 (10:08 +0100)]
Pre-commit test cases for DAG combine folds of SSHLSAT/USHLSAT -> SHL
It should be possible to replace SSHLSAT and USHLSAT with SHL when
it is known that no saturation will take place (e.g. by analysing
known sign bits in the first shift operand).
Differential Revision: https://reviews.llvm.org/D118764
Simon Pilgrim [Sun, 6 Feb 2022 17:19:23 +0000 (17:19 +0000)]
Revert rG7275de7fb2f087871611d037d1b529b226dd0521 "[AArch64] translateLocChar - silence dead code warning"
Seems to cause some buildbot misbehaviour (+ there's a dumb copy+paste typo in the commit message....)
Simon Pilgrim [Sun, 6 Feb 2022 17:17:28 +0000 (17:17 +0000)]
[clang][CodeGen] Add _BitInt test coverage to builtins-elementwise-math.c
As suggested on D117898, we should be testing irregular _BitInt types with the __builtin_elementwise_* intrinsics
Simon Pilgrim [Sun, 6 Feb 2022 16:52:23 +0000 (16:52 +0000)]
Fix Wdocumentation unknown parameter warning
Florian Hahn [Sun, 6 Feb 2022 16:37:20 +0000 (16:37 +0000)]
[LV] Use VPReplicateRecipe::isUniform instead isUniformAfterVec (NFCI).
In scalarizeInstruction(), isUniformAfterVectorization is used to detect
cases where it is sufficient to always access the first lane. This
should map directly checking whether the operand is a uniform replicate
recipe.
Differential Revision: https://reviews.llvm.org/D116654
Simon Pilgrim [Sun, 6 Feb 2022 16:32:16 +0000 (16:32 +0000)]
[AArch64] translateLocChar - silence dead code warning
Remove default case from switch and return None after the switch()
Simon Pilgrim [Sun, 6 Feb 2022 16:29:38 +0000 (16:29 +0000)]
[AArch64] LowerVectorSRA_SRL_SHL - silence dead code warning
Remove default case from switch and move llvm_unreachable to after the switch()
Simon Pilgrim [Sun, 6 Feb 2022 16:25:44 +0000 (16:25 +0000)]
[Support] Use llvm_unreachable instead of LLVM_BUILTIN_UNREACHABLE internal define
David Green [Sun, 6 Feb 2022 16:17:06 +0000 (16:17 +0000)]
[ARM] Mark i64 and f64 shuffles as Custom for MVE
This way they get lowered through the ARMISD::BUILD_VECTOR, which can
produce more efficient D register moves.
Also helps D115653 not get stuck in a loop.
David Green [Sun, 6 Feb 2022 14:12:28 +0000 (14:12 +0000)]
[ARM] Add extra vabd, vhadd and vmulh tests. NFC
This is some extra testing for vabd, vhadd and vmulh. Some of the tests
have also be reordered.
Simon Pilgrim [Sun, 6 Feb 2022 12:53:11 +0000 (12:53 +0000)]
[X86] Fold ZERO_EXTEND_VECTOR_INREG(BUILD_VECTOR(X,Y,?,?)) -> BUILD_VECTOR(X,0,Y,0)
Helps avoid some unnecessary shift by splat amount extensions before shuffle combining gets limited by with one use checks
Fangrui Song [Sun, 6 Feb 2022 07:34:14 +0000 (23:34 -0800)]
[ELF] Fix crash when an input is incompatible with a lazy object file
The diagnostic is concise. It is ok because the case is rare.
Stella Laurenzo [Sun, 6 Feb 2022 06:04:19 +0000 (22:04 -0800)]
[mlir] Do not use an empty source file when building aggregate libraries.
See discussion: https://discourse.llvm.org/t/check-mlir-times-examples-standalone-testing-time/6073/7
It turns out that it has been legal since CMake 3.11 to omit sources at library creation time if they are added later via target_sources, as is done here. This side-steps the issue of having a file that changes and invalidates the build of leaves.
Differential Revision: https://reviews.llvm.org/D119069
Rong Xu [Fri, 4 Feb 2022 20:23:47 +0000 (12:23 -0800)]
[SampleFDO] Enable FSAFDO loading passes if --enable-fs-discriminator is enabled
FSAFDO profile loader is currently disabled even --enable-fs-discriminator is enabled.
They need to be turned on by options which makes it cumbersome for experiments.
This patch changes the FSAFDO profile loader enabled by default. Since they are
guarded by EnableFSDiscriminator, they will only be turned on if
--enable-fs-discriminator is enabled. Note that --enable-fs-discriminator is
still disabled by default.
Differential Revision: https://reviews.llvm.org/D119033
Kazu Hirata [Sun, 6 Feb 2022 05:39:27 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in SCEVFindUnsafe (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:25 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in AAIsDeadCallSiteReturned (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:23 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in TruncInstCombine (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:21 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in MaskOps (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:19 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in EscapeEnumerator (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:17 +0000 (21:39 -0800)]
[IR] Use default member initialization in PMDataManager (NFC)
Craig Topper [Sat, 5 Feb 2022 21:54:38 +0000 (13:54 -0800)]
[RISCV] Add signext test for llvm.abs.i32 for rv64 Zbb.
This shows that we don't preserve sign bits across the
abs expansion, but I think we could if we used negw+max.
Fangrui Song [Sun, 6 Feb 2022 04:43:51 +0000 (20:43 -0800)]
[ELF] SharedFile::parse: move verdefIndex assignment outside of ctor. NFC
SharedSymbol::SharedSymbol initializes verdefIndex and Symbol::replace
copies verdefIndex.
By move verdefIndex assignment outside of ctor, Symbol::replace can be changed
to not copy verdefIndex. This can be used to decrease work for for
ObjKind/BitcodeKind.
Ruiling Song [Mon, 17 Jan 2022 06:54:38 +0000 (14:54 +0800)]
AMDGPU: Don't clobber source register for V_SET_INACTIVE_*
The WWM register has unmodeled register liveness, For v_set_inactive_*,
clobberring source register is dangerous because it will overwrite the
inactive lanes. When the source vgpr is dead at v_set_inactive_lane,
the inactive lanes may be not really dead. This may make common
optimizations doing wrong.
For example in a simple if-then cfg in Machine IR:
bb.if:
%src =
bb.then:
%src1 = COPY %src
%dst = V_SET_INACTIVE %src1(tied-def 0), %inactive
bb.end
... = PHI [0, %bb.then] [%src, %bb.if]
The register coalescer will think it is safe to optimize "%src1 = COPY %src"
in bb.then. And at the same time, there is no interference for the PHI in
bb.end. The source and destination values of the PHI will be assigned
the same register. The single PHI register will be overwritten by the
v_set_inactive, then we would get wrong value in bb.end.
With this change, we will copy the content of the source register before
setting inactive lanes after register allocation. Yes, this will sacrifice
the WWM code generation a little, but I don't have any better idea to do things
correctly.
Differential Revision: https://reviews.llvm.org/D117482
Ruiling Song [Tue, 18 Jan 2022 00:29:10 +0000 (08:29 +0800)]
AMDGPU: add test to show wwm register overwrite issue
Pre-commit the test to make the diff easy to read later.
Differential Revision: https://reviews.llvm.org/D117527
Krystian Kuzniarek [Sun, 6 Feb 2022 03:51:53 +0000 (19:51 -0800)]
[clang-format][docs] Fix incorrect 'clang-format 14' option markers
Introduced by
23a5090c6, some style option markers indicated 'clang-format 14',
though their respective options were available in earlier releases.
Note: Even though the value type of 'SpacesInAngles' option changed,
this option has been already present since version 3.4.
Differential Revision: https://reviews.llvm.org/D118991
Fangrui Song [Sun, 6 Feb 2022 00:34:02 +0000 (16:34 -0800)]
[ELF] Symbol::replace: use the old nameData/nameSize. NFC
Currently `this->getName() == newSym.getName()`.
By keeping the old nameData/nameSize, newSym's nameData/nameSize will be
ignored. The call sites can avoid calling getName().
printTraceSymbol needs to take the symbol name since `other`'s name is empty.
Adrian Prantl [Sun, 6 Feb 2022 00:27:47 +0000 (16:27 -0800)]
fix module build failure
Adrian Prantl [Sun, 6 Feb 2022 00:23:12 +0000 (16:23 -0800)]
fix module build failure
Adrian Prantl [Sun, 6 Feb 2022 00:20:15 +0000 (16:20 -0800)]
fix module build failure
Kazu Hirata [Sun, 6 Feb 2022 00:29:28 +0000 (16:29 -0800)]
[Support] Use default member initialization in ScopedPrinter (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:26 +0000 (16:29 -0800)]
[IR] Use default member initialization in GlobalObject (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:24 +0000 (16:29 -0800)]
[ADT] Use default member initialization in OptionalStorage (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:22 +0000 (16:29 -0800)]
[Transforms] Use default member initialization in SimplifyIndvar (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:20 +0000 (16:29 -0800)]
[ADT] Use default member initialization in DebugEpochBase (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:18 +0000 (16:29 -0800)]
[MC] Use default member initialization in WasmCustomSection (NFC)
Benjamin Kramer [Sat, 5 Feb 2022 23:48:05 +0000 (00:48 +0100)]
[SLP] Skip a DenseSet<unsigned> -> bit vector conversion. NFCI.
Fangrui Song [Sat, 5 Feb 2022 23:25:23 +0000 (15:25 -0800)]
[ELF] Don't access other eSym members it st_shndx == SHN_UNDEF. NFC
Fangrui Song [Sat, 5 Feb 2022 23:03:55 +0000 (15:03 -0800)]
[ELF] De-template reportUndefinedSymbols. NFC
My x86-64 lld executable is 16KiB smaller.
Adrian Prantl [Sat, 5 Feb 2022 22:54:41 +0000 (14:54 -0800)]
Revert "Disable TestLldbGdbServer on Dwarf2 and clang versions below 14"
This reverts commit
867fdec1945df3c1031d3cefdc97903131a3482b.
Adrian Prantl [Sat, 5 Feb 2022 22:54:37 +0000 (14:54 -0800)]
Revert "Fixed typos in TestLldbGdbServer.py"
This reverts commit
cf93a085754e221f73a2877c946dcb2beb6039d7.
Fangrui Song [Sat, 5 Feb 2022 22:40:15 +0000 (14:40 -0800)]
[ELF] Move Symbol::needsTlsLd to config->needsTlsLd. NFC
to decrease sizeof(SymbolUnion) from 72 to 64 on ELF64 platforms.
Benjamin Kramer [Sat, 5 Feb 2022 22:33:06 +0000 (23:33 +0100)]
Simplify mask creation with llvm::seq. NFCI.
Yaxun (Sam) Liu [Fri, 4 Feb 2022 23:18:14 +0000 (18:18 -0500)]
[HIPSPV] Fix literals are mapped to Generic address space
This issue is an oversight in D108621.
Literals in HIP are emitted as global constant variables with default
address space which maps to Generic address space for HIPSPV. In
SPIR-V such variables translate to OpVariable instructions with
Generic storage class which are not legal. Fix by mapping literals
to CrossWorkGroup address space.
The literals are not mapped to UniformConstant because the “flat”
pointers in HIP may reference them and “flat” pointers are modeled
as Generic pointers in SPIR-V. In SPIR-V/OpenCL UniformConstant
pointers may not be casted to Generic.
Patch by: Henry Linjamäki
Reviewed by: Yaxun Liu
Differential Revision: https://reviews.llvm.org/D118876
Fangrui Song [Sat, 5 Feb 2022 22:11:37 +0000 (14:11 -0800)]
[ELF] Reorder Symbol members to improve access locality. NFC
* partition and isPreemptible are frequently used. Move it to the front
* move used beside isUsedInRegularObj. They are similar and accessed together in .symtab finalizing
* move auxIdx/dynsymIndex/verdefIndex to the end.
This decreases code size.
Koakuma [Sat, 5 Feb 2022 21:08:26 +0000 (13:08 -0800)]
[libunwind] [sparc] Add SPARCv9 support
Adds libunwind support for SPARCv9 (aka sparc64). This is a rebase of @kettenis' patch D32450, which I created (with his permission) because the original review has become inactive.
The changes are of a cosmetic nature to make it fit better with the new code style, and to reuse the existing SPARCv8 code, whenever possible.
Please let me know if I posted this on the wrong place. Also, the summary of the original review is reproduced below:
> This adds unwinder support for 64-bit SPARC (aka SPARCv9). The implementation was done on OpenBSD/sparc64, so it takes StackGhost into account:
>
> https://www.usenix.org/legacy/publications/library/proceedings/sec01/full_papers/frantzen/frantzen_html/index.html
>
> Since StackGhost xor's return addresses with a random cookie before storing them on the stack, the unwinder has to do some extra work to recover those. This is done by introducing a new kRegisterInCFADecrypt "location" type that is used to implement the DW_CFA_GNU_window_save opcode. That implementation is SPARC-specific, but should work for 32-bit SPARC as well. DW_CFA_GNU_window_save is only ever generated on SPARC as far as I know.
Co-authored-by: Mark Kettenis
Reviewed By: #libunwind, thesamesam, MaskRay, Arfrever
Differential Revision: https://reviews.llvm.org/D116857
Simon Pilgrim [Sat, 5 Feb 2022 21:03:51 +0000 (21:03 +0000)]
[libunwind] Attempt to fix broken sphinx doc link
bbce75e352be0637305a1b59ac5eca7175bceece replaced `LLVM Bugzilla` with `LLVM bug tracker`
Craig Topper [Sat, 5 Feb 2022 20:51:01 +0000 (12:51 -0800)]
Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)."
This reverts commit
673d68cd923a9daa5065b929453bf4a4b8d39650.
This hadn't been reviewed yet.