ci: bump VVL to 1.3.263

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24925>

intel/dev: Update device string for MTL PCI ID 0x7d55

Ref: bspec 55420
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25073>

nvk: Invalidate the texture cache in PipelineBarrier

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>

nvk: Set the discard bit for Z/S self-deps

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>

nvk: Don't add a dummy attachment when gl_SampleMask is written

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>

intel/compiler: Don't evict for workgroup-scope fences

Flushing and invalidating caches isn't necessary for workgroup scope
fences.  In fact, the DP_FLUSH_TYPE docs (BSpec 54041) say:

   "If the fence scope is Local or Threadgroup, HW ignores the flush
    type and operates as if it was set to None(no flush)"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

intel/compiler: Combine control barriers with identical memory semantics

This prevents the second barrier generating a spurious, identical fence
message as the first barrier.

fossil-db stats on Alchemist:

   Totals:
   Instrs: 196513342 -> 196512777 (-0.00%); split: -0.00%, +0.00%
   Cycles: 14271426028 -> 14271404569 (-0.00%); split: -0.00%, +0.00%
   Send messages: 8021892 -> 8021770 (-0.00%)

   Totals from 46 (0.01% of 653252) affected shaders:
   Instrs: 76761 -> 76196 (-0.74%); split: -0.75%, +0.01%
   Cycles: 2027946 -> 2006487 (-1.06%); split: -1.45%, +0.39%
   Send messages: 7589 -> 7467 (-1.61%)

Nothing in shader-db was affected.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

anv: Use nir_opt_barrier_modes() to drop unnecessary barriers

fossil-db stats on Alchemist:

   Totals:
   Instrs: 196514947 -> 196513342 (-0.00%); split: -0.00%, +0.00%
   Cycles: 14271450761 -> 14271426028 (-0.00%); split: -0.00%, +0.00%
   Send messages: 8022316 -> 8021892 (-0.01%)

   Totals from 43 (0.01% of 653252) affected shaders:
   Instrs: 98558 -> 96953 (-1.63%); split: -1.63%, +0.00%
   Cycles: 15867801 -> 15843068 (-0.16%); split: -0.17%, +0.02%
   Send messages: 8997 -> 8573 (-4.71%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

glsl: Use nir_opt_barrier_modes() to drop unnecessary barriers

iris shader-db stats on Alchemist:

    total instructions in shared programs: 23150249 -> 23142733 (-0.03%)
    instructions in affected programs: 157322 -> 149806 (-4.78%)
    helped: 105
    HURT: 2
    helped stats (abs) min: 2 max: 821 x̄: 71.61 x̃: 15
    helped stats (rel) min: 0.13% max: 27.56% x̄: 6.21% x̃: 2.35%
    HURT stats (abs)   min: 1 max: 2 x̄: 1.50 x̃: 1
    HURT stats (rel)   min: 0.18% max: 0.23% x̄: 0.20% x̃: 0.20%
    95% mean confidence interval for instructions value: -101.99 -38.50
    95% mean confidence interval for instructions %-change: -7.59% -4.58%
    Instructions are helped.

    total sends in shared programs: 1036916 -> 1035366 (-0.15%)
    sends in affected programs: 15274 -> 13724 (-10.15%)
    helped: 108 / HURT: 0
    helped stats (abs) min: 1 max: 162 x̄: 14.35 x̃: 3
    helped stats (rel) min: 0.88% max: 33.83% x̄: 9.81% x̃: 5.05%
    95% mean confidence interval for sends value: -20.79 -7.92
    95% mean confidence interval for sends %-change: -11.66% -7.95%

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

dxil: Set UAV_FENCE_THREAD_GROUP any time global isn't required

With the new nir_opt_barrier_modes() pass, we may encounter control
barriers with no memory modes set, such as:

   @barrier () (execution_scope=WORKGROUP, memory_scope=WORKGROUP, mem_semantics=ACQ|REL, mem_modes=0)

The DXIL validator documentation [1] mentions an
INSTR.BARRIERMODENOMEMORY validation rule:

   "sync must include some form of memory barrier - _u (UAV) and/or
    _g (Thread Group Shared Memory). Only _t (thread group sync) is
    optional."

We were generating a dx.op.barrier instruction with only one flag,
DXIL_BARRIER_MODE_SYNC_THREAD_GROUP.  This seems to run afoul of the
above validator rule.  So, this patch adjusts the code generator to
set DXIL_BARRIER_MODE_UAV_FENCE_THREAD_GROUP too, whenever
UAV_FENCE_GLOBAL isn't required.

[1] https://github.com/microsoft/DirectXShaderCompiler/blob/main/docs/DXIL.rst

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

virgl, nir_to_tgsi: Add a hack for promoting partial memory barriers

Most drivers will want nir_opt_barrier_modes() to optimize out
unnecessary memory barrier modes.  However, virgl has to translate
back to GLSL, which means it can really only handle partial memory
barriers in compute shaders today, because there isn't a proper
way to express them otherwise.  Just ask nir_to_tgsi to promote
these back to full barriers as a workaround.

See KHR-GL43.shader_storage_buffer_object.advanced-readWrite-case1
on virpipe-on-gl as a case where this hack is needed.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

lavapipe: Don't delete control barriers

Control barriers still need to do synchronization even if there are no
associated memory barrier modes.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

nir: Reduce the scope of shared memory barriers

Originally written by Ian Romanick for the Intel backend, but ported
to the new nir_opt_barrier_modes() common optimization pass.  Ian's
original explanation and commit message follows:

Shared memory only exists within a workgroup, so synchronizing it beyond
workgroup scope is nonsense.

Basically every SPIR-V compiler generates operations like

    OpMemoryBarrier(/*Memory*/Device,
                    /*Semantics*/AcquireRelease | WorkgroupMemory)

This is suggested in numerous places, including
https://github.com/KhronosGroup/GLSL/blob/master/extensions/khr/GL_KHR_vulkan_glsl.txt.
Even Mesa's glsl_to_nir pass does this. This advice, which has been
copy-and-pasted everywhere, is contrary to issue 13 in the original
GL_ARB_compute_shader spec:

   "Since shared memory is only accessible to threads within a single
    work group, memoryBarrierShared() also only requires synchronization
    with other threads in the same work group."

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

nir: Add an optimization pass to reduce barrier modes

Many shaders issue full memory barriers, which may need to synchronize
access to images, SSBOs, shared local memory, or global memory.
However, many of them only use a subset of those memory types - say,
only SSBOs.

Shaders may also have patterns such as:

   1. shared local memory access
   2. barrier with full variable modes
   3. more shared local memory access
   4. image access

In this case, the barrier is needed to ensure synchronization between
the various shared memory operations.  Image reads and writes do also
exist, but they are all on one side of the barrier, so it is a no-op for
image access.  We can drop the image mode from the barrier here too.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

nir: Fix function parameter indentation in nir_opt_barriers.c

The first parameter should be on the first line, and any subsequent
lines should line up.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

zink: re-rework i/o variable handling to make having variables entirely optional

old variables are now only used for copying names if possible, which should
make it possible for zink to process shaders which have no variables at all

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: use right function to get src_type in eliminate_io_wrmasks

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: add a new linker pass to handle mismatched i/o components

this is the inverted version of rewrite_read_as_0 which tests for mismatched
component i/o on a given location and rewrites the inputs to zero if the
producer shader didn't write to the component

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: create new vars without copying existing ones

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: use explicit sizing for builtins when creating variables

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: use MAX_PATCH_VERTICES directly for arrayed io var sizing

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: use explicit stride from types instead of copying old_var stride

should be no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: simplify an arrayed io check during variable creation

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: use nir_io_semantics::num_slots for indirect var creation

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: delete some bindless io lowering code

now that variables are pre-converted this is no longer necessary

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: fix typing on bindless io lowering

with lowered io this should always be an ivec2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: reorder bindless io lowering

should be no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: set is_xfb=false for all i/o variables

this can affect streamout generation, even though it so far hasn't

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>

zink: ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: handle multi-plane implicit sync

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: handle implicit sync for dmabufs

this adds explicit queue transitions to FOREIGN at the end of the batch
for all written-to dmabufs, then also adds signal/wait semaphores
using the dmabuf fds

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: hook up cached fd semaphore usage for batch signal/waits

not yet used, matches handling of normal semaphores

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: add a util for getting cached fd semaphores

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: add a screen cache for fd semaphores

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: add another submitinfo for fd semaphore waits

these are semaphores created with VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
and can't be cached with the others

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: make submitinfo handling easier to manage with enum

this was starting to get hard to read

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: add a third submitinfo (unused for now)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: make zink_resource_image_barrier2_init public

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

zink: use a pointer to simplify submit struct mechanics

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>

venus: expose KHR_external_fence/sempahore_fd extensions

Re-purpose renderer has_external_sync to cover explicit sync emulation
in venus, so that we don't have to add a new flag to distinguish the
emulation path enablement for virtgpu and vtest.

This is to unblock zink implicit sync hanlding against venus for now,
and soon we should migrate to virtgpu fence passing.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25127>

ci: drop clover leftover

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24098>

meson: use llvm-config instead of cmake to fix linking errors with meson 1.2.1

The cmake path picks a random LLVM in /usr, which happens to be 32-bit LLVM,
which fails to link with 64-bit Mesa. This is a meson, cmake, or LLVM bug.

Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25042>

anv: Program and emit STATE_COMPUTE_MODE

Don't rely on the HW to set values correctly so just emit
STATE_COMPUTE_MODE with default values set to zero.

Also, this change includes workaround changes:-
   - 14015808183 (Parent HSD 14015782607)  - Need to emit pipe control
     with HDC flush and untyped cache flush set to 1 when CCS has
     non-pipelined state update with STATE_COMPUTE_MODE.
   - 14014427904 (Parent HSD 22013045878) - We need additional
     invalidate/flush when emitting non-pipelined state commands with
     multiple CCS enabled.

v2: (Tapani)
- Use lineage HSD numbers for check
- Don't use poisoned WA directly
- Use intel_needs_workaround helper

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24508>

intel/genxml: Add STATE_COMPUTE_MODE instruction

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24508>

iris: Enable always flush cache with DEBUG_STALL option

With DEBUG_STALL option, enable always cache flush option for debugging
purpose that aligns with anv.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25108>

radv: Don't use the depth image view for depth bias emission

If the application records a secondary command buffer that inherits
a render pass without specifying a framebuffer, we should still be able
to emit the depth bias state properly.

Fixes: 266b2cf ("radv: implement VK_EXT_depth_bias_control")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9588
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25018>

radv/amdgpu: Use rwlock to protect access to virtual BOs.

Vulkan provides no external synchronization guarantees on sparse memory
objects. Use a per-BO rwlock to prevent reading data mid-update.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24806>

anv: bound image usages to the associated queue family

When applying barriers for image transitions, we're currently
considering all possible usages of an image. But when running on a
compute only queue for example, the usage of an image will never be
one of those :
   - VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
   - VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
   - VK_IMAGE_USAGE_TRANSIENT_ATTACHMENT_BIT
   - VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
   - VK_IMAGE_USAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR

Removing unused usages for the compute queue allows us to reduce the
scope of the VK_IMAGE_LAYOUT_GENERAL for example. This a bunch of
transition operation that are completely useless when dealing with
barriers on the compute queue.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25092>

ci/b2c: drop logic to remove install.tar

It's still buggy, and it turns out `mcli` has some logic to check if
a file really needs to be re-uploaded, so this doesn't actually change
much to the time uploads take.

This effectively reverts https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24196

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25114>

anv: remove aux checking asserts

Zink is running into those asserts on CI. The problem is that with non
auxilary modifiers like I915_FORMAT_MOD_Y_TILED, we might still
allocate larger buffers with IMPLICIT_CCS.

This isn't a complete fix, the real fix with come with
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003 where
we stop overallocating and those assert will match the private binding
allocation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 569f80f2df ("anv: Reduce accesses of isl_mod_info->aux_usage")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25099>

radv: remove useless PIPELINE_CREATE_2_LIBRARY_BIT check for retained shaders

VK_PIPELINE_CREATE_2_RETAIN_LINK_TIME_OPTIMIZATION_INFO_BIT_EXT is only
allowed for pipeline libs, so VK_PIPELINE_CREATE_2_LIBRARY_BIT_KHR
should also be set.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25110>

frontends/va: Flush after unmapping VAImageBufferType

If application changed image data we need to flush on unmap to make the
changes visible. This will also flush if the mapping was used only for
reading, but we can't know that as vaMapBuffer doesn't have a parameter
to specify if read or write is requested.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9774

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25102>

nir/opt_algebraic: remove broken fddx/fddy patterns

These patterns are broken in the following scenario:

%1 = f2fmp %0
%2 = fddx %1
%3 = ... // non quad uniform
if %3 {
   %4 = f2f32 %2
   ...
}

Which would turn into

%3 = ...
if %3 {
   %4 = fddx %0
   ...
}

Yet another example that shows why derivative instructions should be
be intrinsics, not alu.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25014>

llvmpipe: enable f16 paths on aarch64.

Karol noticed luxmark didn't work, and this seems to fix it.

Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25104>

radv: do not use pre-compiled prologs when VS is compiled separately

This wouldn't work for VS+TCS or VS+GS if they are compiled separately
on GFX9+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>

radv: adjust emitted prolog regs for merged shaders compiled separately

It should also be the merged shader stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>

radv: adjust next stage for VS prologs and merged shaders compiled separately

It should be the merged shader stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>

aco/gfx11: don't use bfe for local_invocation_id if the others are always 0

Foz-DB GFX1100:
Totals from 4469 (3.37% of 132657) affected shaders:
Instrs: 3895053 -> 3893529 (-0.04%); split: -0.04%, +0.00%
CodeSize: 20244128 -> 20220952 (-0.11%); split: -0.11%, +0.00%
Latency: 37864147 -> 37862227 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 5578100 -> 5576469 (-0.03%); split: -0.03%, +0.00%
SClause: 108336 -> 108343 (+0.01%); split: -0.00%, +0.01%
Copies: 275897 -> 275900 (+0.00%); split: -0.00%, +0.00%

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24514>

tu: Call tu_cs_dbg_stomp_regs with appropriate GPU gen

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25098>

tu: Exclude SP_UNKNOWN_AE73 from reg stomping

There is a guess that GPU may not be able to handle different values of
certain debug register between BR/BV. This one causes GPU to hang.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25098>

radv/sdma: use correct limits for gfx10.3

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>

radv/sdma: use multiple commands if required

Instead of failing the copy we can use multiple chunks.

This codepath shouldn't really be used since the source
image should usually be tiled but it still better to not
fail when possible.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>

radeonsi/sdma: use multiple commands if required

Instead of failing the copy we can use multiple chunks.

This codepath shouldn't really be used since the source
image should usually be tiled but it still better to not
fail when possible.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>

ci: taking igalia farm offline

We're having internet issues, everything is extremely slow.

nir: remove unused param from nir_alu_src_copy()

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>

nir: remove unused nir_src_copy()

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>

nir: replace use of nir_src_copy()

Since 03b2c34793b6 nir_src_copy() no longer does anything useful,
it will be removed in the following patch.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>

zink: always add a per-prog ref for gpl libs

previously non-separable progs had their libs owned exclusively by
the shaders, which meant it was possible for a background compile job
to crash while the context was being destroyed when accessing libs
which no longer had active shaders

fixes #9234

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25088>

radv: Use a double jump to limit nops in DGC for dynamic sequence count.

Some RGP data showing that a large amount of NOPs might be a performance
concern.

Some data from a Granite demo repurposed as benchmark:
  - with max_count = 16, actual draw count 1-4, the new path is ~5% slower
  - with max_count = 2048, actual draw count 1-4, the new path is >2x as fast.
  - with max_count = 16384, actual draw count 1-4, the new path is >7x as fast.

Due to the new path being slower in e.g. small cmdbuffers I added a heuristic.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25046>

ci/traces: extend no-output timeout by 5 minutes

This should help us handling possibly slower downloads of the traces,
which leads into piglit not printing anything on the output.

After Infra will get stabilized again, needs to be reverted.

Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25097>

radv: avoid emitting THREAD_TRACE_MARKER for predicated draws/dispatches

This confused RGP for example when DGC calls are skipped.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25060>

radv: skip DGC calls when the indirect sequence count is zero with a predicate

Starfield has a lot of empty ExecuteIndirect() calls. This optimizes
them by using the indirect sequence count as predicate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25060>

radv/ci: use the default kernel on vkcts-navi10

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7888
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25095>

radv/ci: drop the auto-reboot-on-hang for vkcts-navi10

Anecdotal evidence seems to suggest this is not happening anymore, so
let's try dropping it and see how it fares!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25095>

ir3/lower_tex_prefetch: Fix crash with lowered load_barycentric_at_offset

ir3_nir_lower_tex_prefetch expects src0 of load_interpolated_input to
be intrinsic, however this assumption broke when src0 is
load_barycentric_at_offset and is lowered in series of alu instructions.

 32x2  %1121 = @load_barycentric_at_offset (%1120) (interp_mode=0)
 32x4  %1118 = @load_interpolated_input (%1121, %1116 (0x0)) ...
 32x2    %32 = vec2 %1118.x, %1118.y
 32x4    %37 = (float32)tex %36 (texture_handle), %34 (sampler_handle), %32 (coord), 0 (texture), 0 (sampler)

is lowered into:

 [...]
 32      %54 = ffma %46.y, %52, %50
 32      %55 = ffma %46.y, %53, %51
 32x2    %56 = vec2 %54, %55
 32x4    %57 = @load_interpolated_input (%56, %25 (0x0))
 [...]

Crash backtrace:

 #5  in __GI___assert_fail (assertion=0x7ff6692328 "parent && parent->type == nir_instr_type_intrinsic",
     file=0x7ff66921c8 "nir.h", line=2536, function=0x7ff6692630 <__PRETTY_FUNCTION__.13> "nir_instr_as_intrinsic")
     at assert.c:101
 #6  in nir_instr_as_intrinsic (parent=0x7fd4b648e8) at nir.h:2536
 #7  in coord_offset (ssa=0x7fd4b649d0) at ir3_nir_lower_tex_prefetch.c:77
 #8  in coord_offset (ssa=0x7fd4b64a90) at ir3_nir_lower_tex_prefetch.c:48
 #9  in ir3_nir_coord_offset (ssa=0x7fd4b64a90) at ir3_nir_lower_tex_prefetch.c:104
 #10 in lower_tex_prefetch_block (block=0x7fd482c100) at ir3_nir_lower_tex_prefetch.c:185
 #11 in lower_tex_prefetch_func (impl=0x7fd4aa0890) at ir3_nir_lower_tex_prefetch.c:218
 #12 in ir3_nir_lower_tex_prefetch (shader=0x7fd4942b10) at ir3_nir_lower_tex_prefetch.c:242

Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25096>

v3dv: bump up MAX_UNIFORM_BUFFERS to 16

We currently expose 12 but that becomes 11 when running on Zink
since Mesa's state tracker is aware that the first one is reserved
for its own constant buffer, and the minimum number of UBOs required
by GL is 12, so Zink won't be able to expose UBO support.

Bump it up to 16 to meet Zink requirements, which is what we offer
on V3D.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9764
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25093>

radv: Fix dumping vertex descriptors with RADV_DEBUG=hang.

Adding 3 words should be done before the uint32_t ** cast. This is in
line with other places which uses pointer arithmetic on trace_id_ptr.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25081>

pvr: Add VK_KHR_driver_properties

This commit will implement the VK_KHR_driver_properties extension.
At the moment, the extension is disabled, because the current conformance
test version does not include the Imagination driver ID. The extension
can be enabled after conformance test version 1.3.6.0.

Co-Authored-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24927>

pps-producer: add ability to select device with DRI_PRIME

When running with multiple Intel cards in a system, having the ability
to select the device recording performance data is useful.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25051>

radv: Fix IB size for RADV_DEBUG=hang.

cs->base.cdw here is the size of the last CS in the chain, but we are
passing in the first CS in the chain to begin decoding. Hence,
cs->ib_buffers[0].cdw is the correct size here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25061>

mesa: disable snorm readpix clamping with EXT_render_snorm

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25054>

radv: fix interactions with primitives generated queries and pipeline stats

SAMPLE_STREAMOUTSTATS requires PIPELINESTAT_START to be enabled,
otherwise the hw doesn't count anything.

This fixes
dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_2.*
on GFX8. GFX6-9 are probably also affected by this bug, but with NGG
these queries are slightly different and don't use legacy streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25049>

anv: Copy/Clear MSAA images over companion RCS while we are on compute

When we have MSAA copy/clear operation on the compute queue, use the
companion RCS command buffer to carry out copy/clear operations.

v2: (Sagar)
- Flush cache according to command buffer
- Invalidate AUX when we create new companion RCS command buffer if
  platform support AUX TT.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Extract batch print code to anv_print_batch helper

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Skip layout transition on the compute queue

v2: (Nanley)
- Make sure we skip layout transition during queue ownership transfer

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Add secondary companion RCS cmd buffer to primary

Add secondary buffer's companion RCS command buffer to primary buffer's
companion RCS command buffer for execution if secondary RCS is valid.

v2: (Lionel)
- Fix the primary companion RCS check
- Set batch error

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Execute an empty batch to sync main and companion RCS batch

We need to synchronize main (CCS/BCS) and companion rcs batch, so let's
create an empty batch and make both the batches (CCS/BCS) and companion
RCS batch wait on empty sync batch and signal the fence.

Reason to execute the empty batch is we need to make sure the companion
RCS batch finish as soon as the CCS/BCS batch finish. Preemption could
prevent the companion RCS batch execution and we might end up destroying
the CCS/BCS batch before companion RCS finishes.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Setup companion RCS command buffer submission

Add all the wait fences from the main (CCS/BCS) command buffer to the
companion RCS command buffer so that the companion RCS batch starts at
the same time as the main (CCS/BCS) batch.

v2:
- Drop unncessary flush (Jose)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Execute RCS init batch on companion RCS context/engine

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Move compute specfic bits under compute queue init

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Create companion RCS engine

We need to create companion RCS engine when there is CCS/BCS engine
creation requested.

v2:
- Factor out anv_xe_create_engine code in create_engine (Jose)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: create individual logical engines on i915 when possible

This enables us to create more logical engines than HW engines are
available. This also brings the uAPI usage closer to what is happening
on Xe.

Rework: (Sagar)
- Correct exec_flag at the time of submission
- Handle device status check
- Set queue parameters

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

intel: Pass virtual memory address space ID while creating context

In future patches, we will be creating a separate companion RCS engine
and each engine is created with it's own address space, and we really
don't want. CCS and RCS engine writes should be visible to each other in
order to get the wait/signal mechanism working.

v2:
- Move drm_i915_gem_context_create_ext_setparam out of if block (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

intel: Add helper to create/destroy i915 VM

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Handle companion RCS in end/destory/reset code path

If we have valid companion RCS command buffer, we should
end/destroy/reset in the same fashion as of main command buffer.

v2:
- Add lock around anv_cmd_buffer_destroy (Sagar)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Split out End/Destroy/Reset cmd buffer code into helper

Since we are going to have companion RCS command buffer, we need to
end/destroy/reset companion RCS command buffer similar to main (CCS/BCS)
command buffer.

It's better to split out common code into helper function so that we can
use it later in this series.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

anv: Add helper to create companion RCS command buffer

This helper takes the main command buffer as input and then create a
companion RCS command buffer.

v2:
- Rename anv_get_render_queue_index helper to
  anv_get_first_render_queue_index (Jose)
- Rename RCS command buffer to companion RCS command buffer (Lionel)
- Add early return in anv_get_first_render_queue_index (Lionel)
- Add lock around the function (Jose)
- Move companion rcs command pool creation in device create (Sagar)
- Reset companion RCS cmd buffer (Sagar)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>

v3dv: handle pPlaneLayouts in VkImageDrmFormatModifierExplicitCreateInfoEXT

We have been ignoring these completely until now. V3D isn't very flexible
regarding image layouts anyway, so for the most part we require that
whatever the user puts here matches exactly what the driver would compute
while setting up the slices. The only exceptions are plane offsets which
and array strides.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9742
Tested-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25074>

v3dv: be more precise in vkGetImageSubresourceLayout

Only return non-zero values for arrayPitch and depthPitch if
they make sense for the image type.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25074>

glsl: ir_function_param_visitor::visit_enter always true condition

The condition

!param->type->is_vector() || !param->type->is_scalar()

alawys evaluates to true:

* type is not scalar or vector -> true
* type is vector, i.e. num_components > 1 -> num_components == 1 is
  false and !is_scalar() == true
* type is scalar, i.e. num_components == 1 -> num_components > 1 is
  false and !is_vector() == true

There is no comment explaining why such code has been written, therefore
this seems to be a mistake.

To maintain consistency with the surrounding code,
glsl_type_is_scalar_or_vector has been used instead of
replacing || with &&.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24914>