platform/upstream/mesa.git
14 months agovc4/ci: re-enable VC4 testing
Juan A. Suarez Romero [Fri, 12 May 2023 09:10:07 +0000 (11:10 +0200)]
vc4/ci: re-enable VC4 testing

But keeps piglit's quick_gl disabled, as it contains the test causing
the GPU resets.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22982>

14 months agoamd/drm-shim: Update docs for more devices.
Bas Nieuwenhuizen [Thu, 11 May 2023 23:08:27 +0000 (01:08 +0200)]
amd/drm-shim: Update docs for more devices.

We don't have to update the docs for every new entry.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22975>

14 months agoamd/drm-shim: Add raphael&mendocino, polaris12 and gfx1100.
Bas Nieuwenhuizen [Thu, 11 May 2023 20:49:18 +0000 (22:49 +0200)]
amd/drm-shim: Add raphael&mendocino, polaris12 and gfx1100.

Decided to follow the chip names pretty much.This set happens to be
what is in my workstation currently.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22975>

14 months agoamd/drm-shim: Add vangogh entry.
Bas Nieuwenhuizen [Thu, 11 May 2023 20:34:28 +0000 (22:34 +0200)]
amd/drm-shim: Add vangogh entry.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22975>

14 months agoanv: handle missing astc for gfx125 in CreateImageView
Tapani Pälli [Wed, 3 May 2023 04:13:07 +0000 (07:13 +0300)]
anv: handle missing astc for gfx125 in CreateImageView

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22818>

14 months agoradv: configure PA_CL_VRS_CNTL entirely from the cmd buffer
Samuel Pitoiset [Wed, 10 May 2023 09:34:19 +0000 (11:34 +0200)]
radv: configure PA_CL_VRS_CNTL entirely from the cmd buffer

We already have all the information needed to configure it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22942>

14 months agoradv: re-emit fragment shading rate state when PA_CL_VRS_CNTL changes
Samuel Pitoiset [Wed, 10 May 2023 09:12:06 +0000 (11:12 +0200)]
radv: re-emit fragment shading rate state when PA_CL_VRS_CNTL changes

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22942>

14 months agoradv: dirty the dynamic vertex input state only when needed
Samuel Pitoiset [Wed, 10 May 2023 10:44:48 +0000 (12:44 +0200)]
radv: dirty the dynamic vertex input state only when needed

This shouldn't be necessary when the VS doesn't have a prolog.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22944>

14 months agoradv: reset the emitted VS prolog when a new vertex shader is bound
Samuel Pitoiset [Wed, 10 May 2023 10:41:21 +0000 (12:41 +0200)]
radv: reset the emitted VS prolog when a new vertex shader is bound

When a new vertex shader is bound, the VS prolog needs to be
re-emitted, and this allows us to avoid tracking if the pipeline is
dirty.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22944>

14 months agohasvk: avoid assert due to unsupported format
Iván Briano [Fri, 12 May 2023 02:48:39 +0000 (19:48 -0700)]
hasvk: avoid assert due to unsupported format

Fixes: 0a4c92b646f ("hasvk: Use the common vk_ycbcr_conversion object")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9011
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22978>

14 months agoanv: Enable MCS init with ISL_AUX_OP_AMBIGUATE
Nanley Chery [Fri, 14 Apr 2023 20:10:54 +0000 (13:10 -0700)]
anv: Enable MCS init with ISL_AUX_OP_AMBIGUATE

Up until now, we have been initializing MCS with fast clears. This is
mostly safe, but there's a corner case that can be an issue.

The issue is with a workaround for MCS that requires the sampler not see
any fast-cleared blocks for certain surfaces (14013111325). Even though
we have been initializing MCS with fast clears, we expect most
applications to be safe because we expect that they would only sample
the samples they've rendered to previously (and the render would've
removed the fast-cleared blocks). In other words we don't expect that
apps would transition from VK_IMAGE_LAYOUT_UNDEFINED to
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL and start sampling immediately.

If an application took the unexpected path of sampling undefined
samples, it's possible they'd hit the issue described in the workaround.

Fix this corner case by using an ambiguate to initialize MCS.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>

14 months agoanv: Drop the MCS initialization performance warning
Nanley Chery [Mon, 1 May 2023 18:54:20 +0000 (11:54 -0700)]
anv: Drop the MCS initialization performance warning

The comment above the warning explains that not all bit patterns are
necessarily valid. While we're at it, fix a typo in that comment.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>

14 months agoiris: Enable MCS init with ISL_AUX_OP_AMBIGUATE
Nanley Chery [Fri, 14 Apr 2023 00:46:13 +0000 (17:46 -0700)]
iris: Enable MCS init with ISL_AUX_OP_AMBIGUATE

Add support for using BLORP's ambiguate pass to initialize MCS instead
of mapping and memsetting it on the CPU. Note that this won't be used if
the first operation on the MSAA layer is a fast clear.

Since we're no longer mapping, this removes a blocker towards getting
MCS_CCS enabled in small-BAR mode.

This functionality is difficult to test because of the way iris is set
up. It always tries to compress writes. So, a test would only read the
ambiguated MCS element if it tries to read from undefined samples.

To test this, I locally disabled fast clears and rendering with MCS (via
iris_resource_render_aux_usage). I continued to allow sampling with MCS
in iris_resource_texture_aux_usage. So, writes go directly to the main
surface and reads go through the ambiguated MCS surface.

When I then ran the test group, dEQP-GLES3.functional.multisample.*, all
48/64 supported tests passed on my Ice Lake. If I slightly changed
BLORP's ambiguate pass, I observed several tests failing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>

14 months agointel: Implement ISL_AUX_OP_AMBIGUATE for MCS
Nanley Chery [Fri, 14 Apr 2023 00:46:41 +0000 (17:46 -0700)]
intel: Implement ISL_AUX_OP_AMBIGUATE for MCS

Implement the ambiguate operation for MCS. This clears MCS layers with a
sample-dependent "uncompressed" value that tells the sampler to go look
at the main surface.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>

14 months agoiris: Add a barrier to iris_mcs_partial_resolve
Nanley Chery [Fri, 14 Apr 2023 23:45:33 +0000 (16:45 -0700)]
iris: Add a barrier to iris_mcs_partial_resolve

Partial resolves read from the MCS and write to the MSAA surface.
Add a texture barrier to prepare for the reads.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4179
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>

14 months agointel/isl: Bump the MCS halign value for BDW+
Nanley Chery [Wed, 10 May 2023 19:25:18 +0000 (12:25 -0700)]
intel/isl: Bump the MCS halign value for BDW+

Select a horizontal alignment value that matches the main MSAA surface.

We need a valid horizontal alignment to perform MCS ambiguates. The
halign value doesn't actually affect test behavior, but it is validated
by isl_surf_fill_state. We currently have an invalid halign for gfx125.
This patch fixes that.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>

14 months agoail: Add MSAA tests
Asahi Lina [Wed, 10 May 2023 08:31:43 +0000 (17:31 +0900)]
ail: Add MSAA tests

This tests the following matrix:
- Format: RGBA8Unorm, RGBA16Unorm, RGBA32Float
- Samples: 2 or 4
- Layers: 1 or 2
- Width: Interesting values 1..4097
- Height: Interesting values 1..4097

Compression is based on the dimensions (that is, everything that can be
compressed is). This test compares both the total texture size and the
compression metadata offset.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoail: Handle larger block sizes
Alyssa Rosenzweig [Thu, 2 Mar 2023 15:05:16 +0000 (10:05 -0500)]
ail: Handle larger block sizes

We need to support up to 16 bytes/sample * 4 samples/pixel = 64 bytes/pixel for
multisampling to work with formats like RGBA32F.

Fixes dEQP-GLES3.functional.fbo.msaa.4_samples.rgba32f

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Use ail_can_compress() in agx_compression_allowed()
Asahi Lina [Wed, 10 May 2023 08:30:33 +0000 (17:30 +0900)]
asahi: Use ail_can_compress() in agx_compression_allowed()

This moves the compression size threshold logic into ail, where
it belongs.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoail: Implement multisampling for compression meta calculation
Asahi Lina [Sun, 26 Feb 2023 06:46:57 +0000 (15:46 +0900)]
ail: Implement multisampling for compression meta calculation

For multisampled textures, the decision about whether to compress or not
is based on the effective width and height in samples, not pixels.

Introduce ail_can_compress() to encode this logic in ail, so the driver
can use it to decide whether to compress or not before the full layout
is determined.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Make bo->writer_syncobj atomic
Asahi Lina [Wed, 10 May 2023 07:02:27 +0000 (16:02 +0900)]
asahi: Make bo->writer_syncobj atomic

BOs can be written from several contexts, so writing to this member is
racy. We only care about this for the purposes of exporting BOs after a
submission (and if the app is racing writers/submissions at that point
all bets are off), so just keeping track of the last written value is
sufficient.

Switch to atomic operations to eliminate the race, and drop the assert
in the batch cleanup path that no longer holds when the BO might have
been written to from another context.

Fixes: asahi/mesa#20

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Lazily initialize batch state on first draw
Asahi Lina [Wed, 10 May 2023 06:57:55 +0000 (15:57 +0900)]
asahi: Lazily initialize batch state on first draw

We track buffers written by batches, but this gets messy when we end up
with an empty batch that is never submitted, since then it might have
taken over writer state from a prior already submitted batch (for its
framebuffers).

Instead of trying to track two tiers of resource writers, let's just
defer initializing batch state until we know we have a draw (or compute
launch, or clear). This means that if a batch is marked as a writer for
a buffer, we know it will not be an empty batch.

This should be a small performance win for empty batches (no need to
emit initial VDM state or run the writer code), but more impontantly it
eliminates the empty batch writer state revert corner case.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Partially identify some missing index list stuff
Asahi Lina [Thu, 11 May 2023 05:34:36 +0000 (14:34 +0900)]
asahi: Partially identify some missing index list stuff

Still unclear what the extra 2 blocks do, but at least we know the
size/order now.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Add some more system registers
Asahi Lina [Thu, 11 May 2023 05:32:01 +0000 (14:32 +0900)]
asahi: Add some more system registers

Core and opfifo stuff from the compute helper blob, vm_slot because it
was the only one changing when I poked around yesterday and it hit me
what it was ^^

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Fix check for sprite coord mode in agx_bind_rasterizer_state
Asahi Lina [Wed, 10 May 2023 10:42:17 +0000 (19:42 +0900)]
asahi: Fix check for sprite coord mode in agx_bind_rasterizer_state

We need to set ctx->rast = so after comparing them.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Add missing stdbool include to lib/hexdump.h
Asahi Lina [Wed, 10 May 2023 10:41:28 +0000 (19:41 +0900)]
asahi: Add missing stdbool include to lib/hexdump.h

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Disable tilebuffer write masking optimization
Asahi Lina [Wed, 10 May 2023 06:11:36 +0000 (15:11 +0900)]
asahi: Disable tilebuffer write masking optimization

This seems to flake some dEQPs due to some kind of race/UB (which
doesn't even always cause the dEQPs to fail due to leeway in the image
comparison, since the problem is usually just a few pixels, but it's
there).

I spent a bunch of time trying other flags/things, and almost everything
changed the bad pixel pattern randomly but nothing fixed it. Let's
revisit this one later, since it looks like a pretty deep rabbit hole.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Make framebuffer texture barriers a no-op
Asahi Lina [Wed, 10 May 2023 05:11:26 +0000 (14:11 +0900)]
asahi: Make framebuffer texture barriers a no-op

Framebuffer fetch is coherent, so there is no need for barriers here.
This avoids pointless flushing if an app calls glBlendBarrier().

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Implement create_fence_fd and fence_server_sync
Asahi Lina [Wed, 3 May 2023 11:32:23 +0000 (20:32 +0900)]
asahi: Implement create_fence_fd and fence_server_sync

Apparently we were still missing some fence stuff, and it started
crashing Firefox in apitrace? I'm not sure why we never noticed this
before, but it's trivial enough. Cargo culted from Panfrost.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agoasahi: Implement memory_barrier
Asahi Lina [Wed, 3 May 2023 11:32:00 +0000 (20:32 +0900)]
asahi: Implement memory_barrier

Cargo culted from panfrost.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22971>

14 months agointel: Disable shader cache when executing intel_clc during the build
Matt Turner [Thu, 11 May 2023 17:51:25 +0000 (13:51 -0400)]
intel: Disable shader cache when executing intel_clc during the build

With the shader cache enabled, intel_clc attempts to write to ~/.cache.
Many distributions' build systems limit file-system access, and will
kill the process thus causing the build to fail.

Fixes: 639665053fa ("anv/grl: Build OpenCL kernels")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22968>

14 months agoradv: improve externalMemoryFeatures for android ahb
Chia-I Wu [Fri, 21 Apr 2023 05:37:02 +0000 (22:37 -0700)]
radv: improve externalMemoryFeatures for android ahb

VK_EXTERNAL_MEMORY_FEATURE_DEDICATED_ONLY_BIT should always be set, as
required by the spec.

VK_EXTERNAL_MEMORY_FEATURE_EXPORTABLE_BIT should be set when
radv_ahb_format_for_vk_format knowns the format.  That is,
radv_create_ahb_memory should at least know how to call
AHardwareBuffer_allocate.

VK_EXTERNAL_MEMORY_FEATURE_IMPORTABLE_BIT is always set.  We can't know
if gralloc can allocate the format/flags/usage combo or not (gralloc
might use a private format for the combo).

Fixed
dEQP-VK.api.external.memory.android_hardware_buffer.image_formats.*.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agoanv,hasvk: android ahb is not always exportable
Chia-I Wu [Fri, 21 Apr 2023 05:34:59 +0000 (22:34 -0700)]
anv,hasvk: android ahb is not always exportable

anv_ahb_format_for_vk_format needs to know the format at least.  There
is no guarantee that AHardwareBuffer_allocate will succeed, but we are
reluctant to check with AHardwareBuffer_isSupported which may
test-allocate internally and is expensive.

v2: add anv_ahb_format_for_vk_format to anv_android_stubs.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agovulkan: add vk_image_format_to_ahb_format
Chia-I Wu [Fri, 21 Apr 2023 05:32:52 +0000 (22:32 -0700)]
vulkan: add vk_image_format_to_ahb_format

There should be no functional change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agoanv,hasvk,radv: do not fall back to AHARDWAREBUFFER_FORMAT_BLOB
Chia-I Wu [Fri, 21 Apr 2023 05:27:13 +0000 (22:27 -0700)]
anv,hasvk,radv: do not fall back to AHARDWAREBUFFER_FORMAT_BLOB

When allocating a VkDeviceMemory exportable as AHB, it seems incorrect
to fall back to AHARDWAREBUFFER_FORMAT_BLOB when the image has no known
AHB format.  We should fail the allocation instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agovulkan: add vk_ahb_format_to_image_format
Chia-I Wu [Fri, 21 Apr 2023 05:21:04 +0000 (22:21 -0700)]
vulkan: add vk_ahb_format_to_image_format

There should be no functional change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agovulkan: define inline stubs when android api level < 26
Chia-I Wu [Fri, 21 Apr 2023 06:46:30 +0000 (23:46 -0700)]
vulkan: define inline stubs when android api level < 26

This allows us to reduce ANDROID #ifdef's.

v2: always include vk_android.h in radv_formats.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agovulkan: rename vk_image::ahardware_buffer_format
Chia-I Wu [Fri, 21 Apr 2023 01:02:23 +0000 (18:02 -0700)]
vulkan: rename vk_image::ahardware_buffer_format

Rename it to ahb_format.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agovulkan: make sure vk_image_view::format is never UNDEFINED
Chia-I Wu [Fri, 21 Apr 2023 05:09:26 +0000 (22:09 -0700)]
vulkan: make sure vk_image_view::format is never UNDEFINED

Remove redundant override in anv and hasvk as well.

Fixed
android.graphics.cts.BasicVulkanGpuTest#testBasicBufferImportAndRenderingExternalFormat
for radv.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agovulkan: make sure vk_image::format is never UNDEFINED
Chia-I Wu [Thu, 20 Apr 2023 23:58:17 +0000 (16:58 -0700)]
vulkan: make sure vk_image::format is never UNDEFINED

vk_image::android_external_format is only used for sanity check and is
removed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agohasvk: Use the common vk_ycbcr_conversion object
Chia-I Wu [Fri, 21 Apr 2023 05:07:05 +0000 (22:07 -0700)]
hasvk: Use the common vk_ycbcr_conversion object

Based on commit 30a91d333d1 ("anv: Use the common vk_ycbcr_conversion
object").

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agohasvk/android: Use VkFormat for externalFormat
Chia-I Wu [Fri, 21 Apr 2023 04:55:18 +0000 (21:55 -0700)]
hasvk/android: Use VkFormat for externalFormat

Same as commit 18feb32df0a ("anv/android: Use VkFormat for
externalFormat"), but for hasvk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agohasvk: Refactor Android externalFormat handling in CreateYcbcrConversion
Chia-I Wu [Fri, 21 Apr 2023 04:55:12 +0000 (21:55 -0700)]
hasvk: Refactor Android externalFormat handling in CreateYcbcrConversion

Same as commit 9fc046a87dc ("anv: Refactor Android externalFormat
handling in CreateYcbcrConversion"), but for hasvk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>

14 months agodzn: Enable KHR_shader_integer_dot_product
Jesse Natalie [Thu, 11 May 2023 02:50:40 +0000 (19:50 -0700)]
dzn: Enable KHR_shader_integer_dot_product

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>

14 months agomicrosoft/compiler: Enable packed dot product intrinsics for SM6.4+
Jesse Natalie [Thu, 11 May 2023 02:11:59 +0000 (19:11 -0700)]
microsoft/compiler: Enable packed dot product intrinsics for SM6.4+

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>

14 months agomicrosoft/compiler: Take inputs from callers before providing nir options
Jesse Natalie [Wed, 10 May 2023 20:48:01 +0000 (13:48 -0700)]
microsoft/compiler: Take inputs from callers before providing nir options

The base nir options were assuming all bit sizes were supported at
shader model 6.2. Multiple callers were then changing properties
based on actual support.

Standardize behavior by providing the majority of things that can
impact nir options when getting them. Some callers (e.g. meta blit
shaders or libclc) don't bother, because they are known to have
contents that are unaffected by these options. Other callers might
munge more properties afterwards, but this minimizes that.

Note that lower_helper_invocation was incorrectly being turned off
for SM6.6+ by some callers, despite load_helper_invocation being
unimplemented by the backend.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>

14 months agodzn: Enable 64-bit ints and floats
Jesse Natalie [Wed, 10 May 2023 20:47:28 +0000 (13:47 -0700)]
dzn: Enable 64-bit ints and floats

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>

14 months agod3d12: Convert from D3D shader model to Mesa shader model earlier
Jesse Natalie [Wed, 10 May 2023 20:39:56 +0000 (13:39 -0700)]
d3d12: Convert from D3D shader model to Mesa shader model earlier

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>

14 months agospirv2dxil: Support int64 and doubles
Jesse Natalie [Wed, 10 May 2023 23:02:46 +0000 (16:02 -0700)]
spirv2dxil: Support int64 and doubles

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>

14 months agozink: Always set a blend state for shader-db
Alyssa Rosenzweig [Wed, 10 May 2023 18:01:23 +0000 (14:01 -0400)]
zink: Always set a blend state for shader-db

If we're compiling shaders in shader-db, with shader-db's ./run and
ZINK_DEBUG=shaderdb, we won't get much state set on the graphics pipeline, since
shader-db doesn't actually do any rendering. For a driver like RADV, that is
*almost* ok... Since we use dynamic vertex input, we don't need to make up any
state for vertex inputs; since we use dynamic rendering, we don't need to make
up any render attachments. All of that being said, we *do* need to make up a
blend state to ensure that the Vulkan driver doesn't optimize away all of
store_derefs in the fragment shader (and in turn, optimize the entire fragment
shader away, if there are no image/SSBO writes.) So set the obvious blend state,
fixing fragment shaders in shader-db with zink + radv.

I don't know why other people would want to use Zink with shader-db, but for me
it's an easy way to test ACO, at least until radeonsi gains aco support.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22948>

14 months agospirv: Use NIR_PASS for spirv2nir --optimize
Caio Oliveira [Fri, 28 Apr 2023 16:46:10 +0000 (09:46 -0700)]
spirv: Use NIR_PASS for spirv2nir --optimize

This allows us to use NIR_DEBUG=print to see each step.
Also use an OPT macro to make code slightly more readable.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22764>

14 months agospirv: Do more on spirv2nir --optimize
Caio Oliveira [Fri, 28 Apr 2023 16:40:25 +0000 (09:40 -0700)]
spirv: Do more on spirv2nir --optimize

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22764>

14 months agointel/mi_builder: fixup tests for newer kernel uAPI
Lionel Landwerlin [Thu, 11 May 2023 12:08:37 +0000 (15:08 +0300)]
intel/mi_builder: fixup tests for newer kernel uAPI

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22966>

14 months agoanv: Set memory types supported by Xe KMD
José Roberto de Souza [Thu, 27 Apr 2023 21:14:22 +0000 (14:14 -0700)]
anv: Set memory types supported by Xe KMD

Due the lack of APIs to set mmap modes, Xe KMD can't support the same
memory types as i915.
So here adding a i915 and Xe function to set memory types supported
by each KMD.

Iris function iris_xe_bo_flags_to_mmap_mode() has a table with all the
mmaps modes of each type of placement.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22906>

14 months agoradeonsi: Use vcn version instead of CHIP family for VCNs
Leo Liu [Mon, 1 May 2023 15:50:51 +0000 (11:50 -0400)]
radeonsi: Use vcn version instead of CHIP family for VCNs

Decouple it from CHIP family, based on HW query infomation.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>

14 months agoamd: Add vcn ip version info
Leo Liu [Mon, 1 May 2023 15:46:15 +0000 (11:46 -0400)]
amd: Add vcn ip version info

And make it support for kernel w/wo ip_discovery.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>

14 months agoradeonsi: Remove redundant vcn_decode from info
Leo Liu [Tue, 25 Apr 2023 16:20:10 +0000 (12:20 -0400)]
radeonsi: Remove redundant vcn_decode from info

Use the number of queue instead.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>

14 months agodzn: Fix segmentation fault when Direct3D 12 user mode
MouriNaruto [Thu, 11 May 2023 15:22:50 +0000 (23:22 +0800)]
dzn: Fix segmentation fault when Direct3D 12 user mode
driver from at least one of GPUs is not available.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22961>

14 months agoagx: Optimize multiplies
Alyssa Rosenzweig [Tue, 25 Apr 2023 17:52:32 +0000 (13:52 -0400)]
agx: Optimize multiplies

We have an imad instruction and our iadd has a small immediate shift on the
second source. Together, these allow expressing lots of integer multiplies more
efficiently. Add some rules to optimize these now that the backend compiler can
ingest the optimized forms.

Half-register changes are from load_const scheduling changing in some vertex
shaders.

   total instructions in shared programs: 1539092 -> 1537949 (-0.07%)
   instructions in affected programs: 167896 -> 166753 (-0.68%)

   total bytes in shared programs: 10543012 -> 10533866 (-0.09%)
   bytes in affected programs: 1218068 -> 1208922 (-0.75%)

   total halfregs in shared programs: 483180 -> 483448 (0.06%)
   halfregs in affected programs: 1942 -> 2210 (13.80%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

14 months agoagx: Fix packing of imsub instructions
Alyssa Rosenzweig [Fri, 28 Apr 2023 18:49:25 +0000 (14:49 -0400)]
agx: Fix packing of imsub instructions

The negate for imad is on the third source (a * b - c), not the second source.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

14 months agoagx: Handle imadshl_agx, imsubshl_agx
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:50:24 +0000 (14:50 -0400)]
agx: Handle imadshl_agx, imsubshl_agx

Same hardware instructions as iadd/isub/imad/imsub, just with the extra input
represented in NIR as required.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

14 months agonir: Model AGX-specific multiply-shift-add
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:37:07 +0000 (14:37 -0400)]
nir: Model AGX-specific multiply-shift-add

Models `(a * b) + (c << d)` in general, as implemented in various forms on AGX.
This will be fused with backend NIR opt algebraic rules, both for the literal
pattern as well as to strength reduce certain multiplications, e.g. replacing
a * 5 with `a + (a << 2)` expressed as imadshl_agx(a, 1, a, 2).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

14 months agoagx: Use nir_alu_src_as_uint
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:48:56 +0000 (14:48 -0400)]
agx: Use nir_alu_src_as_uint

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

14 months agopan/bi: Use nir_alu_src_as_uint
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:50:01 +0000 (14:50 -0400)]
pan/bi: Use nir_alu_src_as_uint

Fixes some theoretical issues with swizzle handling. Unsure if this could cause
actual end-to-end miscompiles.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

14 months agonir: Add nir_alu_src_as_uint helper
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:39:23 +0000 (14:39 -0400)]
nir: Add nir_alu_src_as_uint helper

We have a few ALU instructions that take a constant source. Technically, they
have a swizzle so you can't just nir_src_as_uint them, even though a bunch of
backends do. To help backends do the right thing, add a helper that's just as
easy to use that will chase the swizzle properly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

14 months agoanv: fixup workaround 16011411144
Lionel Landwerlin [Tue, 9 May 2023 08:34:05 +0000 (11:34 +0300)]
anv: fixup workaround 16011411144

We're missing it for the memcpy with streamout

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5cc4075f95 ("anv, iris: Add Wa_16011411144 for DG2")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22930>

14 months agoegl/loader: move crtc resource infrastructure as common helper
Tapani Pälli [Sun, 7 May 2023 18:28:54 +0000 (21:28 +0300)]
egl/loader: move crtc resource infrastructure as common helper

Patch moves (and renames) the infrastructure to fix compilation
failures when dri3 is not enabled in the build.

Fixes: 3170b63314f ("loader: Add infrastructure for tracking active CRTC resources");
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8476
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22897>

14 months agoaco: also reassign p_extract_vector post ra
Georg Lehmann [Tue, 2 May 2023 09:54:26 +0000 (11:54 +0200)]
aco: also reassign p_extract_vector post ra

Foz-DB Navi21:
Totals from 1223 (0.91% of 134864) affected shaders:
CodeSize: 6923888 -> 6913516 (-0.15%)
Instrs: 1293744 -> 1291151 (-0.20%)
Latency: 16928653 -> 16925035 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 2985304 -> 2984775 (-0.02%); split: -0.02%, +0.00%
VClause: 32260 -> 32319 (+0.18%)
SClause: 54952 -> 54949 (-0.01%)
Copies: 83968 -> 81377 (-3.09%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22821>

14 months agoaco: Assert that operands have the same byte offset when reassigning split vectors
Georg Lehmann [Wed, 3 May 2023 09:24:19 +0000 (11:24 +0200)]
aco: Assert that operands have the same byte offset when reassigning split vectors

This can not happen because the post-RA optimizer doesn't support sub dword
writes at the moment, but everytime I look at this I wonder if there might
be a bug here.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22821>

14 months agovulkan/pipeline_cache: don't log warnings for internal caches
Daniel Schürmann [Thu, 4 May 2023 10:48:08 +0000 (12:48 +0200)]
vulkan/pipeline_cache: don't log warnings for internal caches

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22850>

14 months agoRevert "intel/compiler: make uses_pos_offset a tri-state"
Lionel Landwerlin [Wed, 10 May 2023 05:16:59 +0000 (08:16 +0300)]
Revert "intel/compiler: make uses_pos_offset a tri-state"

This reverts commit 5489033fa8568ecacafe32ceab36f89f2e14f3dc.

The problem I was trying to address is that we were programming the
3DSTATE_PS::PositionXYOffsetSelect bit differently with GPL (CENTROID)
than without (NONE).

I failed to understand that this bit also impacts the thread payload
layout. GPL fragment shaders don't know ahead of time if pos_offset is
going to be used. It'll be choosen at runtime base on push constant
bits. So we need to program this bit different just to have a payload
matching the compiled shader code.

This fixes the freedoom replay with GPL FS shader in SIMD32.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22938>

14 months agov3d/ci: annotate failures
Juan A. Suarez Romero [Thu, 11 May 2023 06:39:36 +0000 (08:39 +0200)]
v3d/ci: annotate failures

Annotate some of the failures with the root cause.

Remove also some tests that are actually skipped.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22953>

14 months agoamd/drm-shim: add amdgpu drm-shim
Chia-I Wu [Mon, 13 Mar 2023 21:35:55 +0000 (14:35 -0700)]
amd/drm-shim: add amdgpu drm-shim

This is enough to run offscreen apps such as vulkaninfo or deqp-vk.

v2: remove unnecessary idep_amdgfxregs_h dependency

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21892>

14 months agodrm-shim: apply file overrides for open
Chia-I Wu [Wed, 10 May 2023 18:27:42 +0000 (11:27 -0700)]
drm-shim: apply file overrides for open

loader_get_pci_driver calls os_read_file on linux to get the pci id, and
os_read_file uses open instead of fopen.

This allows loader_get_pci_driver to work rather than falling back to
loader_get_kernel_driver_name.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22951>

14 months agomicrosoft/compiler: Do basic I/O analysis for dependency tables
Jesse Natalie [Tue, 9 May 2023 21:57:08 +0000 (14:57 -0700)]
microsoft/compiler: Do basic I/O analysis for dependency tables

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22949>

14 months agomicrosoft/compiler: Allocate space for I/O and viewID dependency tables before instru...
Jesse Natalie [Mon, 8 May 2023 21:40:47 +0000 (14:40 -0700)]
microsoft/compiler: Allocate space for I/O and viewID dependency tables before instruction processing

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22949>

14 months agotu: Re-enable bufferDeviceAddressCaptureReplay
Danylo Piliaiev [Thu, 25 Aug 2022 15:25:30 +0000 (18:25 +0300)]
tu: Re-enable bufferDeviceAddressCaptureReplay

We cannot immidiately free VMA range when BO is freed, we have to
wait until kernel stops considered BO as busy and frees its internal
VMA range. Otherwise userspace and kernel VMA will get desynchronized.

To fix this and re-enable replaying of BDA we place BO's information
into a queue. The queue is drained:
- On BO allocation;
- When we cannot allocate an iova passed from the client.

For more information about this see:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/7106

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>

14 months agotu: Move queue deletion to last
Rob Clark [Wed, 10 May 2023 17:42:17 +0000 (10:42 -0700)]
tu: Move queue deletion to last

For zombie vma tracking, we'll need access to the queue at bo deletion
time.  This simplest way to make that work is just move queue deletion
to late in device teardown.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>

14 months agotu: Move VMA heap to the logical device
Danylo Piliaiev [Tue, 11 Oct 2022 15:51:08 +0000 (17:51 +0200)]
tu: Move VMA heap to the logical device

Since last commit drm fd is being created on per logical device
granularity, which means each logical device has its own
address space. So VMA heap could be moved to logical device.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>

14 months agotu: Create drm fd per logical device
Danylo Piliaiev [Tue, 11 Oct 2022 13:43:31 +0000 (15:43 +0200)]
tu: Create drm fd per logical device

The main reason is to simplify BO managment when
bufferDeviceAddressCaptureReplay would be enabled.

Having to track some BO information in physical device and some
info in logical device gets challenging when BOs are shared
between logical devices.

Other benefits:
- Isolation from hangs in other logical devices;
- Each logical device limited only by its own address space size.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>

14 months agoci/zink+anv: Skip a couple more long tests pre-merge.
Emma Anholt [Wed, 10 May 2023 18:24:59 +0000 (11:24 -0700)]
ci/zink+anv: Skip a couple more long tests pre-merge.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>

14 months agoci: Re-enable some piglit tests that should be fast enough post-uprev.
Emma Anholt [Mon, 8 May 2023 19:51:31 +0000 (12:51 -0700)]
ci: Re-enable some piglit tests that should be fast enough post-uprev.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>

14 months agoUprev Piglit to 536975d94a40cf76a69fcfa786c2513eccd0c989
Collabora's Gfx CI Team [Sat, 6 May 2023 00:04:20 +0000 (00:04 +0000)]
Uprev Piglit to 536975d94a40cf76a69fcfa786c2513eccd0c989
https://gitlab.freedesktop.org/mesa/piglit/-/compare/79a084c56b6dd79f7c3a97b57a72963121ebb1e6...536975d94a40cf76a69fcfa786c2513eccd0c989

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>

14 months agozink: Don't flag legacy_shadow_mask for RED-only reads in the shader.
Emma Anholt [Mon, 8 May 2023 23:37:09 +0000 (16:37 -0700)]
zink: Don't flag legacy_shadow_mask for RED-only reads in the shader.

It is very common in games to read just the .x channel of a vec4 shadow
result (since GL defaults to either LUMINANCE or RED depth mode depending
on context).  So, we can avoid shader recompiles to handle the other
components, in that case.

Fixes some recompiles in CS:GO.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>

14 months agozink: Fix silly void * type in rewrite_tex_dest.
Emma Anholt [Mon, 8 May 2023 22:31:19 +0000 (15:31 -0700)]
zink: Fix silly void * type in rewrite_tex_dest.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>

14 months agozink: Explain some of the current pathway for shadow sampling.
Emma Anholt [Mon, 8 May 2023 23:12:42 +0000 (16:12 -0700)]
zink: Explain some of the current pathway for shadow sampling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>

14 months agomesa: Fix precompile of GLSL programs with shadow samplers.
Emma Anholt [Tue, 9 May 2023 19:40:23 +0000 (12:40 -0700)]
mesa: Fix precompile of GLSL programs with shadow samplers.

Reduces fp variant recompiles on google's CS:GO trace on zink+anv from 115
to 31.

Fixes: 0843d4cbc354 ("nir: switch to a normal sampler for ARB program with not depth textures")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22928>

14 months agomesa: Fix debug logging of fp compile compare func.
Emma Anholt [Tue, 9 May 2023 19:21:35 +0000 (12:21 -0700)]
mesa: Fix debug logging of fp compile compare func.

When we're doing COMPARE_FUNC_ALWAYS, that's not part of a shader
precompile miss.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22928>

14 months agoac: enable SHADOW_GLOBAL_CONFIG for preemptible ib
Jiadong Zhu [Sat, 6 May 2023 09:35:05 +0000 (17:35 +0800)]
ac: enable SHADOW_GLOBAL_CONFIG for preemptible ib

SHADOW_GLOBAL_CONFIG is mandatory for mid command buffer preemmption.

Fixes: 69014d8c94f (radeonsi: implement CP register shadowing)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22916>

14 months agonir/lower_io: Emit less iadd(x, 0)
Konstantin Seurer [Sun, 7 May 2023 09:53:21 +0000 (11:53 +0200)]
nir/lower_io: Emit less iadd(x, 0)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22890>

14 months agofreedreno/a5xx+a6xx: Don't allocate LRZ for z32
Rob Clark [Sun, 7 May 2023 15:17:05 +0000 (08:17 -0700)]
freedreno/a5xx+a6xx: Don't allocate LRZ for z32

We don't do LRZ in this case, so no point in allocating the LRZ buffer.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: Actually use LRZ for ms
Rob Clark [Sun, 23 Apr 2023 17:48:41 +0000 (10:48 -0700)]
freedreno/a6xx: Actually use LRZ for ms

We know the z value after the fallback clear.  But we need to set
rsc->lrz_valid _after_ the fallback clear invalidates it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: Move LRZ clears to gmem
Rob Clark [Sun, 23 Apr 2023 14:21:33 +0000 (07:21 -0700)]
freedreno/a6xx: Move LRZ clears to gmem

If we have multiple LRZ clears, emit them all at once.  This also avoids
redundant LRZ clears if app does multiple clears in sequence.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: New subpass on mid-frame clears
Rob Clark [Sat, 22 Apr 2023 20:06:15 +0000 (13:06 -0700)]
freedreno/a6xx: New subpass on mid-frame clears

If we get a mid-frame clear, split out a new subpass rather than having
to fall-back to u_blitter clears.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: Per-subpass LRZ
Rob Clark [Sat, 22 Apr 2023 19:44:59 +0000 (12:44 -0700)]
freedreno/a6xx: Per-subpass LRZ

Allow the LRZ buffer to be re-allocated if a mid-frame depth clear
starts a new subpass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: Introduce batch subpasses
Rob Clark [Sat, 22 Apr 2023 18:00:05 +0000 (11:00 -0700)]
freedreno/a6xx: Introduce batch subpasses

Just the scaffolding for now, nothing actually creates multiple sub-
passes yet.  For now, only planning to use this for a6xx, as other
gens are doing clears on 3d.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: Split tile loads and clears
Rob Clark [Sat, 22 Apr 2023 17:36:36 +0000 (10:36 -0700)]
freedreno/a6xx: Split tile loads and clears

This will give better visibility in perfetto, and prepares for the next
commit where we could have per-subpass clears.

While we are at it, start adopting vulkan terms for tile load/store.  No
need to be pointlessly different.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: Switch to batch->cleared
Rob Clark [Sat, 22 Apr 2023 18:07:58 +0000 (11:07 -0700)]
freedreno/a6xx: Switch to batch->cleared

batch->fast_cleared will be per-subpass.  But we can use the cleared
bitmask instead in the few places where we just need to know if there
was a clear in any subpass.  For the conditional-ib it is even
preferable since we know a clear touched the contents of the tile so
we know what the result of the conditional would be.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: Simplify per-tile conditional IBs
Rob Clark [Sat, 22 Apr 2023 16:55:57 +0000 (09:55 -0700)]
freedreno/a6xx: Simplify per-tile conditional IBs

Handle the logic which decides between conditional or unconditional IB
in one place.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

14 months agofreedreno/a6xx: Add ctx->emit_sysmem()
Rob Clark [Wed, 19 Apr 2023 22:21:11 +0000 (15:21 -0700)]
freedreno/a6xx: Add ctx->emit_sysmem()

Once we introduce subpass, it won't be just a single IB.  But per
subpass clears + IB.  So interoduce a sysmem counterpart for
emit_tile().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>