York Sun [Sat, 21 Mar 2015 02:28:23 +0000 (19:28 -0700)]
armv8/ls2085aqds: Add support of LS2085AQDS platform
The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Prabhakar Kushwaha [Sat, 21 Mar 2015 02:28:22 +0000 (19:28 -0700)]
driver/ldpaa: Add support of WRIOP static data structure
Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC. Here Each WRIOP block supports
upto 64 DPMACs.
Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Bhupesh Sharma [Sat, 21 Mar 2015 02:28:20 +0000 (19:28 -0700)]
armv8/fsl-ch3: Add support to print RCW configuration
This patch adds support to print out the Reset Configuration Word
information.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Sat, 21 Mar 2015 02:28:19 +0000 (19:28 -0700)]
net/memac_phy: reuse driver for little endian SoCs
The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
is little endian, if not, the I/O access is big endian. Move fsl_memac.h
out of powerpc include.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
J. German Rivera [Sat, 21 Mar 2015 02:28:18 +0000 (19:28 -0700)]
drivers/fsl-mc: Changed MC firmware loading for new boot architecture
Changed MC firmware loading to comply with the new MC boot architecture.
Flush D-cache hierarchy after loading MC images. Add environment
variables "mcboottimeout" for MC boot timeout in milliseconds,
"mcmemsize" for MC DRAM block size. Check MC boot status before calling
flib functions.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
pankaj chauhan [Sat, 21 Mar 2015 02:28:17 +0000 (19:28 -0700)]
net/phy/cortina: Fix compilation warning
Fix comilation warning which is emitted when
firmware address is more than 32 bit.
Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Minghuan Lian [Sat, 21 Mar 2015 02:28:16 +0000 (19:28 -0700)]
armv8: Add SerDes framework for Layerscape Architecture
Add support of SerDes framework for Layerscape Architecture.
- Add support of 2 SerDes block
- Add SerDes protocol parsing and detection
- Create table of SerDes protocol supported by LS2085A
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Sat, 21 Mar 2015 02:28:15 +0000 (19:28 -0700)]
driver/ldpaa_eth: Update ldpaa ethernet driver
Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as
ETH_STATE_INIT in ldpaa_eth_stop.
Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does
not support PHYLIB.
Instead of clearing pull descriptor one time, clear it before issuing any
volatile dequeue command.
Volatile command does not return frame immidiately, wait till a frame
is available in DQRR. This frame can be valid or expired.
Flush buffer before releasing to BMan ensure the core does not have any
cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Scott Wood [Sat, 21 Mar 2015 02:28:14 +0000 (19:28 -0700)]
armv8/fsl-lsch3: Use correct compatible for serial clock fixup
The serial nodes in the fsl-lsch3 device trees have compatible =
"fsl,ns16550", "ns16550a" -- so don't look for "ns16550".
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Scott Wood [Sat, 21 Mar 2015 02:28:13 +0000 (19:28 -0700)]
armv8/ls2085a: Add workaround for USB erratum A-008751
Without this "USB may not work" according to the erratum text, though I
did not notice a problem without it.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Scott Wood [Sat, 21 Mar 2015 02:28:12 +0000 (19:28 -0700)]
fsl-lsch3: Introduce place for common early SoC init
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Sat, 21 Mar 2015 02:28:11 +0000 (19:28 -0700)]
armv8/fsl-lsch3: Update early MMU table
During booting, IFC is mapped to low region. After booting up, IFC is
remapped to high region for larger space. The environmental variables are
also stored at high region. In order to read the variables during booting,
a virtual mapping is required.
Cache was enabled for entire IFC space before. Actually the first two
entries are big enough (4MB) to cover the boot code and environmental
variables. Remove extra entries. Move OCRAM entry out of ifdef.
Signed-off-by: York Sun <yorksun@freescale.com>
Scott Wood [Sat, 21 Mar 2015 02:28:10 +0000 (19:28 -0700)]
armv8/fsl-lsch3: Set nodes in DVM domain
This is required for TLB invalidation broadcasts to work.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
pankaj chauhan [Sat, 21 Mar 2015 02:28:09 +0000 (19:28 -0700)]
armv8/ls2085a: Add support for reset request
Add support for reset_cpu() by asserting RESET_REQ_B.
Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Sat, 21 Mar 2015 02:28:08 +0000 (19:28 -0700)]
armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>
York Sun [Sat, 21 Mar 2015 02:28:07 +0000 (19:28 -0700)]
armv8/fsl-lsch3: Fix platform clock calculation
Platform clock is half of platform PLL. There is an additional divisor
in place. Clean up code copied from powerpc.
Signed-off-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Sat, 21 Mar 2015 02:28:06 +0000 (19:28 -0700)]
armv8/ls2085a: Update common header file
ls2085a_common.h contains hard-coded information for NOR/NAND flash,
I2C, DDR, etc. These are platform specific. Move them out of common
header file and placed into respective board header files.
Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector
size.
Enable command auto complete. Update prompt symbol. Set fdt_high to
0xa0000000 because Linux requires that the fdt be 8-byte aligned
and below 512 MiB. Besides ensuring compliance with the 512 MiB
limit, this avoids problems with the dtb being misaligned within
the FIT image.
Change the MC FW, MC DPL and Debug server NOR addresses in compliance
with the NOR flash layouts for 128MB flash.
Add PCIe macros. Enable "loadb" command. Disable debug server.
Enable workaround for erratum A008511.
Stop reset on panic for postmortem debugging.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Sat, 21 Mar 2015 02:28:05 +0000 (19:28 -0700)]
armv8/fsl-lsch3: Implement workaround for erratum A008585
Generic Timer may contain an erroneous value. The workaround is to
read it twice until getting the same value.
Signed-off-by: York Sun <yorksun@freescale.com>
Minghuan Lian [Thu, 19 Mar 2015 16:43:51 +0000 (09:43 -0700)]
drivers/net/e1000.c: Cleanup whitespace
The patch removes unnecessary whitespace to fix checkpatch's
warning: unnecessary whitespace before a quoted newline
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Scott Wood [Thu, 19 Mar 2015 16:43:12 +0000 (09:43 -0700)]
cmd_mem: Store last address/size/etc as ulong
Otherwise the high 32 bits get truncated on 64-bit U-boot.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Thu, 19 Mar 2015 16:30:29 +0000 (09:30 -0700)]
driver/ddr/fsl: Add workaround for DDR erratum A008511
This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Thu, 19 Mar 2015 16:30:28 +0000 (09:30 -0700)]
driver/ddr/fsl: Add built-in memory test for DDR4 driver
Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable "ddr_bist" is checked before starting test.
It takes a while (several seconds) depending on system memory size.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Thu, 19 Mar 2015 16:30:27 +0000 (09:30 -0700)]
driver/ddr/fsl: Fix driver to support empty first slot
CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Thu, 19 Mar 2015 16:30:26 +0000 (09:30 -0700)]
drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Fri, 20 Mar 2015 17:20:40 +0000 (10:20 -0700)]
driver/i2c/mxc: Enable I2C bus 3 and 4
Some SoCs have more than two I2C busses. Instead of adding ifdef
to the driver, macros are put into board header file where
CONFIG_SYS_I2C_MXC is defined.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Heiko Schocher <hs@denx.de>
Scott Wood [Thu, 19 Mar 2015 16:20:49 +0000 (09:20 -0700)]
nand/fsl_ifc: Increase eccstat[] for IFC 2.0
IFC 2.0 doubled the SRAM size, which means double the number of
ECCSTAT registers. Fix the resulting array overflow.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Thu, 19 Mar 2015 16:20:48 +0000 (09:20 -0700)]
driver/fsl_ifc: Add support to finalize CS1, CS3 address binding
For fsl-lsch3, IFC is binded with address within 32-bit at fist.
After u-boot relocates to DDR, CS1, CS3 can be binded to higher
address to support large space.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Thu, 19 Mar 2015 16:20:47 +0000 (09:20 -0700)]
board/ls2085_common: Increase malloc length
Increase malloc length for more than 2M.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Thu, 19 Mar 2015 16:20:46 +0000 (09:20 -0700)]
driver/ldpaa_eth: Add LDPAA Ethernet driver
LDPAA Ethernet driver is a freescale's new ethernet driver based on
Layerscape architecture.
Every ethernet driver controls on DPNI object. Where all DPNIs share
one common DPBP and DPIO object to support Rx and Tx flows.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Cristian Sovaiala <cristian.sovaiala@freescale.com>
CC: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
CC: J. German Rivera <German.Rivera@freescale.com>
[York Sun: s/NetReceive/net_process_received_packet]
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Thu, 19 Mar 2015 16:20:45 +0000 (09:20 -0700)]
driver/fsl-mc: Add support of MC Flibs
Freescale's Layerscape Management Complex (MC) provide support various
objects like DPRC, DPNI, DPBP and DPIO.
Where:
DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO
DPBP: Management of buffer pool
DPIO: Used for used to QBMan portal
DPNI: Represents standard network interface
These objects are used for DPAA ethernet drivers.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Bhupesh Sharma [Thu, 19 Mar 2015 16:20:44 +0000 (09:20 -0700)]
fsl-ch3/README: Add description for NOR flash layout (firmware images)
This patch adds description for NOR flash layout (firmware images)
in the README file for LS2085A platforms.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Bhupesh Sharma [Thu, 19 Mar 2015 16:20:43 +0000 (09:20 -0700)]
armv8/fsl-lsch3: Add Freescale Debug Server driver
The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:
MC DDR region start = Top of DDR - area reserved by Debug Server FW
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Tue, 7 Apr 2015 07:09:54 +0000 (15:09 +0800)]
QE/DeepSleep: add QE deepsleep support for arm
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Wed, 25 Mar 2015 09:02:59 +0000 (17:02 +0800)]
QE/DeepSleep: add QE deepsleep support for mpc85xx
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Tue, 17 Mar 2015 12:46:33 +0000 (18:16 +0530)]
drivers:usb: Check if USB Erratum A005697 is applicable on BSC913x
Check if USB Erratum A005697 is applicable on BSC913x and
add corresponding property in the device tree via device
tree fixup which is used by linux driver
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Minghuan Lian [Thu, 12 Mar 2015 02:58:49 +0000 (10:58 +0800)]
pci/layerscape: fix link and class issues to support ls2085a
1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
to show the link status, so the patch fixes it.
2. Increase the delay time to make sure that link training
has finished.
3. Return invalid value when accessing multi-function device
4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
must set this bit before change DBI register value.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Minghuan Lian [Thu, 12 Mar 2015 02:58:48 +0000 (10:58 +0800)]
pci/layerscape: remove unnecessary pcie_layerscape.h
The patch uses the common function name ft_pci_setup to replace
ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
all the functions have been declared in common.h.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Wed, 11 Mar 2015 10:14:42 +0000 (15:44 +0530)]
drivers:usb:fsl: Add affected SOCs for USB Erratum A007792
Add following affected SOCs and their personalities for USB
Erratum A007792 :
T1040 Rev 1.1
T1024 Rev 1.0
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Wed, 11 Mar 2015 10:14:23 +0000 (15:44 +0530)]
drivers:usb: Add device-tree fixup to identify socs having dual phy
Identify soc(s) having dual phy so as to add "utmi_dual" as phy_mode
for all these socs. This is required for supporting deel-sleep feature
in linux for usb driver
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
gaurav rana [Tue, 10 Mar 2015 08:38:50 +0000 (14:08 +0530)]
Add bootscript support to esbc_validate.
1. Default environment will be used for secure boot flow
which can't be edited or saved.
2. Command for secure boot is predefined in the default
environment which will run on autoboot (and autoboot is
the only option allowed in case of secure boot) and it
looks like this:
#define CONFIG_SECBOOT \
"setenv bs_hdraddr 0xe8e00000;" \
"esbc_validate $bs_hdraddr;" \
"source $img_addr;" \
"esbc_halt;"
#endif
3. Boot Script can contain esbc_validate commands and bootm command.
Uboot source command used in default secure boot command will
run the bootscript.
4. Command esbc_halt added to ensure either bootm executes
after validation of images or core should just spin.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Mon, 9 Mar 2015 09:23:09 +0000 (17:23 +0800)]
ls102xa: ddr4: Use LPUART as console output to verify DCU driver
On QDS board with DDR4 DIMM, LPUART is used as console
output to verify DCU driver. This patch adds
ls1021aqds_ddr4_nor_lpuart_defconfig for this support.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Yao Yuan [Tue, 3 Mar 2015 08:35:18 +0000 (16:35 +0800)]
ls1021atwr: add hwconfig setting to do pin mux
Freescale LS1021ATWR share some pins. Hwconfig option is used to
allows users to choose the pin functions.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: revised commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Thu, 12 Mar 2015 03:31:44 +0000 (11:31 +0800)]
arm/ls102xa:Add support of conditional workaround implementation as per SoC ver
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Linus Walleij [Tue, 21 Apr 2015 13:10:06 +0000 (15:10 +0200)]
serial: pl01x: fix PL010 regression
commit
aed2fbef5e9a0ab5a7cd01e742039a962f0b24ef
"dm: serial: Tidy up the pl01x driver"
caused a regression on (real hardware) PL010 by omitting
to update the line control register when switching baudrate.
Fix this by inlining the missing write to the baud control
register.
Also renaming the set_line_control() function to
pl011_set_line_control() since this function is clearly
PL011-specific, and it won't suffice to call that to
set up line control.
Tested on the Integrator/AP hardware.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andrey Skvortsov [Sun, 19 Apr 2015 11:58:43 +0000 (14:58 +0300)]
kconfig: remove duplicated CMD_DNS option
two CMD_DNS options were added by commit
60296a835cb17 ("commands: add more
command entries in Kconfig")
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Tue, 21 Apr 2015 00:16:21 +0000 (20:16 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-net
Bin Meng [Wed, 15 Apr 2015 03:18:20 +0000 (11:18 +0800)]
net: pch_gbe: Fix pch_gbe device name
The name "pch_gbe.%x" exceeds the limit of the name in the
'struct eth_device'. Rename it as just "pch_gbe".
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Michal Simek [Wed, 15 Apr 2015 11:31:28 +0000 (13:31 +0200)]
net: gem: Use correct type for casting
Use phys_addr_t which is used in function prototype
in system.h.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Shengzhou Liu [Tue, 7 Apr 2015 10:46:32 +0000 (18:46 +0800)]
net/phy: fixup for get_phy_id
commit
3c6928fd7b0f84 "net: phy: fix warnings with W=1" caused
some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the
warning and make those special PHYs working as well.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Luca Ellero [Tue, 24 Mar 2015 10:32:24 +0000 (11:32 +0100)]
net: phy: micrel: add support for KSZ8081MNX
This patch adds a support for KSZ8081MNX in MII mode.
Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
Acked-by: Pavel Machek <pavel@denx.de>
Tim James [Wed, 25 Mar 2015 11:55:15 +0000 (11:55 +0000)]
mii: add read-modify-write option to mii command
When accessing PHY registers it is often desirable to only update
selected bits, so it is necessary to first read the current value
before writing back an modified value with the relevant bits
updated.
To simplify this and to allow such operations to be incorporated
into simple shell scripts propose adding a 'modify' option to the
existing mii command, which takes a mask indicating the bits to
be updated in addition to a data value containing the new bits,
ie, <updated> = (<data> & <mask>) | (<current> & ~<mask>).
Signed-off-by: Tim <tim.james@macltd.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tim <tim.james@macltd.com>
Joe Hershberger [Fri, 20 Mar 2015 18:25:57 +0000 (13:25 -0500)]
Update MAINTAINERS and git-mailrc for net
Update to my corporate email and make the supported filter and aliases
more accurate.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Thierry Reding [Fri, 20 Mar 2015 11:41:21 +0000 (12:41 +0100)]
net: rtl8169: Build warning fixes for 64-bit
Turn ioaddr into an unsigned long rather than a sized 32-bit variable.
While at it, fix a couple of pointer to integer cast size mismatch
warnings by casting through unsigned long going from pointers to
integers and vice versa.
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Codrin Ciubotariu [Fri, 13 Feb 2015 12:47:58 +0000 (14:47 +0200)]
net: phy: realtek: Disable interrupt on Realtek Ethernet PHY drivers
Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have
interrupts enabled by default. If the interrupt is not treated later by
the OS and the PHY's interrupt line is enabled and shared with other
interrupts, the system will get an interrupt storm. This patch disables
the interrupt for PHY devices that use one of the current Realtek
Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L)
have the interrupt masked. In this case, the functionality of the PHY
should not be afected since this patch brings INER and INSR registers to
their default values.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Mon, 20 Apr 2015 21:12:45 +0000 (17:12 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Scott Wood [Wed, 15 Apr 2015 21:13:48 +0000 (16:13 -0500)]
powerpc/mpc8641hpcn: Move environment to avoid conflict
U-Boot on this board grew a long time ago past the 384 KiB that
it reserves for the U-Boot image, before the environment. Thus,
saveenv overwrites the U-Boot image and bricks the board.
I tried to find out when U-Boot grew beyond this point, but there is a
long stretch in the history where this board did not build -- and
AFAICT when it did fit in 384 KiB, it was missing vital features such
as fdt support. Turning off CONFIG_VIDEO was not enough to make it
fit. Thus, I don't think we have any choice other than to move the
environment.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Wed, 8 Apr 2015 03:12:15 +0000 (11:12 +0800)]
board/t2080rdb: enable CONFIG_PHY_AQUANTIA
CONFIG_PHY_AQ1202 is no longer needed, use CONFIG_PHY_AQUANTIA.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Scott Wood [Wed, 8 Apr 2015 01:20:01 +0000 (20:20 -0500)]
powerpc/mpc85xx: Remove some dead code
U-Boot does not have system calls (the services it exposes to
standalone commands use a different mechanism), so the syscall handler
is dead code. It's also broken code, as it assumes it is located at
0xc00 -- while even before the patch to stop relocating exception
vectors to 0, U-Boot had the syscall at 0x900.
The critical and machine check return paths are never called -- the
regular exception return path is used instead, which works because
xSRR0/1 have already been saved and can be restored via the regular
SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck
inside another exception prolog/epilog).
Also remove a few other small unused functions.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Scott Wood [Wed, 8 Apr 2015 01:20:00 +0000 (20:20 -0500)]
powerpc/mpc85xx: Don't relocate exception vectors
Booke does not require exception vectors to be located at address zero.
U-Boot was doing so anyway, simply because that's how it had been done
on other PPC. The downside of this is that once the OS is loaded to
address zero, the exception vectors have been overwritten -- which
makes it difficult to diagnose a crash that happens after that point.
The IVOR setup and trap entry code is simplified somewhat as a result.
Also, there is no longer a need to align individual exceptions on 0x100
byte boundaries.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 27 Mar 2015 07:53:14 +0000 (15:53 +0800)]
powerpc/t2080rdb: update ddr to support 1866MT/s
Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB.
Enable CONFIG_CMD_MEMTEST as well.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Chunhe Lan [Tue, 24 Mar 2015 07:10:41 +0000 (15:10 +0800)]
T4240RDB: Enable CONFIG_SYS_CORTINA_FW_IN_NOR config
Now cortina driver uses macro CONFIG_SYS_CORTINA_FW_IN_NOR
to define that firmware of cortina driver is stored in the
nor flash.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Ying Zhang [Tue, 10 Mar 2015 06:21:36 +0000 (14:21 +0800)]
board/t208xrdb: VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Mon, 9 Mar 2015 09:12:22 +0000 (17:12 +0800)]
powerpc/t2080: enable erratum_a007186 for t2080 rev1.1
T2080 rev1.1 also needs erratum a007186.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alexander Graf [Sat, 7 Mar 2015 01:10:09 +0000 (02:10 +0100)]
qemu-ppce500: Add support for 64bit CCSR map
QEMU 2.3 changes the address layout of the CCSR map in the PV ppce500 machine
to reside in higher address space.
Unfortunately, this exposed a glitch in u-boot for ppce500: While providing
a function to dynamically evaluate the CCSR region's position in physical
address space, we never used it. Plus we forgot to support 64bit physical
addresses.
This patch fixes that mishap, making u-boot work fine with latest QEMU again.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Curt Brune [Fri, 13 Feb 2015 18:57:11 +0000 (10:57 -0800)]
MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register
According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.
>From section 9.4.1.8 of that manual:
Source synchronous enable. This bit field must be set during
initialization. See Section 9.6.1, "DDR SDRAM Initialization
Sequence," details.
0 - Reserved
1 - The address and command are sent to the DDR SDRAMs source
synchronously.
In addition, Freescale application note AN2805 is also very clear that
this bit must be set.
This patch reverts a change introduced by commit
457caecdbca3df21a93abff19eab12dbc61b7897.
Testing Done:
Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
and inspected the generated assembly code to verify the SS_EN bit was being
set. There is one extra instruction emitted:
fff9b774: 65 29 80 00 oris r9,r9,32768
Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.
Booted an image on a MPC8541 based board successfully.
Signed-off-by: Curt Brune <curt@cumulusnetworks.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tom Rini [Mon, 20 Apr 2015 13:13:52 +0000 (09:13 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video
Heiko Schocher [Sun, 12 Apr 2015 08:20:19 +0000 (10:20 +0200)]
video, lg4573: add support for the lg4573 display
Signed-off-by: Heiko Schocher <hs@denx.de>
Heiko Schocher [Mon, 20 Apr 2015 05:53:48 +0000 (07:53 +0200)]
video, ipu: make ldb clock frequency overwritable through board code
the ldb clock can be setup in board code (for example set through PLL5).
Update the ldb_clock rate also through board code.
This should be removed, if a clock framework is availiable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Heiko Schocher [Mon, 20 Apr 2015 05:52:21 +0000 (07:52 +0200)]
video, ipu: make ldb_clock configurable
make the ldb_clock configurable through the new define
CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not
always
650000000, for example on the aristainetos2 board,
where the ldb clock derives from PLL5 clock.
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:27 +0000 (22:54 +0200)]
sandbox: add config_distro_defaults and config_distro_bootcmd
Make the sandbox setup more generic/examplary by including
config_distro_defaults.h and config_distro_bootcmd.h.
Among other things this makes it easy to test whether images will boot
though with the standard distro bootcmds by running e.g:
u-boot -c 'host bind 0 myimage.img ; boot'
By default there are 2 target host devices to emulate device with
multiple storage devices (e.g. internal ("host 0") and external
("host 1") and verify that the prioritization and fallbacks do work
correctly.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:26 +0000 (22:54 +0200)]
config: Add default client arch defines for intel architectures
Define default PXE client architecture identifiers for IA32 (0x0 aka
Intel x86PC) and Intel x86-64 (0x9 aka EFI x86-64).
This prepares for usage for config_distro_defaults in the sandbox
architecture
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:25 +0000 (22:54 +0200)]
pxe: Ensure all memory access is to mapped memory
Properly map memory through map_sysmem so that pxe can be used from the
sandbox.
Tested in sandbox as well as on jetson-tk1, odroid-xu3, snow as peach-pi
boards
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:24 +0000 (22:54 +0200)]
config_distro_bootcmd.h: Add shared block definition for the host interface
Define the common shared block environment for the host interface in
preperation for the sandbox build to use config_distro_bootcmd.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:23 +0000 (22:54 +0200)]
sandbox: Implement host dev [device]
A common pattern to check if a certain device exists (e.g. in
config_distro_bootcmd) is to use: <interface> dev [device]
Implement host dev [device] so this pattern can be used for sandbox host
devices.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:22 +0000 (22:54 +0200)]
sandbox: Renamed sb command to host
As suggested by Simon Glass, rename the sb command to host but keep the
old sb command as an alias
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:21 +0000 (22:54 +0200)]
sandbox: Add support for bootz
Add dummy bootz_setup implementation allowing the u-boot sandbox to
run bootz. This recognizes both ARM and x86 zImages to validate a
valid zImage was loaded.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:20 +0000 (22:54 +0200)]
sandbox: Split bootm code out into lib/bootm
Follow the convention of other architectures and move the platform
specific linux bootm code into sandbox/lib/bootm.c.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Sjoerd Simons [Mon, 13 Apr 2015 20:54:19 +0000 (22:54 +0200)]
sandbox: only do sandboxfs for hostfs interface
Only do sandbox filesystem access when using the hostfs device
interface, rather then falling back to it in all cases. This prevents
confusion situations due to the fallback being taken rather then an
unsupported error being raised.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 18 Apr 2015 23:24:13 +0000 (19:24 -0400)]
Merge branch 'buildman' of git://git.denx.de/u-boot-x86
Wu, Josh [Fri, 3 Apr 2015 02:51:17 +0000 (10:51 +0800)]
patman: cover letter shows like 00/xx if more than 10 patches
Make cover letter shows like 0/x, 00/xx and 000/xxx etc.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 1 Apr 2015 11:47:41 +0000 (07:47 -0400)]
buildman: Make -V (verbose_build) really be verbose
The help text for -V says we will pass V=1 but all it really did was not
pass in -s. Change the logic to pass make V=1 with given to buildman -V or
-s to make otherwise.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 20 Mar 2015 14:50:38 +0000 (10:50 -0400)]
buildman: Keep more outputs with the --keep-outputs flag
When told to keep outputs, be much more liberal in what files we keep.
In addition to adding 'MLO', keep anything that matches u-boot-spl.* (so
that we keep the map file as well) and anything we generate about
'u-boot itself. A large number of bootable formats now match this and
thus it's easier to build many targets and then boot them afterwards
using buildman.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Feb 2015 05:06:15 +0000 (22:06 -0700)]
buildman: Allow comparison of build configuration
It is useful to be able to see CONFIG changes made by commits. Add this
feature to buildman using the -K flag so that all CONFIG changes are
reported.
The CONFIG options exist in a number of files. Each is reported
individually as well as a summary that covers all files. The output
shows three parts: green for additions, red for removals and yellow for
changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Feb 2015 05:06:14 +0000 (22:06 -0700)]
buildman: Store build config files
Store all config file output so that we can compare changes if requested.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Feb 2015 05:06:13 +0000 (22:06 -0700)]
buildman: Adjust the 'aborted' heuristic for writing output
At present buildman tries to detect an aborted build and doesn't record a
result in that case. This is to make sure that an abort (e.g. with Ctrl-C)
does not mark the build as done. Without this option, buildman would never
retry the build unless -f/-F are provided. The effect is that aborting the
build creates 'fake errors' on whatever builds buildman happens to be
working on at the time.
Unfortunately the current test is not reliable and this detection can
trigger if a required toolchain tool is missing. In this case the toolchain
problem is never reported.
Adjust the logic to continue processing the build result, mark the build as
done (and failed), but with a return code which indicates that it should be
retried.
The correct fix is to fully and correctly detect an aborted build, quit
buildman immediately and not write any partial build results in this case.
Unfortunately this is currently beyond my powers and is left as an exercise
for the reader (and patches are welcome).
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Feb 2015 05:06:12 +0000 (22:06 -0700)]
buildman: Show 'make' command line when -V is used
When a verbose build it selected, show the make command before the output of
that command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Feb 2015 05:06:10 +0000 (22:06 -0700)]
Create a .cfg file containing the CONFIG options used to build
At present CONFIG options are split across Kconfig and board config headers
files. Also we have multiple files containing these CONFIG options.
In order to see exactly what is being used for building, create a .cfg
file which holds these options as reported by the C preprocessor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Scott Wood [Fri, 17 Apr 2015 14:19:01 +0000 (09:19 -0500)]
ahci: mmio_base is a virtual address
Don't store it in a u32.
Don't dereference the bus address as if it were a virtual address
(fixes
284231e49a2b4 ("ahci: Support splitting of read transactions
into multiple chunks")).
Fixes crash on boot in MPC8641HPCN_36BIT target.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: York Sun <yorksun@freescale.com>
Simon Glass [Fri, 6 Mar 2015 20:19:14 +0000 (13:19 -0700)]
sandbox: exynos: Move CONFIG_SOUND_SANDBOX to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:13 +0000 (13:19 -0700)]
sandbox: exynos: Move CONFIG_SOUND_WM8994 to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:12 +0000 (13:19 -0700)]
sandbox: exynos: Move CONFIG_SOUND_MAX98095 to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:11 +0000 (13:19 -0700)]
sandbox: exynos: Move CONFIG_I2S_SAMSUNG to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:10 +0000 (13:19 -0700)]
sandbox: exynos: Move CONFIG_I2S to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:09 +0000 (13:19 -0700)]
sandbox: exynos: Move CONFIG_CMD_SOUND to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:08 +0000 (13:19 -0700)]
sandbox: exynos: Move CONFIG_SOUND to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:07 +0000 (13:19 -0700)]
sandbox: Move CONFIG_TPM_TIS_SANDBOX to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:06 +0000 (13:19 -0700)]
sandbox: Move CONFIG_SPI_FLASH_SANDBOX to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:05 +0000 (13:19 -0700)]
sandbox: Move CONFIG_SANDBOX_SPI to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Mar 2015 20:19:04 +0000 (13:19 -0700)]
sandbox: Move CONFIG_SYS_I2C_SANDBOX to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher<hs@denx.de>
Simon Glass [Fri, 6 Mar 2015 20:19:02 +0000 (13:19 -0700)]
sandbox: Move CONFIG_SYS_VSNPRINTF to Kconfig
Move this over to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>