platform/kernel/u-boot.git
7 years agospl: Add option to enable SPL Legacy image support
Andrew F. Davis [Thu, 16 Feb 2017 17:18:39 +0000 (11:18 -0600)]
spl: Add option to enable SPL Legacy image support

Add a Kconfig option that enables Legacy image support, this allows
boards to explicitly disable this, for instance when needed for
security reasons.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Move to common/spl/Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agospl: Convert CONFIG_SPL_ABORT_ON_RAW_IMAGE into a positive option
Andrew F. Davis [Thu, 16 Feb 2017 17:18:38 +0000 (11:18 -0600)]
spl: Convert CONFIG_SPL_ABORT_ON_RAW_IMAGE into a positive option

CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it
encounters RAW images, express this same functionality as a positive
option enabling support for RAW images: CONFIG_SPL_RAW_IMAGE_SUPPORT

Also move uses of this to defconfigs.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Rework Kconfig logic a little, move to common/spl/Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoMerge git://git.denx.de/u-boot-rockchip
Tom Rini [Fri, 17 Mar 2017 13:11:12 +0000 (09:11 -0400)]
Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang.  Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).

7 years agoARM: DT: stm32f7: add qspi pin contol node
Vikas Manocha [Sun, 12 Feb 2017 18:25:53 +0000 (10:25 -0800)]
ARM: DT: stm32f7: add qspi pin contol node

It also removes the qspi pin configuration done during the
board initialization.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
7 years agoARM: DT: stm32f7: add ethernet pin contol node
Vikas Manocha [Sun, 12 Feb 2017 18:25:52 +0000 (10:25 -0800)]
ARM: DT: stm32f7: add ethernet pin contol node

It also removes the ethernet pin configuration done during the board
initialization.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
7 years agoARM: DT: stm32f7: add pin control node for serial port pins
Vikas Manocha [Sun, 12 Feb 2017 18:25:51 +0000 (10:25 -0800)]
ARM: DT: stm32f7: add pin control node for serial port pins

And remove the uart pin configuration from board initialization.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
7 years agoARM: DT: stm32f7: add pin control device node
Vikas Manocha [Sun, 12 Feb 2017 18:25:50 +0000 (10:25 -0800)]
ARM: DT: stm32f7: add pin control device node

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
7 years agoPINCTRL: stm32f7: add pin control driver
Vikas Manocha [Sun, 12 Feb 2017 18:25:49 +0000 (10:25 -0800)]
PINCTRL: stm32f7: add pin control driver

This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agostm32f7: clk: remove usart1 clock enable from board init
Vikas Manocha [Sun, 12 Feb 2017 18:25:48 +0000 (10:25 -0800)]
stm32f7: clk: remove usart1 clock enable from board init

Before clock driver availability it was required to enable usart1 clock
for serial init but now with clock driver is taking care of usart1 clock.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
7 years agoARM: DT: stm32f7: add usart1 & clock device tree nodes
Vikas Manocha [Sun, 12 Feb 2017 18:25:47 +0000 (10:25 -0800)]
ARM: DT: stm32f7: add usart1 & clock device tree nodes

Also created alias for usart1 and specified oscillator clock for stm32f7
discovery board.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
7 years agostm32f7: serial: use clock driver to enable clock
Vikas Manocha [Sun, 12 Feb 2017 18:25:46 +0000 (10:25 -0800)]
stm32f7: serial: use clock driver to enable clock

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoclk: stm32f7: add clock driver for stm32f7 family
Vikas Manocha [Sun, 12 Feb 2017 18:25:45 +0000 (10:25 -0800)]
clk: stm32f7: add clock driver for stm32f7 family

add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoserial: stm32f7: add device tree support
Vikas Manocha [Sun, 12 Feb 2017 18:25:44 +0000 (10:25 -0800)]
serial: stm32f7: add device tree support

This patch adds device tree support for stm32f7 serial driver & removes serial
platform data structure.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoarm: use common instructions applicable to armv7m & other arm archs
Vikas Manocha [Fri, 5 Feb 2016 18:43:01 +0000 (10:43 -0800)]
arm: use common instructions applicable to armv7m & other arm archs

This patch cleans the code by using instructions allowed for armv7m as well as
other Arm archs.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
7 years agoarm: Update our 'ret' assembler macro slightly
Tom Rini [Thu, 2 Mar 2017 14:59:30 +0000 (09:59 -0500)]
arm: Update our 'ret' assembler macro slightly

We only support cores that do Thumb-1 or later.  So we add a comment to
explain this and remove the architecture test.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agogpt: Fix uuid string format
Vincent Tinelli [Mon, 27 Feb 2017 14:11:15 +0000 (16:11 +0200)]
gpt: Fix uuid string format

Change GPT UUID string format from UUID to GUID per specification.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agocmd: itest: correct calculus for long format
Sebastien Colleur [Fri, 10 Feb 2017 12:59:15 +0000 (15:59 +0300)]
cmd: itest: correct calculus for long format

itest shell command doesn't work correctly in long format when
doing comparaison due to wrong mask value calculus that overflow
on 32 bits values.

Signed-off-by: Sebastien Colleur <sebastienx.colleur@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoconfigs: move CMD_MD5SUM definition to defconfigs
Andre Przywara [Wed, 15 Mar 2017 01:19:07 +0000 (01:19 +0000)]
configs: move CMD_MD5SUM definition to defconfigs

Boards with an apparent need for the md5sum command had the connected
config symbol defined in their board header file.
Move this over to the respective defconfig files now that md5sum is
configured via Kconfig.
(This is a manual effort, which differs from moveconfig.py, not sure
who is right here. Boards except sandbox loose the md5sum command with
moveconfig.py, though it was explicitly mentioned in their config.h's)

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: migrate stih410-b2260]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoKconfig: define MD5 dependency for FIT support
Andre Przywara [Wed, 15 Mar 2017 01:19:06 +0000 (01:19 +0000)]
Kconfig: define MD5 dependency for FIT support

FIT images require MD5 support to verify image checksums. So far this
was expressed by defining a CPP symbol in image.h. Since MD5 is now a
first class Kconfig citizen, express that in Kconfig instead.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoKconfig: introduce md5sum command selection
Andre Przywara [Wed, 15 Mar 2017 01:19:05 +0000 (01:19 +0000)]
Kconfig: introduce md5sum command selection

So far CONFIG_MD5SUM would need to be set by a board's include file.
Since the command is really generic, move it over to Kconfig to allow
it to be defined by either a board's defconfig, menuconfig or some
config snippet merged via mergeconfig.sh.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agokirkwood: remove get_random_hex() and MD5 dependency
Andre Przywara [Wed, 15 Mar 2017 01:19:04 +0000 (01:19 +0000)]
kirkwood: remove get_random_hex() and MD5 dependency

Commit 19a5944fcd62 ("mvgbe: remove setting of ethaddr within the
driver") removed the usage of get_random_hex() from the mvgbe driver
about six years ago. However the prototype of that function survived
till today in some kirkwood header file.
Remove that prototype and the CONFIG_MD5 dependency triggered by that.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agorockchip: video: Remove CSC initialization (HDMI)
Jernej Skrabec [Wed, 8 Mar 2017 23:34:38 +0000 (00:34 +0100)]
rockchip: video: Remove CSC initialization (HDMI)

Despite the comment in the code, CSC unit is never used. According to
the only public description of DW HDMI controller (i.MX6 manual), CSC
unit is bypassed in MC_FLOWCTRL register and then actually powered
down in MC_CLKDIS register.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: Fix HDMI audio clocks
Jernej Skrabec [Wed, 8 Mar 2017 23:34:37 +0000 (00:34 +0100)]
rockchip: video: Fix HDMI audio clocks

Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets
compared with clocks in kHz. Fix that by converting all clocks to Hz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: config: enable the USB host for rk3288 based board
Eddie Cai [Tue, 7 Mar 2017 04:47:07 +0000 (12:47 +0800)]
rockchip: config: enable the USB host for rk3288 based board

RK3288 using the dwc2 USB host controller, enable it and other usb host
funtion like storage and ethernet.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: tinker: add usb host power supply node
Eddie Cai [Tue, 7 Mar 2017 04:46:00 +0000 (12:46 +0800)]
rockchip: dts: tinker: add usb host power supply node

Tinker board have a usb host. add dts node to provide power supply.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3036: dts: bind usb vbus-supply source
Kever Yang [Mon, 6 Mar 2017 12:36:37 +0000 (20:36 +0800)]
rockchip: rk3036: dts: bind usb vbus-supply source

Bind usb host and otg vbus to its source.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: drop CONFIG_SYS_NO_FLASH
Heiko Stübner [Thu, 23 Feb 2017 16:30:40 +0000 (17:30 +0100)]
rockchip: rk3188: drop CONFIG_SYS_NO_FLASH

Commit e856bdcfb492 ("flash: complete CONFIG_SYS_NO_FLASH move with renaming")
obsoleted the CONFIG_SYS_NO_FLASH option, which still is in our
rk3188_common.h header, resulting in warnings like
    The following new ad-hoc CONFIG options were detected:
    CONFIG_SYS_NO_FLASH

So also drop it from the rk3188 header.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodm: Return actual bools in dm_fdt_pre_reloc
Heiko Stübner [Thu, 23 Feb 2017 16:30:38 +0000 (17:30 +0100)]
dm: Return actual bools in dm_fdt_pre_reloc

Documentation says that we're returning true/false, not 1/0 so adapt
the function to return actual booleans.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: configs: Enable networking support on rk3288 boards
Jacob Chen [Thu, 23 Feb 2017 06:20:17 +0000 (14:20 +0800)]
rockchip: configs: Enable networking support on rk3288 boards

At current, only firefly and rock2 have network enabled.
Let's enable other boards.

Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agoARM: dts: rockchip: enable gmac for rk3288 boards
Jacob Chen [Thu, 23 Feb 2017 06:20:16 +0000 (14:20 +0800)]
ARM: dts: rockchip: enable gmac for rk3288 boards

Enable gmac interface for rk3288 board dts.
use "okay" not "ok"

Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodts: rk3036: add sdmmc for rk3036
Eddie Cai [Mon, 20 Feb 2017 06:03:01 +0000 (14:03 +0800)]
dts: rk3036: add sdmmc for rk3036

rk3036 support sdmmc, add dts node to support it.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodts: rk3399: add mmc alias for rk3399
Eddie Cai [Mon, 20 Feb 2017 06:02:37 +0000 (14:02 +0800)]
dts: rk3399: add mmc alias for rk3399

add mmc alias for rk3399

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3328: add defconfig for evb-rk3328
Kever Yang [Thu, 23 Feb 2017 07:37:56 +0000 (15:37 +0800)]
rockchip: rk3328: add defconfig for evb-rk3328

Enable board config for evb-rk3328.
SDcard and eMMC boot is OK in this initial version,
USB and EMAC function is not available now, will comes later.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3328: add evb-rk3328 support
Kever Yang [Thu, 23 Feb 2017 07:37:55 +0000 (15:37 +0800)]
rockchip: rk3328: add evb-rk3328 support

evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3328: add sysreset driver
Kever Yang [Thu, 23 Feb 2017 07:37:54 +0000 (15:37 +0800)]
rockchip: rk3328: add sysreset driver

Add rk3328 sysreset driver.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3328: add pinctrl driver
Kever Yang [Thu, 23 Feb 2017 07:37:53 +0000 (15:37 +0800)]
rockchip: rk3328: add pinctrl driver

Add rk3328 pinctrl driver and grf/iomux structure definition.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3328: add clock driver
Kever Yang [Thu, 23 Feb 2017 07:37:52 +0000 (15:37 +0800)]
rockchip: rk3328: add clock driver

Add rk3328 clock driver and cru structure definition.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3328: add soc basic support
Kever Yang [Thu, 23 Feb 2017 07:37:51 +0000 (15:37 +0800)]
rockchip: rk3328: add soc basic support

RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3328: add device tree file
Kever Yang [Thu, 23 Feb 2017 07:37:50 +0000 (15:37 +0800)]
rockchip: rk3328: add device tree file

Add dts binding header for rk3328, files origin from kernel.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: config: rk3399: enable SPL config for evb-rk3399
Kever Yang [Wed, 22 Feb 2017 08:56:38 +0000 (16:56 +0800)]
rockchip: config: rk3399: enable SPL config for evb-rk3399

Enable all the CONFIGs which need by SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Drop CONFIG_ROCKCHIP_DWMMC for now due to build error:
Move changes to arch/arm/mach-rockchip/Kconfig to this patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: arm64: rk3399: add SPL support
Kever Yang [Thu, 23 Feb 2017 08:09:05 +0000 (16:09 +0800)]
rockchip: arm64: rk3399: add SPL support

Add SPL support for rk3399, default with of-platdata enabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Drop Kconfig changes to fix build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: rk3399: update for spl require driver
Kever Yang [Wed, 22 Feb 2017 08:56:36 +0000 (16:56 +0800)]
rockchip: dts: rk3399: update for spl require driver

Add syscon and dmc node, and 'u-boot,dm-pre-reloc' option for
required driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: arm64: rk3399: add ddr controller driver
Kever Yang [Wed, 22 Feb 2017 08:56:35 +0000 (16:56 +0800)]
rockchip: arm64: rk3399: add ddr controller driver

RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Added rockchip: tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: tinker: configs: use correct mmc instance as boot target device
Eddie Cai [Mon, 20 Feb 2017 03:08:16 +0000 (11:08 +0800)]
rockchip: tinker: configs: use correct mmc instance as boot target device

We are using wrong mmc instance as boot target device now. below Jaehoon Chung's
patch use mmc alias which correct it. That make tinker board can not find mmc
device. So give it correct mmc device instance.

        commit 02ad33aa3a84821c8d9a6c4f167f143f6248b084
        Author: Jaehoon Chung <jh80.chung@samsung.com>
        Date:   Thu Feb 2 13:41:14 2017 +0900

            mmc: mmc-uclass: use the fixed devnum with alias node

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: firefly: configs: remove config_spl_of_platdata
Jacob Chen [Wed, 15 Feb 2017 03:06:00 +0000 (11:06 +0800)]
rockchip: firefly: configs: remove config_spl_of_platdata

We should remove config_spl_of_platdata to build u-boot-spl-dtb.bin rather than u-boot-spl-nodtb.bin
since we use spl_back_to_brom.

I miss it because i forget to clean build-dir..

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: Add main, spl and tpl boards
Heiko Stübner [Sat, 18 Feb 2017 18:46:38 +0000 (19:46 +0100)]
rockchip: rk3188: Add main, spl and tpl boards

The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl
the resides in the rest of the sram and loads the regular U-Boot living
in regular ram.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3188: Add sdram driver
Heiko Stübner [Sat, 18 Feb 2017 18:46:37 +0000 (19:46 +0100)]
rockchip: rk3188: Add sdram driver

The sdram controller blocks are very similar to the rk3288 in utilizing
memory scheduler, Designware uPCTL and Designware PUBL blocks, only
limited to one bank instead of two.

There are some minimal differences when setting up the ram, so it gets
a separate driver for the rk3188 but reuses the driver structs, as there
is no need to define the same again.

More optimization can happen when the modelling of the controller parts
in the dts actually follow the hardware layout hopefully at some point
in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3188: Add core support
Heiko Stübner [Sat, 18 Feb 2017 18:46:36 +0000 (19:46 +0100)]
rockchip: rk3188: Add core support

Add the core architecture code for the rk3188.
It doesn't support the SPL yet, as because of some
unknown error it doesn't start yet.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Drop these defines from rk3188_common.h
   CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION
   CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: Add core devicetree files
Heiko Stübner [Sat, 18 Feb 2017 18:46:35 +0000 (19:46 +0100)]
rockchip: rk3188: Add core devicetree files

The rk3188 shares a lot of peripherals with the rk3066 and thus
has a common include called rk3xxx.dtsi. Add both this one and
the specialized rk3188 on top of it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3188: Add clock driver
Heiko Stübner [Sat, 18 Feb 2017 18:46:34 +0000 (19:46 +0100)]
rockchip: rk3188: Add clock driver

Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3188: Add rk3066/rk3188 clock bindings
Heiko Stübner [Sat, 18 Feb 2017 18:46:33 +0000 (19:46 +0100)]
rockchip: rk3188: Add rk3066/rk3188 clock bindings

Bring in required device clock binding files from Linux.
The clock trees for rk3066 and rk3188 are largely similar, which makes
them share the common parts in a shared header. While we focus on rk3188
for now, bring in both headers already for completeness sake.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3188: Add sysreset driver
Heiko Stübner [Sat, 18 Feb 2017 18:46:32 +0000 (19:46 +0100)]
rockchip: rk3188: Add sysreset driver

Driver for the sysreset of Rockchip rk3188 socs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3188: Add pinctrl driver
Heiko Stübner [Sat, 18 Feb 2017 18:46:31 +0000 (19:46 +0100)]
rockchip: rk3188: Add pinctrl driver

Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3188: Add header files for PMU and GRF
Heiko Stübner [Sat, 18 Feb 2017 18:46:30 +0000 (19:46 +0100)]
rockchip: rk3188: Add header files for PMU and GRF

PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: serial: Adapt rockchip of-platdata driver for rk3188
Heiko Stübner [Sat, 18 Feb 2017 18:46:29 +0000 (19:46 +0100)]
rockchip: serial: Adapt rockchip of-platdata driver for rk3188

Add necessary structs to have the driver also work for the serial
on the rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: mkimage: Add support rk3188 serial
Heiko Stübner [Sat, 18 Feb 2017 18:46:28 +0000 (19:46 +0100)]
rockchip: mkimage: Add support rk3188 serial

Add the entry for the rk3188 requiring rc4-encryption of the SPL.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: mkimage: Allow encoding of loader code in spl images
Heiko Stübner [Sat, 18 Feb 2017 18:46:27 +0000 (19:46 +0100)]
rockchip: mkimage: Allow encoding of loader code in spl images

Rockchip SoCs allow the spl code to be rc4-encoded, not only the
image header, but only newer SoCs allow this encoding to be disabled.

The rk3188 is not part of those and requires its boot code to be
rc4-encoded with the regular key. So add the ability to do this
encoding via a setting on a per-soc basis when building spl images.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: Move bootrom-related declarations to a header
Heiko Stübner [Sat, 18 Feb 2017 18:46:26 +0000 (19:46 +0100)]
rockchip: Move bootrom-related declarations to a header

So far spl-boards have declared the back_to_brom() function as simple
extern in the files themself. That doesn't scale well if every boards
defines this on its own.
Therefore move the declarations to a bootrom header.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: Move bootrom helper compilation to a hidden option
Heiko Stübner [Sat, 18 Feb 2017 18:46:25 +0000 (19:46 +0100)]
rockchip: Move bootrom helper compilation to a hidden option

Right now the ROCKCHIP_SPL_BACK_TO_BROM option both triggers
compilation of the bootrom hook-code as well as enabling the
behaviour of loading the full U-Boot via the boot.

New added socs may always need the bootrom code, while still
being able to decide between loading U-Boot regularly or via
the bootrom separately.

So move the compilation of the bootrom code to a hidden option
that gets selected by ROCKCHIP_SPL_BACK_TO_BROM, but can also
be selected by other parts.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3288: sdram: style fixes from rk3188 sdram review
Heiko Stübner [Sat, 18 Feb 2017 18:46:24 +0000 (19:46 +0100)]
rockchip: rk3288: sdram: style fixes from rk3188 sdram review

The sdram IP blocks used on rk3066, rk3188 and rk3288 are very similar
and we want to unify things once all 3 work as expected.
Therefore try to keep the rk3288 sdram driver in line by applying the
general review comments received for the rk3188 variant to it as well.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3288: sdram: use constants in ddrconf table
Heiko Stübner [Sat, 18 Feb 2017 18:46:23 +0000 (19:46 +0100)]
rockchip: rk3288: sdram: use constants in ddrconf table

Use defines to describe the bit shifts used to create the
table for ddrconf register values.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3288: limit gpll and cpll init to SPL build
Heiko Stübner [Sat, 18 Feb 2017 18:46:22 +0000 (19:46 +0100)]
rockchip: clk: rk3288: limit gpll and cpll init to SPL build

The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodm: allow limiting pre-reloc markings to spl or tpl
Heiko Stübner [Sat, 18 Feb 2017 18:46:21 +0000 (19:46 +0100)]
dm: allow limiting pre-reloc markings to spl or tpl

Right now the u-boot,dm-pre-reloc flag will make each marked node
always appear in both spl and tpl. But systems needing an additional
tpl might have special constraints for each, like the spl needing to
be very tiny.

So introduce two additional flags to mark nodes for only spl or tpl
environments and introduce a function dm_fdt_pre_reloc to automate
the necessary checks in code instances checking for pre-relocation
flags.

The behaviour of the original flag stays untouched and still marks
a node for both spl and tpl.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: arm64: rk3399: syscon addition for rk3399
Kever Yang [Mon, 13 Feb 2017 09:38:59 +0000 (17:38 +0800)]
rockchip: arm64: rk3399: syscon addition for rk3399

rk3399 has different syscon registers which may used in spl,
add to support rk3399 spl.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3399: add the of-platdata support
Kever Yang [Mon, 13 Feb 2017 09:38:58 +0000 (17:38 +0800)]
rockchip: pinctrl: rk3399: add the of-platdata support

Do not use the API which of-platdata not support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: sdhci: rk3399: update driver to support of-platdata
Kever Yang [Mon, 13 Feb 2017 09:38:57 +0000 (17:38 +0800)]
rockchip: sdhci: rk3399: update driver to support of-platdata

Change some API in order to enable of-platdata.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3399: update driver for spl
Kever Yang [Mon, 13 Feb 2017 09:38:56 +0000 (17:38 +0800)]
rockchip: clk: rk3399: update driver for spl

Add ddr clock setting, add rockchip_get_pmucru API,
and enable of-platdata support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag and fix pmuclk_init() build warning:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h
Kever Yang [Mon, 13 Feb 2017 09:38:55 +0000 (17:38 +0800)]
rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h

rk3399 grf register bit defenitions should locate in header
file, so that not only pinctrl can use it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3288: use spl_early_init() instead of spl_init()
Eddie Cai [Wed, 15 Mar 2017 14:43:29 +0000 (08:43 -0600)]
rockchip: rk3288: use spl_early_init() instead of spl_init()

Use spl_early_init() to make sure that early malloc() is initialised. This
fixes booting on firefly-rk3288, for example.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
7 years agospl: Add spl_early_init()
Eddie Cai [Wed, 15 Mar 2017 14:43:28 +0000 (08:43 -0600)]
spl: Add spl_early_init()

At present malloc_base/_limit/_ptr are not initialised in spl_init() when
we call spl_init() in board_init_f(). This is due to a recent change aimed
at avoiding overwriting the malloc area set up on some boards by
spl_relocate_stack_gd().

However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
skip setting up the memory area in spl_init() which is obviously wrong.

To fix this, add a new function spl_early_init() which can be called in
board_init_f().

Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Rewrote spl_{,early_}init() to avoid duplicate code:
Rewrite/expand commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
7 years agoMerge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Thu, 16 Mar 2017 20:44:23 +0000 (16:44 -0400)]
Merge tag 'xilinx-for-v2017.05' of git://denx.de/git/u-boot-microblaze

Xilinx changes for v2017.05

- Move to DM clk driver
- Add clk support for zynq_sdhci

7 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Thu, 16 Mar 2017 20:43:32 +0000 (16:43 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

7 years agoarm64: booti: allow to place kernel image anywhere in physical memory
Masahiro Yamada [Thu, 9 Mar 2017 07:28:25 +0000 (16:28 +0900)]
arm64: booti: allow to place kernel image anywhere in physical memory

At first, the ARM64 Linux booting requirement recommended that the
kernel image be placed text_offset bytes from 2MB aligned base near
the start of usable system RAM because memory below that base address
was unusable at that time.

This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
allow kernel Image to be loaded anywhere in physical memory").
Since then, the bit 3 of the flags field indicates the tolerance
of the kernel physical placement.  If this bit is set, the 2MB
aligned base may be anywhere in physical memory.  For details, see
Documentation/arm64/booting.txt of Linux.

The booti command should be also relaxed.  If the bit 3 is set,
images->ep is respected, and the image is placed at the nearest
bootable location.  Otherwise, it is relocated to the start of the
system RAM to keep the original behavior.

Another wrinkle we need to take care of is the unknown endianness of
text_offset for a kernel older than commit a2c1d73b94ed (i.e. v3.16).
We can detect this based on the image_size field.  If the field is
zero, just use a fixed offset 0x80000.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agotools: fix cross-compiling tools when HOSTCC is overridden
Masahiro Yamada [Mon, 13 Mar 2017 08:43:16 +0000 (17:43 +0900)]
tools: fix cross-compiling tools when HOSTCC is overridden

Richard reported U-Boot tools issues in OpenEmbedded/Yocto project.

OE needs to be able to change the default compiler. If we pass in
HOSTCC through the make command, it overwrites all HOSTCC instances,
including ones in tools/Makefile and tools/env/Makefile, which breaks
"make cross_tools" and "make env", respectively.

Add "override" directives to avoid overriding HOSTCC instances that
really need to point to the cross-compiler.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agotiny-printf: add static to locally used functions
Masahiro Yamada [Sun, 12 Feb 2017 09:08:43 +0000 (18:08 +0900)]
tiny-printf: add static to locally used functions

These two functions are only used in lib/tiny-printf.c .

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoigep00x0: fixup FDT according to detected flash type
Ladislav Michl [Sat, 18 Feb 2017 23:24:49 +0000 (00:24 +0100)]
igep00x0: fixup FDT according to detected flash type

Leave only detected flash type enabled in FTD as otherwise GPMC CS is
claimed (and never freed) by Linux, causing 'concurent' flash type
not to be probed.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
7 years agoigep00x0: disable environment
Ladislav Michl [Sat, 18 Feb 2017 23:23:39 +0000 (00:23 +0100)]
igep00x0: disable environment

ISEE's U-Boot and Linux are using 1bit ECC scheme, while we
switched to 8bit ECC to fullfill flash specification requirements.
However when trying to run U-Boot on board with 1bit ECC'd data
on flash, UBI code takes several minutes to pass scan as reading
of every block ends with ecc error (which is also printed on
console).
So, until proper solution is developed, disable environment
alltogether.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
7 years agoboard: Add STMicroelectronics STiH410-B2260 support
Patrice Chotard [Tue, 21 Feb 2017 12:37:12 +0000 (13:37 +0100)]
board: Add STMicroelectronics STiH410-B2260 support

This is a 96Board compliant board based on STiH410 SoC:
  - 1GB DDR
  - On-Board USB combo WiFi/Bluetooth RTL8723BU
    with PCB soldered antenna
  - Ethernet 1000-BaseT
  - SATA
  - HDMI
  - 2 x USB2.0 type A
  - 1 x USB2.0 type micro-AB
  - SD card slot
  - High speed connector (SD/I2C/USB interfaces)
  - Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces)

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSTiH410-B2260: Add device tree
Patrice Chotard [Tue, 21 Feb 2017 12:37:11 +0000 (13:37 +0100)]
STiH410-B2260: Add device tree

This device tree has been extracted from v4.9 kernel

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSTiH410: Add STi pinctrl driver
Patrice Chotard [Tue, 21 Feb 2017 12:37:10 +0000 (13:37 +0100)]
STiH410: Add STi pinctrl driver

Add STMicroelectronics STiH410 pinctrl driver

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSTiH410: Add STi SDHCI driver
Patrice Chotard [Tue, 21 Feb 2017 12:37:09 +0000 (13:37 +0100)]
STiH410: Add STi SDHCI driver

Add SDHCI host controller found on STMicroelectronics SoCs

On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live
inside a dedicated flashSS sub-system that provides an extend subset
of registers that can be used to configure the Arasan MMC/SD Host
Controller.

This means, that the SDHCI Arasan Controller can be configured to be
eMMC4.5 or 4.3 spec compliant.

W/o these settings the SDHCI will configure and use the MMC/SD
controller with limited features e.g. PIO mode, no DMA, no HS etc.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
7 years agogpio: do not include <asm/arch/gpio.h> for ARCH_STI
Patrice Chotard [Tue, 21 Feb 2017 12:37:08 +0000 (13:37 +0100)]
gpio: do not include <asm/arch/gpio.h> for ARCH_STI

As no gpio.h is defined in arch/arm/include/asm/arch-stih410,
to avoid compilation failure, do not include asm/arch/gpio.h.

This is needed for example when including sdhci.h, which include
asm/gpio.h>.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSTiH410: Add STi serial driver
Patrice Chotard [Tue, 21 Feb 2017 12:37:07 +0000 (13:37 +0100)]
STiH410: Add STi serial driver

This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP
is common across other STMicroelectronics SoCs

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSTiH410: Add STi sysreset driver
Patrice Chotard [Tue, 21 Feb 2017 12:37:06 +0000 (13:37 +0100)]
STiH410: Add STi sysreset driver

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSTiH410: Add STi timer driver
Patrice Chotard [Tue, 21 Feb 2017 12:37:05 +0000 (13:37 +0100)]
STiH410: Add STi timer driver

Add ARM global timer based timer

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoarm: Add support for STMicroelectronics STiH410 soc
Patrice Chotard [Tue, 21 Feb 2017 12:37:04 +0000 (13:37 +0100)]
arm: Add support for STMicroelectronics STiH410 soc

The STiH410 is an advanced multi-HD AVC processor with 3D
graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU
part of the STiH407 family.

It has wide connectivity including USB 3.0, PCI-e, SATA
and gigabit ethernet.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
7 years agoarmv7m: Add SysTick timer driver
Phil Edworthy [Fri, 17 Feb 2017 08:22:17 +0000 (08:22 +0000)]
armv7m: Add SysTick timer driver

The SysTick is a 24-bit down counter that is found on all ARM Cortex
M3, M4, M7 devices and is always located at a fixed address.

The number of reference clock ticks that correspond to 10ms is normally
defined in the SysTick Calibration register's TENMS field. However, on some
devices this is wrong, so this driver allows the clock rate to be defined
using CONFIG_SYS_HZ_CLOCK.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Vikas MANOCHA <vikas.manocha@st.com>
7 years agotools: omapimage: Fix size in header
Lokesh Vutla [Wed, 15 Feb 2017 13:12:54 +0000 (18:42 +0530)]
tools: omapimage: Fix size in header

The size field in GP header that is expected by ROM is size of the
image + size of the header. But omapimage generates a gp header
only with size of the image as size field. Fix it

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoarm: omap3: Bring back ARM errata workaround 725233
Siarhei Siamashka [Mon, 6 Mar 2017 01:16:53 +0000 (03:16 +0200)]
arm: omap3: Bring back ARM errata workaround 725233

The workaround for ARM errata 725233 had been lost since
commit 45bf05854bc94e (armv7: adapt omap3 to the new cache
maintenance framework). Bring it back in order to avoid
very difficult to reproduce, but actually encountered in
the wild CPU deadlocks when running software rendered
X11 desktop on OMAP3530 hardware.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Migrate to Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoarm: omap3: Compile clock.c with -marm option to unbreak OMAP3530
Siarhei Siamashka [Mon, 6 Mar 2017 01:16:52 +0000 (03:16 +0200)]
arm: omap3: Compile clock.c with -marm option to unbreak OMAP3530

Boards with OMAP3530 SoC fail to boot since commit bd2c4522c26d5
("ti: armv7: enable EXT support in SPL (using ti_armv7_common.h)")
because it enabled the use of Thumb2 for the SPL.

Experiments have shown that the deadlock happens in the
prcm_init() function from 'arch/arm/mach-omap2/omap3/clock.c'.

This patch enforces the compilation of clock.c source file in
ARM mode and makes the deadlock disappear. We are yet to figure
out the root cause of the problem. Still this is somewhat
better than having non-bootable boards for years.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoomap3_overo: Reduce SPL size
Tom Rini [Fri, 10 Mar 2017 19:16:54 +0000 (14:16 -0500)]
omap3_overo: Reduce SPL size

Borrowing from omap3_logic, switch to SPL_SYS_MALLOC_SIMPLE and moving
the stack to DDR as soon as we're able.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoLS1021ATWR: Modify u-boot size for sd secure boot
Vinitha Pillai [Wed, 1 Feb 2017 12:58:53 +0000 (18:28 +0530)]
LS1021ATWR: Modify u-boot size for sd secure boot

Raw uboot image is used in place of FIT image in secure boot.
The maximum allocated size of raw u-boot bin is 1MB in memory map.
Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
The bootscript  (BS_ADDR) and its header (BS_HDR_ADDR) offset on
MMC have also been modified to accommodate the increase in uboot size.

Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-layerscape: Add vid support for LS2080AQDS
Priyanka Jain [Thu, 19 Jan 2017 05:42:28 +0000 (11:12 +0530)]
armv8: fsl-layerscape: Add vid support for LS2080AQDS

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-lsch3: Update VID support
Priyanka Jain [Thu, 19 Jan 2017 05:42:27 +0000 (11:12 +0530)]
armv8: fsl-lsch3: Update VID support

VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
LS2088A, LS2080A differs from existing logic.
-VDD voltage array is different
-Registers are different
-VDD calculation logic is different

Add new function adjust_vdd() for LSCH3 compliant SoCs

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-layerscape: Updates DCFG register map
Priyanka Jain [Thu, 19 Jan 2017 05:42:26 +0000 (11:12 +0530)]
armv8: fsl-layerscape: Updates DCFG register map

Based on latest hardware documentation,
update ccsr_gur structure (represents DCFG register map)

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/ls104xa: remove the DDR interactive debugging info from SPL
Hou Zhiqiang [Mon, 6 Feb 2017 03:29:00 +0000 (11:29 +0800)]
armv8/ls104xa: remove the DDR interactive debugging info from SPL

Remove the DDR interactive debugging to reduce the size of spl image.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-lsch2: add workaround for erratum A-010635
Tang Yuantian [Tue, 7 Feb 2017 06:18:59 +0000 (14:18 +0800)]
armv8: fsl-lsch2: add workaround for erratum A-010635

Read DMA operations causes CRC error on armv8 chassis 2 platforms
due to the erratum A-010635.
In order to support sata on these platforms, ECC needs to be disabled.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: layerscape: Update early MMU for DDR after initialization
York Sun [Mon, 6 Mar 2017 17:02:34 +0000 (09:02 -0800)]
armv8: layerscape: Update early MMU for DDR after initialization

In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.

Signed-off-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: mmu: Add a function to change mapping attributes
York Sun [Mon, 6 Mar 2017 17:02:33 +0000 (09:02 -0800)]
armv8: mmu: Add a function to change mapping attributes

Function mmu_change_region_attr() is added to change existing mapping
with updated PXN, UXN and memory type. This is a break-before-make
process during which the mapping becomes fault (invalid) before final
attributres are set.

Signed-off-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls2080a: Drop early MMU for SPL build
York Sun [Mon, 6 Mar 2017 17:02:32 +0000 (09:02 -0800)]
armv8: ls2080a: Drop early MMU for SPL build

Early MMU improves performance especially on emulators. However, the
early MMU is left enabled after the first stage of SPL boot. Instead
of flushing D-cache and dealing with re-enabling MMU for the second
stage U-Boot, disabling it for SPL build simplifies the process. The
performance penalty is unnoticeable on the real hardware. As of now,
SPL boot is not supported by existing emulators. So this should have
no impact on emulators.

Signed-off-by: York Sun <york.sun@nxp.com>