Tom Rini [Mon, 24 Jul 2023 14:58:25 +0000 (10:58 -0400)]
Merge tag 'u-boot-at91-fixes-2023.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-atmel fixes for the 2023.07 cycle:
This small fixes set includes the LTO configs for the boards that had
the SPL size up to the limit (sama5d2-based), such that more code can be
added. It also includes a fix for mmc non-removable.
Tom Rini [Mon, 24 Jul 2023 14:58:07 +0000 (10:58 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Set up per-hart stack before any function call
- Sync visionfive2 board DTS with Linux
- Define cache line size for USB 3.0 driver for RISC-V CPU
Zixun LI [Wed, 17 May 2023 13:49:45 +0000 (15:49 +0200)]
atmel_sdhci: Force card-detect if MMC_CAP_NONREMOVABLE.
If the device attached to the MMC bus is not removable, set force card-detect
bit to bypass card detection procedure, so card detection pin can be used for
other purposes.
It's also a workaround for SAMA5D2 who doesn't drive CMD if using GPIO for card
detection.
Signed-off-by: Zixun LI <zli@ogga.fr>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Eugen Hristev [Mon, 24 Jul 2023 10:05:13 +0000 (13:05 +0300)]
configs: sama5d2: enable CONFIG_LTO
arm-none-linux-gnueabihf-ld.bfd: u-boot-spl section `__u_boot_list' will not fit in region `.sram'
arm-none-linux-gnueabihf-ld.bfd: region `.sram' overflowed by 100 bytes
SPL is at limit so to stop seeing above error in built, enable
link time optimizations CONFIG_LTO.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
Stefan Roese [Thu, 27 Apr 2023 08:59:45 +0000 (10:59 +0200)]
configs: at91: sama5d2_icp_mmc: Enable CONFIG_LTO
Adding just a tiny bit more code for sama5d2_icp_mmc leads to a SRAM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
[eugen.hristev@microchip.com: restrict patch just to CONFIG_LTO]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Heinrich Schuchardt [Fri, 21 Jul 2023 16:01:18 +0000 (18:01 +0200)]
riscv: define a cache line size for the generic CPU
The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.
Define the cache line size for QEMU on RISC-V to be 64 bytes.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Chanho Park [Fri, 14 Jul 2023 09:41:09 +0000 (18:41 +0900)]
doc: visionfive2: apply a trailing space to the prompt
Apply the trailing space changes in the guide document.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Chanho Park [Fri, 14 Jul 2023 09:41:08 +0000 (18:41 +0900)]
configs: visionfive2: add a trailing space to prompt
Adds a trailing space to SYS_PROMPT to make it easier to distinguish
between commands and the prompt.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Xingyu Wu [Fri, 7 Jul 2023 10:50:11 +0000 (18:50 +0800)]
clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion
Modify the drivers to add of_xlate ops and transform clock id.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Xingyu Wu [Fri, 7 Jul 2023 10:50:10 +0000 (18:50 +0800)]
dt-bindings: clock: jh7110: Modify clock id to be same with Linux
The clock id needs to be changed to be consistent with Linux.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Xingyu Wu [Fri, 7 Jul 2023 10:50:09 +0000 (18:50 +0800)]
riscv: dts: jh7110: Add clock source from PLL
Change the PLL clock source from syscrg to sys_syscon child node.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Xingyu Wu [Fri, 7 Jul 2023 10:50:08 +0000 (18:50 +0800)]
riscv: dts: jh7110: Add PLL clock controller node
Add child node about PLL clock controller in sys_syscon node.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Xingyu Wu [Fri, 7 Jul 2023 10:50:07 +0000 (18:50 +0800)]
clk: starfive: jh7110: Separate the PLL driver
Drop the PLL part in SYSCRG driver and separate to be a single
PLL driver of which the compatible is "starfive,jh7110-pll".
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Bo Gan [Sun, 11 Jun 2023 23:54:17 +0000 (16:54 -0700)]
riscv: setup per-hart stack earlier
Harts need to use per-hart stack before any function call, even if that
function is a simple one. When the callee uses stack for register save/
restore, especially RA, if nested call, concurrent access by multiple
harts on the same stack will cause data-race.
This patch sets up SP before `board_init_f_alloc_reserve`. A side effect
of this is that the memory layout has changed as the following:
+----------------+ +----------------+ <----- SPL_STACK/
| ...... | | hart 0 stack | SYS_INIT_SP_ADDR
| malloc_base | +----------------+
+----------------+ | hart 1 stack |
| GD | +----------------+ If not SMP, N=1
+----------------+ | ...... |
| hart 0 stack | +----------------+
+----------------+ ==> | hart N-1 stack|
| hart 1 stack | +----------------+
+----------------+ | ...... |
| ...... | | malloc_base |
+----------------+ +----------------+
| hart N-1 stack| | GD |
+----------------+ +----------------+
| | | |
Signed-off-by: Bo Gan <ganboing@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Leo <ycliang@andestech.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tom Rini [Mon, 24 Jul 2023 01:46:05 +0000 (21:46 -0400)]
Merge branch '2023-07-22-TI-binman-and-K3-improvements'
- Migrate TI K3 platforms to using binman to generate all images, and
then improve the platform slightly.
Tom Rini [Fri, 21 Jul 2023 18:44:46 +0000 (00:14 +0530)]
CI: Make use of buildman requirements.txt
Now that buildman has a requirements.txt file we need to make use of it.
Reviewed-by: Simon Glass <sjg@chromium.org>
[n-francis@ti.com: Adding missing command from .azure-pipelines.yml]
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 21 Jul 2023 18:44:45 +0000 (00:14 +0530)]
buildman: Create a requirements.txt file
At this point, buildman requires a few different modules and so we need
a requirements.txt to track what modules are needed.
Cc: Simon Glass <sjg@chromium.org>
Cc: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Andrew Davis [Fri, 21 Jul 2023 18:44:44 +0000 (00:14 +0530)]
binman: Overwrite symlink if it already exists
Without this re-building will fail with an error when trying to create
the symlink for the second time with an already exists error.
Signed-off-by: Andrew Davis <afd@ti.com>
[n-francis@ti.com: Added support for test output dir and testcase]
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:43 +0000 (00:14 +0530)]
doc: board: ti: Update documentation for binman flow
Earlier documentation specified builds for generating bootloader images
using an external TI repository k3-image-gen and core-secdev-k3. Modify
this to using the binman flow so that user understands how to build the
final boot images.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:42 +0000 (00:14 +0530)]
k3: tools: config.mk: Update makefile and remove scripts
Since binman is used to package bootloader images for all K3 devices, we
do not have to rely on the earlier methods to package them.
Scripts that were used to generate x509 certificate for tiboot3.bin and
generate tispl.bin, u-boot.img have been removed.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:41 +0000 (00:14 +0530)]
arm: k3-am65x-iot2050: Use binman for tispl.bin for iot2050
Move to using binman to generate tispl.bin which is used to generate the
final flash.bin bootloader for iot2050 boards.
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:40 +0000 (00:14 +0530)]
am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img
Support added for HS-SE, HS-FS and GP boot binaries for AM62ax.
HS-SE:
* tiboot3-am62ax-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-am62ax-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am62ax-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by AM62ax requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:39 +0000 (00:14 +0530)]
am62a: yaml: Add board configs for AM62ax
Added YAML configs for AM62ax
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:38 +0000 (00:14 +0530)]
am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img
Support added for HS-SE, HS-FS and GP boot binaries for AM62.
HS-SE:
* tiboot3-am62x-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-am62x-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am62x-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by AM62 requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:37 +0000 (00:14 +0530)]
am62: yaml: Add board configs for AM62
Added YAML configs for AM62
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:36 +0000 (00:14 +0530)]
j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img
Support has been added for both HS-SE, HS-FS and GP images.
HS-SE:
* tiboot3-j721s2-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-j721s2-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-j721s2-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by J721S2 requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:35 +0000 (00:14 +0530)]
j721s2: yaml: Add board configs for J721S2
Added YAML configs for J721S2
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:34 +0000 (00:14 +0530)]
am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img
Support added for HS and GP boot binaries for AM64x.
HS-SE:
* tiboot3-am64x_sr2-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-am64x_sr2-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am64x-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
Note that the bootflow followed by AM64x requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* sysfw
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* ATF
* OP-TEE
* A53 SPL
* A53 SPL dtbs
u-boot.img:
* A53 U-Boot
* A53 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:33 +0000 (00:14 +0530)]
am64x: yaml: Add board configs for AM64x
Added YAML configs for AM64xx
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:32 +0000 (00:14 +0530)]
am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img
Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images.
HS-SE:
* tiboot3-am65x_sr2-hs-evm.bin
* sysfw-am65x_sr2-hs-evm.itb
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin
* sysfw.itb --> sysfw-am65x_sr2-gp-evm.itb
* tispl.bin_unsigned
* u-boot.img_unsigned
Note that the bootflow followed by AM65x requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
sysfw.itb:
* sysfw
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* ATF
* OP-TEE
* A53 SPL
* A53 SPL dtbs
u-boot.img:
* A53 U-Boot
* A53 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:31 +0000 (00:14 +0530)]
am65x: yaml: Add AM65x board config files
Added YAML configs for AM65x
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:30 +0000 (00:14 +0530)]
j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img
Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP
images.
HS-SE:
* tiboot3-j7200_sr2-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-j7200_sr2-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-j7200-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by J7200 requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:29 +0000 (00:14 +0530)]
j7200: yaml: Add J7200 board config files
Added YAML configs for J7200
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:28 +0000 (00:14 +0530)]
j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img
By providing entries in the binman node of the device tree, binman will
be able to find and package board config artifacts generated by
TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.
It will also pick out the R5 SPL and sign it with the help of TI signing
entry and generate the final tiboot3.bin.
Entries for A72 build have been added to k3-j721e-binman.dtsi to
generate tispl.bin and u-boot.img.
Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images
In HS-SE, the encrypted system firmware binary must be signed along with
the signed certificate binary.
HS-SE:
* tiboot3-j721e_sr1_1-hs-evm.bin
* sysfw-j721e_sr1_1-hs-evm.itb
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-j721e_sr2-hs-fs-evm.bin
* sysfw-j721e_sr2-hs-fs-evm.itb
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin -->tiboot3-j721e-gp-evm.bin
* sysfw.itb --> sysfw-j721e-gp-evm.itb
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by J721E requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
sysfw.itb:
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:27 +0000 (00:14 +0530)]
j721e: schema: yaml: Add general schema and J721E board config files
Schema file in YAML must be provided in board/ti/common for validating
input config files and packaging system firmware. The schema includes
entries for rm-cfg, board-cfg, pm-cfg and sec-cfg.
Board config files must be provided in board/ti/<devicename> in YAML.
These can then be consumed for generation of binaries to package system
firmware. Added YAML configs for J721E in particular.
Signed-off-by: Tarun Sahu <t-sahu@ti.com>
[n-francis@ti.com: prepared patch for upstreaming]
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:26 +0000 (00:14 +0530)]
arm: dts: k3: Add support for packaging sysfw.itb and tiboot3.bin
Board config binary artifacts must be generated to be used by binman to
package sysfw.itb and tiboot3.bin for all K3 devices.
For devices that follow combined flow, these board configuration
binaries must again be packaged into a combined board configuration
blobs to be used by binman to package tiboot3.bin.
Add common k3-binman.dtsi to generate all the board configuration
binaries needed.
Also add custMpk.pem and ti-degenerate-key.pem needed for signing GP and
HS bootloader images common to all K3 devices.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:25 +0000 (00:14 +0530)]
binman: ti-secure: Add support for TI signing
The ti-secure entry contains certificate for binaries that will be
loaded or booted by system firmware whereas the ti-secure-rom entry
contains certificate for binaries that will be booted by ROM. Support
for both these types of certificates is necessary for booting of K3
devices.
Reviewed-by: Simon Glass <sjg@chromium.org>
[vigneshr@ti.com: fixed inconsist cert generation by multiple packing]
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 21 Jul 2023 18:44:24 +0000 (00:14 +0530)]
binman: ti-board-config: Add support for TI board config binaries
The ti-board-config entry loads and validates a given YAML config file
against a given schema, and generates the board config binary. K3
devices require these binaries to be packed into the final system
firmware images.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Tom Rini [Fri, 21 Jul 2023 23:33:05 +0000 (19:33 -0400)]
Merge branch '2023-07-21-assorted-TI-platform-updates'
- The first half of a number of TI platform bugfixes and improvements,
primarily around K3 platforms and splash screen support.
Samuel Dionne-Riel [Tue, 18 Jul 2023 08:57:36 +0000 (14:27 +0530)]
common: Kconfig: Fix CMD_BMP/BMP dependency
Using `default y` will not select BMP when CMD_BMP has been enabled, if
it was already configured.
By using `select`, if `CMD_BMP` is turned on, it will force the presence
of `BMP`.
Fixes:
072b0e16c4 ("common: Kconfig: Add BMP configs")
Signed-off-by: Samuel Dionne-Riel <samuel@dionne-riel.com>
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:35 +0000 (14:27 +0530)]
doc: board: ti: am62x_sk: Add A53 SPL DDR layout
To understand usage of DDR in A53 SPL stage, add a table showing region
and space used by major components of SPL.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:34 +0000 (14:27 +0530)]
configs: am62x_evm_a53: Add bloblist address
Set bloblist address to 0x80D00000.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:33 +0000 (14:27 +0530)]
common: spl: spl: Remove video driver
Use config SPL_VIDEO_REMOVE to remove video driver at SPL stage before
jumping to next stage, in place of CONFIG_SPL_VIDEO, to allow user to
remove video if required.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:32 +0000 (14:27 +0530)]
drivers: video: Kconfig: Add config remove video
This is required since user may want to either call the remove method
of video driver and reset the display or not call the remove method
to continue displaying until next stage.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:31 +0000 (14:27 +0530)]
common: board_f: Pass frame buffer info from SPL to u-boot
U-boot proper can use frame buffer address passed from SPL to reserve
the memory area used by framebuffer set in SPL so that splash image
set in SPL continues to get displayed while u-boot proper is running.
Put the framebuffer address and size in a bloblist to make them
available at u-boot proper, if in u-boot proper CONFIG_VIDEO is defined.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:30 +0000 (14:27 +0530)]
include: video: Reserve video using blob
Add method to reserve video framebuffer information using blob,
received from previous stage.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:29 +0000 (14:27 +0530)]
board: ti: am62x: evm: Update function calls for splash screen
Use spl_dcache_enable, in place of setup_dram, arch_reserve_mmu to set
up pagetable, initialise DRAM and enable Dcache to avoid multiple
function calls.
Check for CONFIG_SPL_VIDEO in place of CONFIG_SPL_VIDEO_TIDSS to prevent
any build failure in case video config is not defined and video related
functions are called.
Check for CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_BMP before calling
splash_display to avoid compilation failure.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:28 +0000 (14:27 +0530)]
arch: arm: mach-k3: common: Return a pointer after setting page table
In spl_dcache_enable after setting up page table, set gd->relocaddr
pointer to tlb_addr, to get next location to reserve memory. Align
tlb_addr with 64KB address.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Nikhil M Jain [Tue, 18 Jul 2023 08:57:27 +0000 (14:27 +0530)]
common: spl: spl: Update stack pointer address
At SPL stage when stack is relocated, the stack pointer needs to be
updated, the stack pointer may point to stack in on chip memory even
though stack is relocated.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Bryan Brattlof [Mon, 17 Jul 2023 23:01:33 +0000 (18:01 -0500)]
arm: mach-k3: am62a7: change some prints to debug prints
There is little need to print the devstat information or when we exit a
function during a typical boot. Remove them to reduce the noise during
typical operation
Signed-off-by: Bryan Brattlof <bb@ti.com>
Bryan Brattlof [Mon, 17 Jul 2023 22:15:26 +0000 (17:15 -0500)]
ram: k3-ddrss: do not touch ctrl regs during training
During LPDDR initialization we will loop through a series of frequency
changes in order to train at the various operating frequencies. During
this training, accessing the DRAM_CLASS bitfield could happen during a
frequency change and cause the read to hang.
Store the DRAM type into the main structure to avoid multiple readings
while the independent phy is training.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Tom Rini [Mon, 17 Jul 2023 19:26:43 +0000 (15:26 -0400)]
arm: omap2: Fix warning in force_emif_self_refresh
The function declaration for force_emif_self_refresh takes no parameters
but does not specify this, only the prototype in the headers do. As
clang will warn about this, correct it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Andrew Davis [Fri, 14 Jul 2023 19:00:58 +0000 (14:00 -0500)]
configs: k2x_evm: Always include FIT loading support
Non-HS boards can use FIT images so include the env var commands
for these unconditionally.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Emanuele Ghidoli [Fri, 14 Jul 2023 15:23:10 +0000 (17:23 +0200)]
arm: mach-k3: am62: Fixup CPU core, gpu and pru nodes in fdt
AM62x SoC is available in multiple variant:
- CPU cores (Cortex-A) AM62x1 (1 core), AM62x2 (2 cores), AM62x4 (4 cores)
- GPU AM625x with GPU, AM623x without GPU
- PRU (Programmable RT unit) can be present or not on AM62x2/AM62x4
Remove the relevant FDT nodes by reading the actual configuration
from the SoC registers, with that change is possible to have a single
dts/dtb file handling the different variant at runtime.
While removing GPU node and CPU nodes also the watchdog node
in the same Module Domain is removed.
A similar approach is implemented for example on i.MX8 and STM32MP1 SoC.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Emanuele Ghidoli [Fri, 14 Jul 2023 15:23:09 +0000 (17:23 +0200)]
arm: mach-k3: am62: Add CTRLMMR_WKUP_JTAG_DEVICE_ID register definition
Add register address and relevant bitmasks and shifts.
Allow reading these information:
- device identification
- number of cores (part of device identification)
- features (currently: PRU / no PRU)
- security
- functional safety
- speed grade
- temperature grade
- package
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Emanuele Ghidoli [Fri, 14 Jul 2023 15:23:08 +0000 (17:23 +0200)]
arm: k3: Fix ft_system_setup so it can be enabled on any SoC
ft_system_setup cannot be enabled on SoC without msmc sram otherwise
fdt_fixup_msmc_ram function fails causing system reset.
Fix by moving fdt_fixup_msmc_ram to common_fdt.c file and creating
SoC (AM654, J721E and J721S2) specific files for fdt fixups.
This change was verified to not change anything on any existing board
(all the J721S2, AM654 and J721E boards requires it,
none of the remaining k3 boards require it).
Fixes:
30e96a240156 ("arm: mach-k3: Move MSMC fixup to SoC level")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Nishanth Menon [Thu, 13 Jul 2023 19:40:51 +0000 (14:40 -0500)]
arm: dts: Fix build of am62a7 dtbs
am62a7 should be built with CONFIG_SOC_K3_AM62A7 not CONFIG_SOC_K3_AM625
Fixes:
6bdfa69155d8 ("arm: dts: introduce am62a7 u-boot dtbs")
Cc: Bryan Brattlof <bb@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Francesco Dolcini <francesco@dolcini.it>
Cc: Sjoerd Simons <sjoerd@collabora.com>
Cc: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Nishanth Menon [Thu, 13 Jul 2023 19:36:34 +0000 (14:36 -0500)]
arm: mach-k3: *: dev-data: Update to use ARRAY_SIZE
Instead of hard-coding the count of entries manually, use ARRAY_SIZE
to keep the count updates appropriately.
Cc: Bryan Brattlof <bb@ti.com>
Suggested-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Vignesh Raghavendra [Sun, 2 Jul 2023 09:16:54 +0000 (14:46 +0530)]
arm: mach-k3: am62a7_init: Open up FSS_DAT_REG3 firewall
On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that
is present in above 64bit region. Open this up in bootloader to allow
Linux to access OSPI flashes in mmap mode.
Without this kernel will crash when accessing this region due to
firewall violations on HS-SE devices.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nikhil M Jain [Wed, 21 Jun 2023 10:59:53 +0000 (16:29 +0530)]
common: splash_source: Fix type casting errors
During compilation splash_source puts out below warning for type
conversion in splash_load_fit for bmp_load_addr and fit_header.
Change their type to uintptr_t to fix the warnings.
common/splash_source.c: In function ‘splash_load_fit’:
common/splash_source.c:366:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
366 | img_header = (struct legacy_img_hdr *)bmp_load_addr;
| ^
common/splash_source.c:376:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
376 | res = splash_storage_read_raw(location, (u32)fit_header, fit_size);
| ^
common/splash_source.c:401:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
401 | memmove((void *)bmp_load_addr, internal_splash_data, internal_splash_size);
The above warnings are generated if CONFIG_FIT is enabled.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Nikhil M Jain [Wed, 21 Jun 2023 10:59:52 +0000 (16:29 +0530)]
board: ti: am62x: evm: Include necessary header files
At the time of compilation evm.c gives below warning for implicit
declaration of enable_caches, to mitigate this include cpu_func.h.
board/ti/am62x/evm.c: In function ‘spl_board_init’:
board/ti/am62x/evm.c:90:9: warning: implicit declaration of function ‘enable_caches’ [-Wimplicit-function-declaration]
90 | enable_caches();
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Tom Rini [Fri, 21 Jul 2023 14:01:11 +0000 (10:01 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
For once this adds USB support for two SoCs: the H616 and the F1C100s
series. The rest is support for LPDDR3 DRAM chips on H616 boards.
Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s
board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that
works for Mikhail, and doesn't regress on my DDR3 boards.
Tom Rini [Fri, 21 Jul 2023 13:57:59 +0000 (09:57 -0400)]
Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.10-rc1 v2
axi_emac:
- Change return value if RX packet is not ready
cadence_qspi:
- Enable flash reset for Versal NET
dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location
fpga:
- Add load event
mtd:
- Add missing dependency for FLASH_CFI_MTD
spi/nand:
- Minor cleanup in Xilinx drivers
versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations
watchdog:
- Use new versal-wwdt property
xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email
zynqmp_clk:
- Add handling for gem rx/tsu clocks
zynq_gem:
- Configure mdio clock at run time
zynq:
- Enable fdt overlay support
zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
Christian Taedcke [Thu, 20 Jul 2023 07:27:24 +0000 (09:27 +0200)]
event: Add fpga load event
This enables implementing custom logic after a bitstream was loaded
into the fpga.
Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/20230720072724.11516-1-christian.taedcke-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Thu, 20 Jul 2023 07:28:59 +0000 (01:28 -0600)]
clk: zynqmp: Add gem rx and tsu clocks to return register
Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 19 Jul 2023 08:49:12 +0000 (02:49 -0600)]
clk: zynqmp: Add set_rate support for gem rx and tsu clks
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Maksim Kiselev [Wed, 19 Jul 2023 06:53:37 +0000 (09:53 +0300)]
net: axi_emac: Change return value to -EAGAIN if RX is not ready
If there is no incoming package than axiemac_recv will return -1 which
in turn leads to printing `eth_rx: recv() returned error -1` error
message in eth_rx function. But missing a package is not an fatal error,
so return -EAGAIN in that case would be more suitable.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20230719065337.69280-1-bigunclemax@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Michal Simek [Mon, 10 Jul 2023 12:37:43 +0000 (14:37 +0200)]
arm64: zynqmp: Remove clock-names from pcap node
Clock is not used in driver and also not described in binding.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a0fa0ba197fa4051a2c8a24e1451cefadce7517.1688992653.git.michal.simek@amd.com
Michal Simek [Mon, 10 Jul 2023 12:37:42 +0000 (14:37 +0200)]
arm64: zynqmp: Rename ams_ps/pl node names
Fix child node names to be aligned with dt-binding available in the Linux
kernel which requires names as ams-ps@ and ams-pl@.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8f1451d614f654cb0d0da1e799e876c078fbf2c9.1688992653.git.michal.simek@amd.com
Michal Simek [Mon, 10 Jul 2023 12:37:41 +0000 (14:37 +0200)]
arm64: zynqmp: Remove interrupt/reg-names for AMS
These two properties are not described in DT binding and also not used by
driver that's why remove them.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b123c7e537dcf70802e828bbcd484a761a264186.1688992653.git.michal.simek@amd.com
Piyush Mehta [Mon, 10 Jul 2023 12:37:40 +0000 (14:37 +0200)]
arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usb
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk'
quirk for usb. This quirk is no more available in linux after the xilinx
release 2022.2.
This functionality is taken care of by the 'snps,resume-hs-terminations'
quirk.
Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com
Radhey Shyam Pandey [Mon, 10 Jul 2023 12:37:39 +0000 (14:37 +0200)]
arm64: zynqmp: add pmu interrupt-affinity
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
guessing.
Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com
Michal Simek [Mon, 10 Jul 2023 12:37:38 +0000 (14:37 +0200)]
arm64: zynqmp: Sync node name address with reg (mailbox)
Address in node name should match with the first reg property in DT.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/47bea10bbc3c88727c1fe839ff20e15a0c79c339.1688992653.git.michal.simek@amd.com
Radhey Shyam Pandey [Mon, 10 Jul 2023 12:37:37 +0000 (14:37 +0200)]
arm64: zynqmp: Add L2 cache nodes
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.
Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
Michal Simek [Mon, 10 Jul 2023 12:37:36 +0000 (14:37 +0200)]
arm64: zynqmp: Fix usb reset over bootmode pins on zcu100
The commit
a4180c369607 ("arm64: zynqmp: Add mode-pin GPIO controller DT
node") added usb phy reset over bootmode pins by default on usb0 only.
zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset
line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744
hub which is used only in host mode. Especially this chip requires reset to
operate properly that's why better assign gpio reset to usb1 instead of
usb0.
Without this change usb start crashed when runs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com
Michal Simek [Mon, 10 Jul 2023 12:37:35 +0000 (14:37 +0200)]
arm64: zynqmp: Cover K24 revB/1 SOM
Extend compatible versions for K24 SOM.
Changes are not affecting SW behavior that's why all versions are
compatible to each other.
Describing all revisions is done by purpose because user space SW is
reading compatible string for logic around DT overlays and bitstreams.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com
Michal Simek [Mon, 10 Jul 2023 12:37:34 +0000 (14:37 +0200)]
arm64: zynqmp: Record compatible string for kv260 rev2
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335
autofocus feature). PS side is completely unchanged.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/42f78dee8429eeac016d73de5c73af46fdaf4a98.1688992653.git.michal.simek@amd.com
Harini Katakam [Mon, 10 Jul 2023 12:37:33 +0000 (14:37 +0200)]
arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KV and KD carrier cards to allow PTP functionality.
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com
Harini Katakam [Mon, 10 Jul 2023 12:37:32 +0000 (14:37 +0200)]
arm64: zynqmp: Increase reset assert time for TI SGMII PHY
Increase reset assert time for TI SGMII PHY on KR260 CC starting
6.1 kernel. This PHY does not come out of reset with the existing
100us pulse width as per testing on multiple carrier cards. The reset
is driven via a PCA9570 I2C expander. The expander driver was updated
to an upstream version in 6.1 where gpio_chip _set was optimized.
Delays in earlier kernels may have masked this issue. This is a safe
workaround value for assert pulse width before the discussions are
resolved with TI.
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
Michal Simek [Mon, 10 Jul 2023 12:37:31 +0000 (14:37 +0200)]
arm64: zynqmp: Fix gpio comment about No of gpios
There are total 174 gpios but from 0 - 173 that's why fix comment to
reflect it.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com
Harini Katakam [Mon, 10 Jul 2023 12:37:30 +0000 (14:37 +0200)]
arm64: zynqmp: Assign TSU clock frequency for KR260
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KR260 CC to allow PTP functionality.
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com
Parth Gajjar [Mon, 10 Jul 2023 12:37:29 +0000 (14:37 +0200)]
arm64: zynqmp: Update MALI 400 interrupt and clock names
Motivation for the commit is to utilize the upstream community
device tree so that the either modified ARM Mali 400 driver
or upstream lima driver can be used.
Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
Manikanta Guntupalli [Mon, 10 Jul 2023 12:37:28 +0000 (14:37 +0200)]
xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by
Linux.
"enforced open drain please flag it properly in DT/ACPI DSDT/board
file."
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
Varalaxmi Bingi [Mon, 10 Jul 2023 12:37:27 +0000 (14:37 +0200)]
arm: xilinx: Setting default i2c clock frequency to 400kHz
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of
400kHz. Current default value is 100kHz.
Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
Michal Simek [Tue, 4 Jul 2023 12:04:04 +0000 (14:04 +0200)]
mtd: Add missing MTD dependency for cfi_mtd
cfi_mtd requires add_mtd_device() which is available only when MTD is
enabled that's why record this dependency.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/76ae01ce2b2c988758b69e0f0cdcc21bf301c01e.1688472227.git.michal.simek@amd.com
Ashok Reddy Soma [Mon, 10 Jul 2023 12:11:59 +0000 (14:11 +0200)]
mmc: zynq_sdhci: Dll reset only for ZynqMP platform
Dll reset is needed only for ZynqMP platforms, add condition in tuning
to call arasan_zynqmp_dll_reset() just for ZynqMP platforms.
On other platforms like Versal NET, If this condition is not added, we
see PLM error messages when dll reset smc is called.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d673ff3bdc5c236a7f0403c920e719684abd6059.1688991117.git.michal.simek@amd.com
Michal Simek [Mon, 10 Jul 2023 12:35:49 +0000 (14:35 +0200)]
arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
Raju Kumar Pothuraju [Mon, 10 Jul 2023 11:56:21 +0000 (13:56 +0200)]
xilinx: zynq: Enable fdt apply utility for zynq
Enables the FDT library (libfdt) overlay support for zynq platforms
to be able to use fdt apply command.
Signed-off-by: Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ab26dd186fb752b3d607e6160ae5baf6661d5de7.1688990179.git.michal.simek@amd.com
Michal Simek [Fri, 23 Jun 2023 12:51:57 +0000 (14:51 +0200)]
xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h
zynqmp_mmio_read/write() are firmware provided hooks that's why use only
zynqmp_firmware.h for function declaration.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
Ashok Reddy Soma [Wed, 14 Jun 2023 12:13:51 +0000 (06:13 -0600)]
xilinx: versal-net: Add mini eMMC 5.1 configuration
Add support for Versal NET mini eMMC 5.1 configuration. Add device tree
and defconfig.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 14 Jun 2023 12:13:50 +0000 (06:13 -0600)]
xilinx: versal-net: Add mini ospi configuration
Add support for Versal NET mini Octal SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Octal SPI
related settings are enabled.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 14 Jun 2023 12:13:49 +0000 (06:13 -0600)]
xilinx: versal-net: Add mini qspi configuration
Add support for Versal NET mini Quad SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Quad SPI
related settings are enabled.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 14 Jun 2023 12:04:52 +0000 (06:04 -0600)]
cadence_qspi: Enable flash reset for Versal NET platform
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.
Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.
Add read_delay initialization for Versal NET also.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Venkatesh Yadav Abbarapu [Mon, 19 Jun 2023 03:49:22 +0000 (09:19 +0530)]
net: zynq_gem: Don't hardcode the MDC clock divisor
As per spec MDC must not exceed 2.5MHz, read the pclk clock
from the device tree and update the MDC clock divisor.
GEM devices support larger clock divisors and have a different
range of divisors. Program the MDIO clock divisors based on
the clock rate of the pclk clock.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230619034922.24019-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 14 Jun 2023 09:30:58 +0000 (03:30 -0600)]
arm64: versal-net: spi: Update boot sequence dynamically
Currently xspi0 is used for all spi boot modes, it means it will use "sf
probe 0 0 0" for all spi's irrespective of which node it is wired.
Get boot sequence from dev_seq() and update boot command for xspi
dynamically.
As a result bootcmd for spi is updated as below when two instances of spi
are present in DT node.
bootcmd_xspi0=devnum_xspi=0; run xspi_boot
bootcmd_xspi1=devnum_xspi=1; run xspi_boot
xspi_boot=sf probe $devnum_xspi:0 0 0 && sf read $scriptaddr
$script_offset_f $script_size_f && echo XSPI: Trying to boot script at
${scriptaddr} && source ${scriptaddr}; echo XSPI: SCRIPT FAILED:
continuing...;
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614093058.30438-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Algapally Santosh Sagar [Wed, 14 Jun 2023 09:03:59 +0000 (03:03 -0600)]
xilinx: zynq: Add the missing function prototypes
Add the missing prototypes for the functions pointed by the below
sparse warnings
warning: no previous prototype for 'set_dfu_alt_info'
[-Wmissing-prototypes]
warning: no previous prototype for 'board_debug_uart_init'
[-Wmissing-prototypes]
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-7-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Algapally Santosh Sagar [Wed, 14 Jun 2023 09:03:58 +0000 (03:03 -0600)]
arm: zynq: Pass the missing argument type in function definition
Pass missing argument type in the function definition to fix the
sparse warning, warning: old-style function definition
[-Wold-style-definition]
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-6-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Algapally Santosh Sagar [Wed, 14 Jun 2023 09:03:57 +0000 (03:03 -0600)]
mtd: nand: zynq_nand: Change datatype of status and ecc_status to int
status and ecc_status are of unsigned type where they are compared for
negative value. This is pointed by below sparse warning. Change datatype
to int to fix this.
warning: comparison of unsigned expression in '< 0' is always false
[-Wtype-limits]
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Algapally Santosh Sagar [Wed, 14 Jun 2023 09:03:56 +0000 (03:03 -0600)]
spi: zynq_qspi: Add missing prototype for zynq_qspi_mem_exec_op
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynq_qspi_mem_exec_op' [-Wmissing-prototypes].
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Algapally Santosh Sagar [Wed, 14 Jun 2023 09:03:55 +0000 (03:03 -0600)]
xilinx: zynq: Add missing prototype for zynqmp_mmio_write
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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