Marek Olšák [Thu, 22 Apr 2021 04:38:37 +0000 (00:38 -0400)]
radeonsi: remove 8 bytes from si_resource, turn other 4 bytes into padding
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 22 Apr 2021 04:31:28 +0000 (00:31 -0400)]
radeonsi: change si_resource::alignment to alignment_log2 for better packing
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sun, 9 May 2021 22:33:24 +0000 (18:33 -0400)]
radeonsi: improve generated culling code by adding optimization barriers
This removes a lot of instructions and 16 bytes from the code size.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Mon, 10 May 2021 11:44:42 +0000 (07:44 -0400)]
radeonsi: re-enable fast launch with indexed tri strips because it doesn't hang
I don't know which change fixed this, but I can't reproduce the hang anymore.
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Tue, 11 May 2021 00:31:19 +0000 (20:31 -0400)]
radeonsi: remove a twice duplicated workaround for VERT_GRP_SIZE
This enables better lane occupancy.
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Mon, 10 May 2021 10:53:46 +0000 (06:53 -0400)]
radeonsi: fix the fast launch vert/prim thread counts if they are trimmed
This fixes the case when the counts were out of sync because one of them
was decreased.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Tue, 11 May 2021 13:11:34 +0000 (09:11 -0400)]
radeonsi: don't use GS fast launch with small instances
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 03:52:19 +0000 (23:52 -0400)]
radeonsi: don't disable L2 caching for staging textures
Uncached access can be slow if the box is not aligned nicely.
Also, caching in L2 might enable bigger PCIe bursts.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 03:47:23 +0000 (23:47 -0400)]
radeonsi: always use the L2 LRU cache policy for faster clears and copies
Waves and CP DMA can finish sooner if L2 doesn't do any evictions, which
is hard to predict.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Tue, 11 May 2021 00:03:04 +0000 (20:03 -0400)]
radeonsi: fix a coherency issue when VS memory stores are not visible in PS
If a shader has no param exports (no varyings), the pixel shader can start
after the VS position is written before the vertex shader finishes.
The fix is to wait for the memory stores before the position export.
The code needs to be restructured. First prepare param exports to get
nr_param_exports, then emit position exports with the wait, and then
emit param exports.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 02:52:42 +0000 (22:52 -0400)]
radeonsi: add a gfx10 bug workaround for NOT_EOP
Fixes:
cc24ec8c077 - radeonsi: set NOT_EOP for back-to-back draws on gfx10+
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 22 Apr 2021 02:14:03 +0000 (22:14 -0400)]
radeonsi: handle PIPE_CAP_MAX_VERTEX_BUFFERS
no change in behavior because the value is the same as the default
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 6 May 2021 21:37:24 +0000 (17:37 -0400)]
radeonsi: remove unused SI_IMAGE_ACCESS_AS_BUFFER
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Fri, 7 May 2021 13:17:12 +0000 (09:17 -0400)]
winsys/amdgpu: don't hold a mutex while accessing is_shared
It adds overhead to amdgpu_bo_wait and I'm not sure whether the mutex
is even needed.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Wed, 12 May 2021 16:00:31 +0000 (12:00 -0400)]
ac/llvm: don't draw the primitive for the dummy export workaround for Navi1x
for conservative rasterization
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 10:14:15 +0000 (06:14 -0400)]
ac/llvm: set range metadata on mbcnt and deduplicate get_thread_id
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 08:24:58 +0000 (04:24 -0400)]
ac/llvm: allow ac_build_optimization_barrier with SGPRs, pointers, and metadata
sgpr=true prevents moving the value to a VGPR.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 09:26:04 +0000 (05:26 -0400)]
ac/llvm: expose set_range_metadata to more users
I sometimes use it for experiments. It will be used later.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 04:34:05 +0000 (00:34 -0400)]
ac/llvm: set target features per function instead of per target machine
This is a cleanup that allows the removal of the wave32 target machine and
the wave32 pass manager.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Wed, 28 Apr 2021 03:51:24 +0000 (23:51 -0400)]
ac/gpu_info: set has_zero_index_buffer_bug for Navi12 too
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Fri, 7 May 2021 11:01:44 +0000 (07:01 -0400)]
amd: fix incorrect addrlib comment for HTILE equations
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Fri, 7 May 2021 08:09:16 +0000 (04:09 -0400)]
amd/registers: regenerate json files without 32-bit register fields
Only a few of those were used in drivers.
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Fri, 7 May 2021 07:57:36 +0000 (03:57 -0400)]
amd/registers: don't generate 32-bit register fields
This removes confusing register types due to deduplication, such as:
"name": "SQ_WAVE_TTMP10",
"type_ref": "SPI_SHADER_USER_DATA_PS_0"
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Samuel Pitoiset [Wed, 19 May 2021 07:14:13 +0000 (09:14 +0200)]
radv: remove an useless TODO for dynamic line width
We can't do anything it seems.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10881>
Samuel Pitoiset [Wed, 19 May 2021 07:13:54 +0000 (09:13 +0200)]
radv: ignore dynamic blend constants if blend isn't enabled
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10881>
Timur Kristóf [Fri, 21 May 2021 12:14:33 +0000 (14:14 +0200)]
aco: Don't eliminate exec write when it's used by a copy later.
Fixes:
bc130497472cb4ec4ec60695ed99b169d6681118
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10920>
Alyssa Rosenzweig [Fri, 5 Mar 2021 20:59:39 +0000 (20:59 +0000)]
panfrost: Add message preload to pan_shader_info
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10967>
Alyssa Rosenzweig [Fri, 5 Mar 2021 15:55:47 +0000 (15:55 +0000)]
panfrost: Add Message Preload descriptor XML
New to v7, allows executing up to +LD_VAR_IMM or +VAR_TEX instructions
before starting the shader.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10967>
Alyssa Rosenzweig [Mon, 24 May 2021 14:04:44 +0000 (10:04 -0400)]
panfrost/ci: Run jobs with PAN_MESA_DEBUG=sync
This way if there's a fault, the pipeline won't accidentally pass
and let bugs slip into main. This seems to have occurred on both T720
and G72, leading to flakes on both. I want flakeless CI, so this is a
step in eliminating flakes before they hit the tree.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Fri, 21 May 2021 22:14:22 +0000 (18:14 -0400)]
panfrost/ci: Remove reference to dated flag
This was removed ages ago, nobody updated it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Mon, 24 May 2021 21:06:41 +0000 (17:06 -0400)]
panfrost/ci: Disable terrain trace
It's reliably faulting in CI but not locally, and I can't figure out
what the difference could possibly be. Regardless I can't fix the fault
otherwise, and faultless CI matters more than losing a single trace
(from an app I manually test anyway).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Mon, 24 May 2021 15:07:11 +0000 (11:07 -0400)]
panfrost: Increase tiler_heap max allocation to 64MB
We previously allocated only 16MB, but this isn't always enough. Now
that we have growable (heap) on recent kernels, there's not much reason
to try to shrink this allocation.
Fixes OUT_OF_MEMORY fault on furmark trace.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Fri, 21 May 2021 21:42:19 +0000 (17:42 -0400)]
panfrost: Remove minimal mode
Superseded by abort-on-fault. It didn't work correctly in the presence
of MMU faults anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Fri, 21 May 2021 21:38:00 +0000 (17:38 -0400)]
panfrost: Abort on faults in SYNC mode
This allows failing fast (optionally still tracing, if set with
PAN_MESA_DEBUG=trace) when a GPU fault is introduced. This is better
behaviour for both use cases:
1. When debugging a known fault, setting this mode together with trace
will stop the driver as soon as a buggy command stream is submitted,
and the offending stream will be the last trace file.
2. When running test suites (particularly in CI), setting this mode
will detect faults and crash, causing the pipeline to fail fast as
opposed to incorrectly marking the run green if the test happens to
pass despite the faults and slow downs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Fri, 21 May 2021 21:30:34 +0000 (17:30 -0400)]
panfrost: Lower max inputs again
Due to Midgard ABI silliness. We could fix this properly but I'm not
aware of any app that needs more than 16, so let's just revert to the
behaviour matching the DDK.
Fixes:
fdbf8c96fe2 ("panfrost: Use natural shader limits")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Lucas Stach [Fri, 13 Nov 2020 14:05:55 +0000 (15:05 +0100)]
etnaviv: flush used render buffers on context flush when neccessary
Some resources like backbuffers are explicitly flushed by the frontend
at the appropriate time, others however won't get flushed explicitly.
Remember those resources when they get emitted as a render buffer and
flush them on a context flush to make their content visible to other
entities sharing the buffer.
We still keep the optimized path for most resources where the frontend
promises to do the flushing for us and only enable implicit flushing
when a buffer handle is exported/imported without the
PIPE_HANDLE_USAGE_EXPLICIT_FLUSH flag set.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7603>
Lucas Stach [Fri, 13 Nov 2020 14:03:37 +0000 (15:03 +0100)]
etnaviv: remove double assigment of surface->texture
surf->base.texture is already assigned earlier via a proper
pipe_resource_reference call. Remove the superfluous assignement.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7603>
Lucas Stach [Fri, 13 Nov 2020 13:59:52 +0000 (14:59 +0100)]
frontend/dri: add EXPLICIT_FLUSH hint in dri2_resource_get_param
dri2_resource_get_param() is called from two different places right now.
Only one of them adds the EXPLICIT_FLUSH hint to the handle usage, which
may disable the optimizations provided by this hint without a reason.
Make sure to always add this hint when appropriate.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7603>
Lionel Landwerlin [Fri, 21 May 2021 15:36:31 +0000 (18:36 +0300)]
intel/perf: rename metric descriptions
There is an effort to drop the "Gen" prefix from much of our codebase.
This just applies this to the metrics.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Lionel Landwerlin [Fri, 21 May 2021 15:35:46 +0000 (18:35 +0300)]
intel/perf: update Gen9/11 programming for AsyncCompute
Adding a register, similar to what was done for RenderBasic.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Lionel Landwerlin [Fri, 21 May 2021 15:35:07 +0000 (18:35 +0300)]
intel/perf: add EHL availability condition to HDCAndSF counters
The availability of those counters depends on the topology.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Lionel Landwerlin [Fri, 21 May 2021 15:34:41 +0000 (18:34 +0300)]
intel/perf: update Gen11 RenderBasic programming
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Lionel Landwerlin [Fri, 21 May 2021 15:34:08 +0000 (18:34 +0300)]
intel/perf: update Gen11 RenderBasic programming
Simple order change.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Lionel Landwerlin [Fri, 21 May 2021 15:33:20 +0000 (18:33 +0300)]
intel/perf: update gen9/11 TestOa configs
Programming an additional FLEX register.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Iago Toral Quiroga [Wed, 19 May 2021 12:27:28 +0000 (14:27 +0200)]
v3dv: expose VK_KHR_maintenance2
We don't do anything for input attachment aspects read by a subpass
since it doesn't have performance implications for us.
We also ignore the the new depth stencil layouts because they don't
have practical implications for our implementation.
We also ignore the new usage info for views since we are not currently
making decisions about views based on their usage.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10951>
Iago Toral Quiroga [Mon, 24 May 2021 09:24:02 +0000 (11:24 +0200)]
v3dv: allow creating uncompressed views from compressed images and vice versa
Relevant CTS tests (requires VK_KHR_maintenance2):
dEQP-VK.image.texel_view_compatible.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10951>
Iago Toral Quiroga [Mon, 24 May 2021 09:20:50 +0000 (11:20 +0200)]
v3dv: fix texture_size()
The uniform data for the texture size as produced by the compiler
contains the texture index directly and is not packed with
v3d_unit_data_create, so using v3d_unit_data_get_unit is not
correct.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10951>
Iago Toral Quiroga [Wed, 19 May 2021 07:08:23 +0000 (09:08 +0200)]
v3dv: implement VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
Relevant CTS test (requires VK_KHR_maintenance2);
dEQP-VK.clipping.clip_volume.clipped.large_points
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10951>
Erik Faye-Lund [Mon, 24 May 2021 15:47:34 +0000 (17:47 +0200)]
zink: simplify emit_load_const
This is the combination of two simplifications I spotted while
researching some other issue:
1. We can use nir_const_value_as_uint to save some conditionals
2. We can unify the vector and scalar code-paths to reduce some
duplicated logic.
While we're at it, switch to using NIR_MAX_VEC_COMPONENTS rather than a
dynamic array size on the stack, because that tends to generate better
code.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10956>
Tomeu Vizoso [Mon, 24 May 2021 09:37:09 +0000 (11:37 +0200)]
ci/piglit: Use wget instead of ci-fairy to check a file exists
ci-fairy minio ls will try to list files in the path given, which for
trace buckets is generally forbidden. We don't really need to do any
listing in this case, so use wget instead to check that the reference
image doesn't exist yet.
Previous to this patch, trace jobs would re-upload all reference images
to minio every time because they wouldn't be able to verify that the
reference image was already there. Jobs would often take up to 4 minutes
needlessly re-uploading these files.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10953>
Yiwei Zhang [Sat, 22 May 2021 03:32:09 +0000 (03:32 +0000)]
radv: fix AHB leak upon exportable allocation
A successful AHardwareBuffer_allocate itself will increase a refcount on
the newly allocated AHB. For the import case, the implementation must
acquire a reference on the AHB. So if we layer the exportable allocation
on top of AHB allocation and AHB import, we must release an AHB
reference to avoid leak.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10940>
Yiwei Zhang [Sat, 22 May 2021 03:21:05 +0000 (03:21 +0000)]
anv: fix AHB leak upon exportable allocation
A successful AHardwareBuffer_allocate itself will increase a refcount on
the newly allocated AHB. For the import case, the implementation must
acquire a reference on the AHB. So if we layer the exportable allocation
on top of AHB allocation and AHB import, we must release an AHB
reference to avoid leak.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10940>
Icecream95 [Fri, 29 May 2020 08:06:36 +0000 (20:06 +1200)]
pan/mdg: Try scheduling load/store ops in pairs
If there are an even number of load/store ops to be scheduled, and
only one load/store op is available for scheduling, try using another
instruction type.
Helps bundle count at the cost of register pressure.
total instructions in shared programs: 333405 -> 333599 (0.06%)
instructions in affected programs: 27576 -> 27770 (0.70%)
helped: 43
HURT: 69
helped stats (abs) min: 1 max: 61 x̄: 5.49 x̃: 1
helped stats (rel) min: 0.18% max: 11.71% x̄: 2.27% x̃: 1.75%
HURT stats (abs) min: 1 max: 95 x̄: 6.23 x̃: 2
HURT stats (rel) min: 0.06% max: 32.42% x̄: 2.59% x̃: 1.53%
95% mean confidence interval for instructions value: -0.93 4.40
95% mean confidence interval for instructions %-change: -0.09% 1.53%
Inconclusive result (value mean confidence interval includes 0).
total bundles in shared programs: 155785 -> 152371 (-2.19%)
bundles in affected programs: 83689 -> 80275 (-4.08%)
helped: 2538
HURT: 110
helped stats (abs) min: 1 max: 59 x̄: 1.53 x̃: 1
helped stats (rel) min: 0.14% max: 22.52% x̄: 8.71% x̃: 7.69%
HURT stats (abs) min: 1 max: 92 x̄: 4.32 x̃: 1
HURT stats (rel) min: 0.21% max: 55.76% x̄: 4.61% x̃: 2.86%
95% mean confidence interval for bundles value: -1.41 -1.17
95% mean confidence interval for bundles %-change: -8.37% -7.94%
Bundles are helped.
total quadwords in shared programs: 264143 -> 260520 (-1.37%)
quadwords in affected programs: 141705 -> 138082 (-2.56%)
helped: 2560
HURT: 96
helped stats (abs) min: 1 max: 15 x̄: 1.49 x̃: 1
helped stats (rel) min: 0.06% max: 14.29% x̄: 5.62% x̃: 5.00%
HURT stats (abs) min: 1 max: 11 x̄: 2.02 x̃: 2
HURT stats (rel) min: 0.12% max: 6.20% x̄: 1.94% x̃: 1.47%
95% mean confidence interval for quadwords value: -1.42 -1.31
95% mean confidence interval for quadwords %-change: -5.50% -5.20%
Quadwords are helped.
total registers in shared programs: 21709 -> 22156 (2.06%)
registers in affected programs: 2684 -> 3131 (16.65%)
helped: 55
HURT: 470
helped stats (abs) min: 1 max: 2 x̄: 1.05 x̃: 1
helped stats (rel) min: 6.67% max: 40.00% x̄: 15.37% x̃: 14.29%
HURT stats (abs) min: 1 max: 4 x̄: 1.07 x̃: 1
HURT stats (rel) min: 6.67% max: 100.00% x̄: 31.63% x̃: 25.00%
95% mean confidence interval for registers value: 0.79 0.91
95% mean confidence interval for registers %-change: 24.69% 28.72%
Registers are HURT.
total threads in shared programs: 24450 -> 24360 (-0.37%)
threads in affected programs: 234 -> 144 (-38.46%)
helped: 12
HURT: 63
helped stats (abs) min: 1 max: 2 x̄: 1.50 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1 max: 2 x̄: 1.71 x̃: 2
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.49 -0.91
95% mean confidence interval for threads %-change: -38.74% -13.26%
Threads are [HURT].
total loops in shared programs: 286 -> 286 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 521 -> 593 (13.82%)
spills in affected programs: 260 -> 332 (27.69%)
helped: 8
HURT: 9
total fills in shared programs: 1598 -> 1659 (3.82%)
fills in affected programs: 839 -> 900 (7.27%)
helped: 9
HURT: 10
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5745>
Alyssa Rosenzweig [Thu, 13 May 2021 16:17:28 +0000 (12:17 -0400)]
panfrost: Only link varyings once in good conditions
If the varying descriptors will always be the same for a given shader
variant (certainly true if none of separable shaders, transform
feedback, or point sprites are used), we only need to link once. Now
that pan_pool supports both owned and unowned modes, we have the
flexibility to reuse the code path for both allocation strategies.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10954>
Italo Nicola [Tue, 11 May 2021 10:29:01 +0000 (10:29 +0000)]
panfrost: fix GL_EXT_multisampled_render_to_texture regression
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Fixes:
ff3eada7eb4 ("panfrost: Use the generic preload and FB helpers in the gallium driver")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10962>
Marek Olšák [Fri, 16 Oct 2020 13:22:44 +0000 (09:22 -0400)]
amd: add Beige Goby support
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
Aaron Liu [Thu, 17 Sep 2020 08:03:15 +0000 (16:03 +0800)]
amd: add Yellow Carp support
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
Marek Olšák [Fri, 7 May 2021 00:43:34 +0000 (20:43 -0400)]
radeonsi: simplify the NGG culling vertex count heuristic
This removes another chip-specific switch.
It enables a lower threshold on Navi1x, which should be fine.
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
Emma Anholt [Tue, 18 May 2021 23:57:30 +0000 (16:57 -0700)]
mesa/st: Fix iris regression with clip distances.
In general gallium shaders are all SSO and it's up to the driver to handle
lining up varying storage between stages at draw time. However, there's a
NIR option "unify_interfaces" that iris uses which applies to non-SSO (as
indicated by nir->info.separate_shader) shaders and makes the inputs_read
and outputs_written match up at GLSL-to-NIR link time, and then iris then
avoids any lowering passes that would add new varyings.
By introducing info gathering after variant creation (because all I knew
was "gallium is always SSO"), I broke the unify_interfaces link-time setup
on iris. Just skip that when the unify_interfaces flag is set, and add
some asserts to catch anyone trying to mix unify_interfaces with known
varying-adjusting lowering passes.
Closes: #4450
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10876>
Emma Anholt [Mon, 24 May 2021 16:25:35 +0000 (09:25 -0700)]
ci/freedreno: Add glx-copy-sub-buffer to flakes on a530 and a630.
A630 just had one sample count marked, but when piglit's been shuffled,
samples=4 and non-msaa have showed up too. Looks like from our history
a530 is flaky on it too.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emma Anholt [Fri, 21 May 2021 19:53:24 +0000 (12:53 -0700)]
ci/freedreno: Also mark waitformsc as flaky.
glx@glx_arb_sync_control@glxgetmscrateoml is the only non-flaky (so far)
arb_sync_control test on a630.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emma Anholt [Fri, 21 May 2021 03:12:02 +0000 (20:12 -0700)]
ci/freedreno: Mark a630 glx-visuals-depth/stencil as piglit flakes.
These seem to be present from the beginning of piglit runs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emma Anholt [Thu, 20 May 2021 22:56:49 +0000 (15:56 -0700)]
ci/freedreno: Consolidate ssbo.fragment_binding_array flake annotation.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emma Anholt [Thu, 20 May 2021 22:55:13 +0000 (15:55 -0700)]
ci/freedreno: Drop VK flake annotations not seen in the last ~year.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emma Anholt [Thu, 20 May 2021 22:53:50 +0000 (15:53 -0700)]
ci/freedreno: Add a link explaining get_display_plane_capabilities
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emma Anholt [Thu, 20 May 2021 22:52:55 +0000 (15:52 -0700)]
ci/freedreno: Drop a630 flake annotation from the go-fast changes.
The async fix seems to have fixed it, haven't seen this one since May 3rd.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emma Anholt [Thu, 20 May 2021 22:52:01 +0000 (15:52 -0700)]
ci/freedreno: Clear stale validation failure flake annotation.
Haven't seen it in my current set of IRC logs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emma Anholt [Thu, 20 May 2021 22:50:45 +0000 (15:50 -0700)]
ci/freedreno: Clear compswap flake annotation.
These flakes disappeared around 2020-08 and the only sign since then has
been some flakes on versions of the ir3 RA rewrite.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10933>
Emil Velikov [Mon, 10 May 2021 16:55:59 +0000 (17:55 +0100)]
gbm: list to stderr all the missing extension
This way people have a fighting chance of figuring out what's wrong.
v2: add gbm: prefix to the warning (Simon Ser)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10732>
Alejandro Piñeiro [Sun, 23 May 2021 21:08:07 +0000 (23:08 +0200)]
v3dv: don't use typedef enum with broadcom stages
This is the only place on the broadcom stack where we use "typedef
enum", so for consistency let's avoid it.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10947>
Alyssa Rosenzweig [Fri, 21 May 2021 15:25:55 +0000 (11:25 -0400)]
ci: Condition s390x on specific drivers
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10926>
Alyssa Rosenzweig [Fri, 21 May 2021 15:24:17 +0000 (11:24 -0400)]
ci: Condition ppc64-el on specific drivers
Changes to Panfrost or Freedreno should not trigger ppc64 rebuilds.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10926>
Alyssa Rosenzweig [Fri, 21 May 2021 15:01:02 +0000 (11:01 -0400)]
panfrost/ci: Split rules by ISA
Panfrost has two compilers, one for Midgard GPUs and one for Bifrost
GPUs. The respective compilers are src/panfrost/midgard and
src/panfrost/bifrost. Changes internal to just one compiler (or
disassembler) cannot affect the other hardware, so there's no need to
run extra jobs in these cases.
Also split out common vs Gallium panfrost so we can do the right thing
for panvk builds in the imminent future.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10924>
Icecream95 [Sat, 22 May 2021 19:10:19 +0000 (07:10 +1200)]
panfrost: Fix polygon list size computations
As noted in
f5c293425fa ("panfrost: Correct polygon size computations"),
"We do have to be careful to add the header size to total comptued BO
size."
Fixes:
ff3eada7eb4 ("panfrost: Use the generic preload and FB helpers in the gallium driver")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4660
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4737
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10943>
Mike Blumenkrantz [Fri, 21 May 2021 09:18:52 +0000 (05:18 -0400)]
radeonsi: explicitly return support for all index buffer formats
this should not change current behavior
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10914>
Tomeu Vizoso [Mon, 24 May 2021 08:26:41 +0000 (10:26 +0200)]
ci/lava: Add caching proxies for trace downloads
To avoid having to download the same traces again and again in each job,
use the caching proxy configured in the Collabora lab.
We can currently hardcode it like this because we don't test the same
driver in more than one lab, but when that changes we will need a more
flexible approach.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10949>
Erik Faye-Lund [Fri, 21 May 2021 11:48:53 +0000 (13:48 +0200)]
docs: update link to #lima
Similar to the other channels, #lima is also moving to OFTC, so let's
update the links as appropriate.
While we're at it, fix the URI scheme to use a slash as a host/channel
separator, and drop the hash for maximum compatibility.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10917>
Erik Faye-Lund [Fri, 21 May 2021 11:06:43 +0000 (13:06 +0200)]
docs: update location of #panfrost
Panfrost has already moved their IRC-channel to OFTC, so let's update
the docs as well.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10917>
Erik Faye-Lund [Fri, 21 May 2021 10:49:20 +0000 (12:49 +0200)]
docs: update link to #zink
We have decided to follow what's happening with #dri-devel for #zink as
well, so let's update our link there as well.
While we're at it, let's switch the link to an anonymous link, because
we're not referring to it anywhere, so it doesn't need to be named.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10917>
Erik Faye-Lund [Fri, 21 May 2021 10:38:19 +0000 (12:38 +0200)]
docs: promote #dri-devel on oftc over freenode
Due to the recent changes at Freenode and the recommendation from the
X.Org board of moving to OFTC[1], many mesa-developers have moved over
to the #dri-devel channel on OFTC by now.
So let's promote that channel rather than the Freenode channel.
While we're at it, let's correct[2] the URI to use a slash to separate
between the host and channel. And omit the # from the channel name for
maximum compatibility.
[1]: https://lists.freedesktop.org/archives/mesa-dev/2021-May/225271.html
[2]: https://en.wikipedia.org/wiki/Internet_Relay_Chat#URI_scheme
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10917>
Samuel Pitoiset [Thu, 20 May 2021 20:54:51 +0000 (22:54 +0200)]
radv: remove small overhead of radv_pipeline_has_ngg()
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4784
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10908>
Samuel Pitoiset [Thu, 20 May 2021 21:03:33 +0000 (23:03 +0200)]
radv: simplify radv_pipeline_has_gs_copy_shader()
The GS copy shader should only be built if GS and without NGG.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10908>
Samuel Pitoiset [Thu, 29 Apr 2021 09:51:14 +0000 (11:51 +0200)]
radv: fix fast clearing DCC if one level can't be compressed on GFX10+
Fallback to a slow clear, this could be improved by splitting the
clear into two parts (one fast and one slow) but that's complicated.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10516>
Boris Brezillon [Fri, 21 May 2021 09:48:03 +0000 (11:48 +0200)]
ci: Update to a new kernel fixing a bug in the panfrost driver
Should fix #4818.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10915>
Tomeu Vizoso [Tue, 18 May 2021 06:02:51 +0000 (08:02 +0200)]
radv/ci: Test on Stoney on CI
Run part of the VK CTS in 3 devices with Stoney Ridge graphics.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10853>
Emma Anholt [Fri, 21 May 2021 17:07:07 +0000 (10:07 -0700)]
ci/iris: Switch GLK back to manual testing.
The glk boards are particularly slow, and we've had the lab get backed up,
causing many spurious failures in the last day due to #4819. Just disable
this board by default for now until that can get sorted out.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10932>
Yogesh Mohanmarimuthu [Wed, 21 Apr 2021 15:18:23 +0000 (20:48 +0530)]
radv: set RADEON_FLAG_GTT_WC flag for prime memory
With display on iGPU and render on dGPU, VRR is not working. To fix
this set RADEON_FLAG_GTT_WC flag when allocating memory for prime. This
allows kernel function amdgpu_display_user_framebuffer_create() to
allocate GTT memory with USWC flag making the buffer scanout for iGPU.
This helps the ddx amdgpu_present_check_flip() function to return
true. Now, xserver will flip the framebuffer instead of blit. Due
to this VRR feature will work where iGPU supports USWC flag.
v2: modify commit message with use case (Michel Dänzer)
v3: allow GTT_WC flag only if VRAM_DOMAIN and NO_CPU_ACCESS (Bas Nieuwenhuizen)
v4: add check for wsi_info is NULL
v5: use wsi_info pointer to check for prime alloc (Bas Nieuwenhuizen)
v6: set _GTT_WC flag when wsi_info pointer is not NULL (Bas Nieuwenhuizen)
Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10657>
Lionel Landwerlin [Thu, 20 May 2021 20:30:19 +0000 (23:30 +0300)]
intel/fs: make sure shuffle is lowered to supported types
On XeHP there are restrictions on types of source and destinations
with float types. As shuffle is implemented using MOV we need to make
sure we lower it to supported types.
This fixes tests like :
dEQP-VK.subgroups.arithmetic.framebuffer.subgroupexclusivemax_vec4_vertex
dEQP-VK.subgroups.arithmetic.framebuffer.subgroupexclusivemul_f16vec3_vertex
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10902>
Mike Blumenkrantz [Mon, 17 May 2021 18:17:49 +0000 (14:17 -0400)]
aux/trace: dump 'wait' param for get_query_result
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Mike Blumenkrantz [Mon, 17 May 2021 18:02:29 +0000 (14:02 -0400)]
aux/trace: add a pipe_context::clear_buffer hook
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Mike Blumenkrantz [Mon, 17 May 2021 18:01:49 +0000 (14:01 -0400)]
aux/trace: fix query handling with tc
trace needs to follow the tc rules for queries a little in order to avoid
crashing and provide drivers with the same behavior they expect
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Mike Blumenkrantz [Mon, 10 May 2021 20:13:01 +0000 (16:13 -0400)]
aux/trace: fix set_inlinable_constants hook
need to dump the arg, not just the array
Fixes:
8926c4a313e ("aux/trace: add a set_inlinable_constants hook")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Mike Blumenkrantz [Fri, 7 May 2021 20:47:56 +0000 (16:47 -0400)]
aux/trace: hook tc methods
these need to have the context/screen unwrapped in order to not crash
while tracing
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Mike Blumenkrantz [Fri, 7 May 2021 19:04:09 +0000 (15:04 -0400)]
aux/trace: stop dumping transfer data for threaded contexts
this is only useful for unit testing (and is it really useful even then?),
and does nothing but explode trace dumps and demolish performance otherwise
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Mike Blumenkrantz [Fri, 7 May 2021 19:03:46 +0000 (15:03 -0400)]
aux/trace: trace transfer ops
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Mike Blumenkrantz [Thu, 6 May 2021 21:06:09 +0000 (17:06 -0400)]
aux/trace: more effectively unwrap pipe_context params from screen functions
when using tc, these are the threaded context, not the trace context
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Mike Blumenkrantz [Thu, 6 May 2021 20:04:00 +0000 (16:04 -0400)]
aux/trace: add pipe_context::set_debug_callback hook
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
Andres Gomez [Wed, 5 May 2021 09:03:22 +0000 (12:03 +0300)]
ci: update some radv trace checksums
After
a7c0cf500b3 ("radv: Enable DCC for image stores on GFX10.")
some checksums for the radv driver remained to be updated.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10856>
Andres Gomez [Wed, 5 May 2021 07:18:10 +0000 (10:18 +0300)]
ci: update some radv trace checksums
After
524848707b4 ("radv: don't set sx_blend_opt_epsilon for V_028C70_COLOR_10_11_11")
some checksums for the radv driver remained to be updated.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10856>
Andres Gomez [Wed, 5 May 2021 07:10:44 +0000 (10:10 +0300)]
ci: make sure we only read the first line from install/VERSION
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10856>