platform/kernel/u-boot.git
7 years agoboard_f: powerpc: Use timer_init() instead of init_timebase()
Simon Glass [Tue, 28 Mar 2017 16:27:24 +0000 (10:27 -0600)]
board_f: powerpc: Use timer_init() instead of init_timebase()

There is no good reason to use a different name on PowerPC. Change it to
timer_init() like the others.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoboard_f: powerpc: Unified get_clocks() portion of init sequence
Simon Glass [Tue, 28 Mar 2017 16:27:23 +0000 (10:27 -0600)]
board_f: powerpc: Unified get_clocks() portion of init sequence

Now that both branches of the #if do the same thing, we can unify them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoboard_f: Remove adjust_sdram_tbs_8xx() from the init sequence
Simon Glass [Tue, 28 Mar 2017 16:27:22 +0000 (10:27 -0600)]
board_f: Remove adjust_sdram_tbs_8xx() from the init sequence

We can just call this from the only place that needs it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoboard_f: Remove sdram_adjust_866() from the init sequence
Simon Glass [Tue, 28 Mar 2017 16:27:21 +0000 (10:27 -0600)]
board_f: Remove sdram_adjust_866() from the init sequence

We can just call this from the only function that needs it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoboard_f: powerpc: Rename get_clocks_866() to get_clocks()
Simon Glass [Tue, 28 Mar 2017 16:27:20 +0000 (10:27 -0600)]
board_f: powerpc: Rename get_clocks_866() to get_clocks()

We really don't need to have a name like this in the generic init
sequence. Use the generic get_clocks() name so that we can merge these
two at some point.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoboard_f: powerpc: Join the two CONFIG_8xx_CPUCLK_DEFAULT sections
Simon Glass [Tue, 28 Mar 2017 16:27:19 +0000 (10:27 -0600)]
board_f: powerpc: Join the two CONFIG_8xx_CPUCLK_DEFAULT sections

We have two chunks of code which depend on this CONFIG options. There is
likely no need to keep them apart, so join them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoboard_f: x86: Rename x86_fsp_init() to arch_fsp_init()
Simon Glass [Tue, 28 Mar 2017 16:27:18 +0000 (10:27 -0600)]
board_f: x86: Rename x86_fsp_init() to arch_fsp_init()

While x86 is the only user and this could in principle be moved to
arch_cpu_init() there is some justification for this being a separate
call. It provides a way to handle init which is not CPU-specific, but
must happen before the CPU can be set up.

Rename the function to be more generic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoboard_f: initcall: Add a header guard
Simon Glass [Tue, 28 Mar 2017 16:27:17 +0000 (10:27 -0600)]
board_f: initcall: Add a header guard

This file is missing the usual header guard. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoboard_f: sandbox: Move setup_ram_buf() to private code
Simon Glass [Tue, 28 Mar 2017 16:27:16 +0000 (10:27 -0600)]
board_f: sandbox: Move setup_ram_buf() to private code

There is no need to have this call in the generic init sequence and no
other architecture has needed it in the time it has been there. Move it
into sandbox's private code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoOpenRISC: Remove
Tom Rini [Tue, 14 Mar 2017 15:08:12 +0000 (11:08 -0400)]
OpenRISC: Remove

The OpenRISC architecture is currently unmaintained, remove.

Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSPARC: Remove
Tom Rini [Tue, 14 Mar 2017 15:08:11 +0000 (11:08 -0400)]
SPARC: Remove

The SPARC architecture is currently unmaintained, remove.

Cc: Francois Retief <fgretief@spaceteq.co.za>
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoBlackfin: Remove
Tom Rini [Tue, 14 Mar 2017 15:08:10 +0000 (11:08 -0400)]
Blackfin: Remove

The architecture is currently unmaintained, remove.

Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agomx6sxsabreauto: Remove legacy CONFIG_PCA953X
Tom Rini [Wed, 5 Apr 2017 14:42:16 +0000 (10:42 -0400)]
mx6sxsabreauto: Remove legacy CONFIG_PCA953X

When this board was switched to using more DM drivers we didn't disable
the legacy PCA953X driver.  This in turn learn to a build time warning
about implicit functions as i2c.h would not say anything about
'i2c_read' nor 'i2c_write'.  But this was not a fatal error as none of
the legacy driver would be linked in either.

Fixes: e389033f72b5 ("imx: mx6sxsabreauto: enable more dm drivers")
Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Wed, 5 Apr 2017 12:28:33 +0000 (08:28 -0400)]
Merge git://git.denx.de/u-boot-dm

7 years agodm: avoid dropping pin control DT properties in case of SPL_PINCTRL
Vikas Manocha [Fri, 24 Mar 2017 21:47:44 +0000 (14:47 -0700)]
dm: avoid dropping pin control DT properties in case of SPL_PINCTRL

This patch replaces SPL_PINCTRL_FULL with SPL_PINCNTRL. It is to avoid removal
of pin control properties in case of SPL_PINCTRL. No impact in case of
SPL_PINCTRL_FULL as it depends on SPL_PINCTRL.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: test: Add test for device removal
Stefan Roese [Mon, 27 Mar 2017 09:02:43 +0000 (11:02 +0200)]
dm: test: Add test for device removal

Add a test for the correct device removal. Currently two different ways
for device removal are supported:

- Normal device removal via the device_remove() API
- Removal via selective device driver flags (DM_FLAG_ACTIVE_DMA)

This new test "remove_active_dma" adds tests cases for those both ways
of removal. This is done by adding a new test driver, which has this
flag set.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
7 years agoarm: bootm: Add dm_remove_devices_flags() call to announce_and_cleanup()
Stefan Roese [Mon, 20 Mar 2017 11:51:50 +0000 (12:51 +0100)]
arm: bootm: Add dm_remove_devices_flags() call to announce_and_cleanup()

This patch adds a call to dm_remove_devices_flags() to
announce_and_cleanup() so that drivers that have one of the removal flags
set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may do some
last-stage cleanup before the OS is started.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: core: Add dm_remove_devices_flags() and hook it into device_remove()
Stefan Roese [Mon, 27 Mar 2017 08:58:53 +0000 (10:58 +0200)]
dm: core: Add dm_remove_devices_flags() and hook it into device_remove()

The new function dm_remove_devices_flags() is intented for driver specific
last-stage cleanup operations before the OS is started. This patch adds
this functionality and hooks it into the common device_remove()
function.

Drivers wanting to use this feature for some last-stage removal calls,
need to add one of the DM_REMOVE_xx flags to their driver .flags.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: core: Add flags parameter to device_remove()
Stefan Roese [Mon, 20 Mar 2017 11:51:48 +0000 (12:51 +0100)]
dm: core: Add flags parameter to device_remove()

This patch adds the flags parameter to device_remove() and changes all
calls to this function to provide the default value of DM_REMOVE_NORMAL
for "normal" device removal.

This is in preparation for the driver specific pre-OS (e.g. DMA
cancelling) remove support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: Add support for MiQi rk3288 board
Jernej Skrabec [Wed, 29 Mar 2017 23:23:14 +0000 (01:23 +0200)]
rockchip: Add support for MiQi rk3288 board

MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: cosmetic: Sort RK3288 boards
Jernej Skrabec [Wed, 29 Mar 2017 23:23:13 +0000 (01:23 +0200)]
rockchip: cosmetic: Sort RK3288 boards

Sort rk3288 boards in alphabetical order.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodts: rk3399: move rockchip, vbus-gpio properties into board-specific files
Philipp Tomsich [Wed, 29 Mar 2017 19:19:25 +0000 (21:19 +0200)]
dts: rk3399: move rockchip, vbus-gpio properties into board-specific files

The (shared) rk3399.dtsi had defined the 'rockchip,vbus-gpio'
properties for each USB 3.0 controller.

As the GPIO usage will vary (e.g. one of those GPIOs shuts down one of
the regulators on the RK3399-Q7) between boards, we move this from the
shared dtsi into the device tree file for the EVB board which these
GPIO definitions match.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodefconfig: puma-rk3399: add defconfig for the RK3399-Q7 (Puma)
Philipp Tomsich [Tue, 28 Mar 2017 16:48:52 +0000 (18:48 +0200)]
defconfig: puma-rk3399: add defconfig for the RK3399-Q7 (Puma)

This commit adds the baseline defconfig for the RK3399-Q7 (Puma) SoM
(under the name 'puma-rk3399_defconfig') featuring the Rockchip RK3399
in a Qseven compatible module.

This subsumes the following changes:
 * defconfig: rk3399: migrate CONFIG_SPL_LIBCOMMON_SUPPORT/CONFIG_SPL_LIBGENERIC_SUPPORT
 * defconfig: rk3399-puma: add CONFIG_MMC_DW_ROCKCHIP
 * defconfig: rk3399-puma: disable CONFIG_SPL_OF_PLATDATA
 * defconfig: rk3399-puma: don't USE_TINY_PRINTF
 * defconfig: rk3399-puma: set up CONFIG_SYS_BOARD for the RK3399-Q7
 * defconfig: rk3399-puma: enable the multi-image loading via CONFIG_SPL_FIT
 * defconfig: rk3399-puma: SPL should be able to boot from MMC/SD card
 * defconfig: rk3399-puma: enable GMAC support
 * defconfig: rk3399-puma: enable support for SPI and Winbond SPI flash
 * defconfig: rk3399-puma: enable SPI as a boot-source in SPL
 * defconfig: rk3399-puma: disallow non-FIT images from being loaded
 * defconfig: rk3399-puma: rename to puma-rk3399
 * rockchip: config: rk3399: update defconfigs and rk3399_common

For the RK3399-Q7, we want a default boot-order of SPI -> MMC -> uSD.
This both follows how the BootROM probes devices and is a sane default
for customers in device-personalisation (e.g. it allows for quick and
easy factory programming of unpersonalised devices using an SD card)
and field usage (with customer devices expected to have their firmware
either in SPI or MMC).

However, when probing multiple interfaces (according to the result
from the board_boot_order function), we need to ensure that only valid
FIT images are considered and disable the fallback to assuming that a
raw (binary-only) U-Boot image is loaded (to avoid hangs/crashes from
jumping to random content loaded from devices that are probed, but
don't contain valid image content).

By disabling the SPL_RAW_IMAGE_SUPPORT and SPL_LEGACY_IMAGE_SUPPORT
options, we ensure that raw images (indistinguishable from random
data) are not considered for booting.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop CONFIG_DEBUG_UART_BOARD_INIT:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM
Philipp Tomsich [Tue, 28 Mar 2017 16:48:51 +0000 (18:48 +0200)]
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM

The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399
in a Qseven-compatible form-factor.

These changes add a device-tree describing the board and its
interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card).

This includes the following changes from the original development:

 * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile
 * dts: rk3399-puma: add gmac for the RK3399-Q7

This change enables the Gigabit Ethernet support on the RK3399-Q7.

 * dts: rk3399-puma: use serial0 for stdout
 * dts: rk3399-puma: prepare the sdmmc node for SPL booting
 * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash

The RK3399-Q7 (Puma) unsually (this is a build-time option for
customised boards) has an on-module SPI-flash connected to SPI1.
As of today, this is a Winbond W25Q32DW (32MBit) device.

The SPI5 controller is routed to the Q7 edge connector and provides
general-purpose SPI connectivity for customer base-boards.

With some minor improvements on integration into our outbound tree
 - explicitly modelled the SPI flash as 'spiflash' under spi0
   [dts: rk3399-puma: explicitly model spi-flash under spi1]
 - renamed the aliases to spi0 and spi1 to allow easier use of
   commands and legacy (SPL) infrastructure... i.e. the controllers
   will be 0 and 1 for 'sf probe', 'sspi', etc.
   [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands]

 * dts: rk3399-puma: include SPI in the spl-boot-order property

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spi: rk3399: move CONFIG_SPI and CONFIG_SPI_FLASH to defconfig
Jakob Unterwurzacher [Wed, 29 Mar 2017 11:31:30 +0000 (13:31 +0200)]
rockchip: spi: rk3399: move CONFIG_SPI and CONFIG_SPI_FLASH to defconfig

On the RK3399-Q7 we need to enable a number of configuration options
(e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI
and CONFIG_SPI_FLASH active.

To allow for these being defined in Kconfig (e.g. via defconfig) and
to avoid a warning on having the macro defined multiple times, we
remove them from the common header file.

Note that the rk3399-evb does not currently have the rk_spi.c driver
active (i.e. CONFIG_ROCKCHIP_SPI), so there's no change to the
evb-rk3399_defconfig as part of this change.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agoarm64: rockchip: rk3399-puma: add DDR3-1333 timings
Philipp Tomsich [Tue, 28 Mar 2017 16:48:50 +0000 (18:48 +0200)]
arm64: rockchip: rk3399-puma: add DDR3-1333 timings

For the initial validation of the RK3399-Q7 (Puma), the DDR3 has been
clocked at 666MHz (i.e. DDR3-1333) using the same (safe) settings as
used in Rockchip's MiniLoader.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3399: spl: make SPL boot-order configurable via /chosen
Philipp Tomsich [Tue, 28 Mar 2017 09:03:00 +0000 (11:03 +0200)]
rockchip: rk3399: spl: make SPL boot-order configurable via /chosen

The RK3399 does not have any boot selection pins and the BootROM probes
the boot interfaces using the following boot-order:
    1. SPI
    2. eMMC (sdhci in DTS)
    3. SD card (sdmmc in DTS)
    4. USB loader
For ease of deployment, the SPL stage should mirror the boot order of
the ROM and use the same probing order (assuming that valid images can
be detected by SPL) unless instructed otherwise.  The boot-order can
then be configured via the 'u-boot,spl-boot-order' property in the
chosen-node of the DTS.

While this approach is easily extensible to other boards, it is only
implemented for the RK3399 for now, as the large SRAM on the RK3399
makes this easy to fit the needed infrastructure into SPL and our
production setup already runs with DM, OF_CONTROL and BLK in SPL.

The new boot-order property is expected to be used in conjunction with
FIT images (and all legacy image formats disabled via Kconfig).

A boot-sequence with probing and fallthroughs from SPI via eMMC to SD
card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: Add Radxa Rock board
Heiko Stübner [Sun, 26 Mar 2017 19:09:55 +0000 (21:09 +0200)]
rockchip: rk3188: Add Radxa Rock board

The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agostring: Provide a slimmed-down memset()
Simon Glass [Sun, 2 Apr 2017 15:50:28 +0000 (09:50 -0600)]
string: Provide a slimmed-down memset()

Most of the time the optimised memset() is what we want. For extreme
situations such as TPL it may be too large. For example on the 'rock'
board, using a simple loop saves a useful 48 bytes. With gcc 4.9 and
the rodata bug, this patch is enough to reduce the TPL image below the
limit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
7 years agoMakefile: Correct dependency race condition with TPL
Simon Glass [Sun, 26 Mar 2017 23:38:15 +0000 (17:38 -0600)]
Makefile: Correct dependency race condition with TPL

At present we sometimes see the following build error when building on a
machine with multiple cores.

+make[2]: *** No rule to make target 'dts/dt.dtb', needed by 'tpl/u-boot-tpl.dtb'.  Stop.

Add a dependency to correct this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
7 years agorockchip: dts: firefly: add usb host power supply node
Eddie Cai [Mon, 27 Mar 2017 07:17:27 +0000 (15:17 +0800)]
rockchip: dts: firefly: add usb host power supply node

firefly have a usb host. add dts node to provide power supply

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: follow THUMB_BUILD Kconfig migration
Heiko Stübner [Sun, 26 Mar 2017 19:09:54 +0000 (21:09 +0200)]
rockchip: rk3188: follow THUMB_BUILD Kconfig migration

Commit 3a649407a49b ("arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce
SPL_SYS_THUMB_BUILD") moved the THUMB_BUILD symbols from the header to
Kconfig symbols. With it still defined in the rk3188 header we end up
with a duplicate symbol and compile errors, so fix that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3399: 24MHz is not a power of 2
Philipp Tomsich [Fri, 24 Mar 2017 18:35:37 +0000 (19:35 +0100)]
rockchip: clk: rk3399: 24MHz is not a power of 2

The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.

This commits fixes this.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodts: rk3399: add gmac for the rk3399
Philipp Tomsich [Fri, 24 Mar 2017 18:24:27 +0000 (19:24 +0100)]
dts: rk3399: add gmac for the rk3399

This change adds the gmac node (i.e. the GMAC Ethernet controller) as
defined in the Linux DTS.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agonet: gmac_rockchip: Add support for the RK3399 GMAC
Philipp Tomsich [Fri, 24 Mar 2017 18:24:26 +0000 (19:24 +0100)]
net: gmac_rockchip: Add support for the RK3399 GMAC

The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it
is a Designware GMAC core and requires similar configuration as the
RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit).
The key difference is that the register offsets (within the GRF block)
and bit-offsets (within those registers) used to hold the configuration
differ between the various RK32/33 CPUs.

This change refactors the gmac_rockchip.c driver to use a function
table (selected via driver_data) to factor out these differences. Each
function's implementation then matches the underlying processor.

Some collateral changes are needed in the definitions describing the
bits and offsets in the GRF are needed to prefix each set of symbolic
constants with the SoC name to avoid name clashes... and in doing so,
the shifts for masks and constants have been moved into the header
files for readability (and to make it easier to stay below 80 chars).

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed commit message typo s/factor our/factor out/:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3399: add clocking support for Ethernet
Philipp Tomsich [Fri, 24 Mar 2017 18:24:25 +0000 (19:24 +0100)]
rockchip: clk: rk3399: add clocking support for Ethernet

The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock
is ungated through a call to clk_set_rate(...). Even though nothing
needs to be done on the RK3399 (the clock gates are open and the clock
is external), we need to implement enough support to at least return
success to enable driver probing.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3399: fix warnings for unused variables in SPL/non-SPL
Philipp Tomsich [Fri, 24 Mar 2017 18:24:24 +0000 (19:24 +0100)]
rockchip: clk: rk3399: fix warnings for unused variables in SPL/non-SPL

Due to differences in the code paths for SPL and non-SPL, some static
constant structures remain unused in each build variant. This raises
warnings with recent GCC versions (we currently use GCC-6.3).

The warnings addressed in this commit (by matching #if conditions for
the variable definition with their uses) are:

* for the SPL build:
    drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
                                 ^~~~~~~~~~~~~
    drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
                                 ^~~~~~~~~~~~~
* for the non-SPL build:
    drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
                                 ^~~~~~~~~~~~~

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3399: add GMAC (RGMII only) support
Philipp Tomsich [Fri, 24 Mar 2017 18:24:23 +0000 (19:24 +0100)]
rockchip: pinctrl: rk3399: add GMAC (RGMII only) support

To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration.  This commit
adds the pinctrl support for GMAC in RGMII signalling mode:
 * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
 * adds the required defines (in the GRF support) for configuring the
   GPIOC pins for RGMII
 * configures the RGMII pins (in GPIOC) when requested via pinctrl

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: arm64: rk3399: remove unconditional debug message
Philipp Tomsich [Fri, 24 Mar 2017 18:10:52 +0000 (19:10 +0100)]
rockchip: arm64: rk3399: remove unconditional debug message

An earlier upstream change contained an unconditional debug message
which would show up as a message similar to the following in the
U-Boot startup (after the ATF and before the U-Boot banner):
      time 159f019, 0

This commit removes this message (instead of making if conditional on
being a debug-build), as it doesn't pertain to any initialisation done
in this file.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spl: RK3399: add COUNTER_FREQUENCY define to rk3399_common.h
Philipp Tomsich [Thu, 23 Mar 2017 22:27:45 +0000 (23:27 +0100)]
rockchip: spl: RK3399: add COUNTER_FREQUENCY define to rk3399_common.h

The BootROM of the RK3399 SoC does not initialise the cntfrq_el0 (which
holds the value 0 (zero) on entry into the SPL. This causes the timebase
for U-Boot not to advance (and will cause a hang where a timeout would
be expected... e.g. if something goes wrong during MMC/SD card startup).

This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0 (if necessary).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: Split out HDMI controller code
Jernej Skrabec [Mon, 20 Mar 2017 22:01:22 +0000 (23:01 +0100)]
rockchip: video: Split out HDMI controller code

Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.

DW HDMI has 8 bit registers but they can be represented as 32 bit
registers as well. Add support to select access mode.

EDID reading code use reading by blocks which is not supported by other
SoCs in general. Make it more general using byte by byte approach, which
is also used in Linux driver.

Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
Support custom phys by making controller code independent from phy code.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Tested-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: i2c: Add compatibles for Rockchip Cortex-A9 socs
Heiko Stübner [Mon, 20 Mar 2017 11:40:35 +0000 (12:40 +0100)]
rockchip: i2c: Add compatibles for Rockchip Cortex-A9 socs

The Cortex-A9 socs rk3066 and rk3188 share the IP but have their own
compatible values, so add them to make the i2c on these platforms accessible.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: Setup the armclk in spl
Heiko Stübner [Mon, 20 Mar 2017 11:40:33 +0000 (12:40 +0100)]
rockchip: rk3188: Setup the armclk in spl

The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot
startup taking a lot of time (U-Boot itself, but also the rc4 decoding done
in the bootrom).

With default pmic settings we can always reach a safe frequency of 600MHz
which is also the frequency the proprietary loader left the armclk at,
without needing access to the systems pmic.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3188: Allow configuration of the armclk
Heiko Stübner [Mon, 20 Mar 2017 11:40:32 +0000 (12:40 +0100)]
rockchip: clk: rk3188: Allow configuration of the armclk

The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.

For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: Cleanup some SPL/TPL rename leftovers
Heiko Stübner [Mon, 20 Mar 2017 11:40:31 +0000 (12:40 +0100)]
rockchip: rk3188: Cleanup some SPL/TPL rename leftovers

In the beginning, we did SPL -> TPL -> U-Boot, but after clarification
of the real ordering swapped SPL and TPL.
It seems some renames were forgotten and may confuse future readers, so
also swap these to reflect the actual ordering.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: Decode the actual amount of ram
Heiko Stübner [Mon, 20 Mar 2017 11:40:30 +0000 (12:40 +0100)]
rockchip: rk3188: Decode the actual amount of ram

There was still a static ram value set in the rk3188-board from the
time where we didn't have actual sdram init code.
Now the sdram init leaves the ram information in SYS_REG2 and we can
decode it similarly to the rk3288.

Right now we have two duplicates of that code, which is still ok and
doesn't really count as common code yet, but if we get a third copy
at some point from a newer soc, we should think about moving that to
a more general position.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: sdram: Set correct sdram base
Heiko Stübner [Mon, 20 Mar 2017 11:40:29 +0000 (12:40 +0100)]
rockchip: rk3188: sdram: Set correct sdram base

Right now we're setting the wrong value of 0 as base in the ram_info struct,
which is obviously wrong for the rk3188. So instead set the correct value
we already have in CONFIG_SYS_SDRAM_BASE.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: add README.rockchip paragraph describing sd boot
Heiko Stübner [Thu, 23 Mar 2017 23:41:34 +0000 (00:41 +0100)]
rockchip: rk3188: add README.rockchip paragraph describing sd boot

Building sd images for rk3188 requires more steps due to the needed split
into TPL and SPL as loaders. Describe how to build an image for it in a
separate paragraph in the READER.rockchip file.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3188: enable TPL_LIBGENERIC for generic memset
Heiko Stübner [Thu, 23 Mar 2017 23:41:32 +0000 (00:41 +0100)]
rockchip: rk3188: enable TPL_LIBGENERIC for generic memset

Commit c67c8c604b6c ("board_init.c: Always use memset()") dropped the naive
memset alternative from board_init_f_init_reserve.
So activate CONFIG_TPL_LIBGENERIC for that common memset implementation.
We cannot use the ARCH-specific memset, as that would incur 200bytes of
additional TPL size, space we do not have.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agorockchip: spl: use spl_early_init() instead of spl_init()
Kever Yang [Mon, 20 Mar 2017 06:47:16 +0000 (14:47 +0800)]
rockchip: spl: use spl_early_init() instead of spl_init()

Rockchip spl driver needs using spl_early_init().

Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: use per-SoC option names for Kconfig
Philipp Tomsich [Fri, 17 Mar 2017 19:41:03 +0000 (20:41 +0100)]
rockchip: pinctrl: use per-SoC option names for Kconfig

The config options for pinctrl on the RK3188, RK3288, RK3328 and
RK3399 previously showed up in menuconfig with the generic string
descriptor "Rockchip pin control driver" requiring one to look through
the help/full description to identify which chip each menu entry was
for.

This change renames each option with the chip-name in the description
string to make it easy to identify the configuration options in
menuconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: update rkimage to support pre-padded payloads
Philipp Tomsich [Wed, 15 Mar 2017 11:08:45 +0000 (12:08 +0100)]
rockchip: mkimage: update rkimage to support pre-padded payloads

To simplify the creation of AArch64 SPL images for the RK3399, we
use the ENABLE_ARM_SOC_BOOT0_HOOK option and prepend 4 bytes of
padding at the start of the text section. This makes it easy for
mkimage to rewrite this word with the 'RK33' boot magic.

This change brings logic to calculate the header size and allocate
the header back in sync. For the RK3399 we now limit the header to
before the payload (i.e. the 'header0' and the padding up to the
actual image) and overwrite the first word (inserted by the
boot0-hook for this purpose) with the 'RK33' magic in-place.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
7 years agorockchip: spl: RK3399: use boot0 hook to create space for SPL magic
Philipp Tomsich [Wed, 15 Mar 2017 11:08:44 +0000 (12:08 +0100)]
rockchip: spl: RK3399: use boot0 hook to create space for SPL magic

The SPL binary needs to be prefixed with the boot magic ('RK33' for
the RK3399) on the Rockchip platform and starts execution of the
instruction word following immediately after this boot magic.

This poses a challenge for AArch64 (ARMv8) binaries, as the .text
section would need to start on the odd address, violating natural
alignment (and potentially triggering a fault for any code that
tries to access 64bit values embedded in the .text section).

A quick and easy fix is to have the .text section include the 'RK33'
magic and pad it with a boot0 hook to insert 4 bytes of padding at the
start of the section (with the intention of having mkimage overwrite
this padding with the appropriate boot magic). This avoids having to
modify the linker scripts or more complex logic in mkimage.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
7 years agorockchip: mkimage: pad the header to 8-bytes (using a 'nop') for RK3399
Philipp Tomsich [Wed, 15 Mar 2017 11:08:43 +0000 (12:08 +0100)]
rockchip: mkimage: pad the header to 8-bytes (using a 'nop') for RK3399

The RK3399 boot code (running as AArch64) poses a bit of a challenge
for SPL image generation:
 * The BootROM will start execution right after the 4-byte header (at
   the odd instruction word loaded into SRAM at 0xff8c2004, with the
   'RK33' boot magic residing at 0xff8c2000).
 * The default padding (during ELF generation) for AArch64 is 0x0,
   which is an illegal instruction and the .text section needs to be
   naturally aligned (someone might locate a 64bit constant relative
   to the section start and unaligned loads trigger a fault for all
   privileged modes of an ARMv8)... so we can't simply define the
   CONFIG_SPL_TEXT_BASE option to the odd address (0xff8c2004).
 * Finally, we don't want to change the values used for padding of
   the SPL .text section for all ARMv8 targets to the instruction
   word encoding 'nop', as this would affect all padding in this
   section and might hide errors that would otherwise quickly trigger
   an illegal insn exception.

To deal with this situation, we modify the rkimage generation to
 - understand the fact that the RK3399 needs to pad the header to an
   8 byte boundary using an AArch64 'nop'
 - the necessary logic to adjust the header_size (which controls the
   location where the payload is copied into the image) and to insert
   this padding (AArch64 insn words are always little-endian) into
   the image following the 4-byte header magic.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
7 years agorockchip: mkimage: simplify start/size calculation for rc4_encode
Philipp Tomsich [Wed, 15 Mar 2017 11:08:42 +0000 (12:08 +0100)]
rockchip: mkimage: simplify start/size calculation for rc4_encode

The RC4 encoding works on full blocks, but the calculation of the
starting offset and size are needlessly complicated by using a
reference value known to be offset into a block by the size of the
header and then correcting for the (hard-coded) size of the header
(i.e. 4 bytes).

We change this over to use the RK_SPL_HDR_START directly (which is
known to be on a block boundary).

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
7 years agorockchip: configs: correct mmc env dev for rk3288 based boards
Jacob Chen [Wed, 15 Mar 2017 09:28:43 +0000 (17:28 +0800)]
rockchip: configs: correct mmc env dev for rk3288 based boards

we are using mmc alias , so mmc index have been changed.
now mmc dev 0 is emmc and mmc dev 1 is sdmmc.

Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
7 years agoPrepare v2017.05-rc1 v2017.05-rc1
Tom Rini [Tue, 4 Apr 2017 21:53:24 +0000 (17:53 -0400)]
Prepare v2017.05-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoMerge git://git.denx.de/u-boot-tegra
Tom Rini [Tue, 4 Apr 2017 20:01:02 +0000 (16:01 -0400)]
Merge git://git.denx.de/u-boot-tegra

7 years agoMerge git://git.denx.de/u-boot-arc
Tom Rini [Tue, 4 Apr 2017 13:20:03 +0000 (09:20 -0400)]
Merge git://git.denx.de/u-boot-arc

In this patch-set we add support of new AXS103 firmware as well as
troubleshoot unexpected execution by multiple cores simultaneously.

7 years agoMerge git://git.denx.de/u-boot-mmc
Tom Rini [Tue, 4 Apr 2017 13:19:24 +0000 (09:19 -0400)]
Merge git://git.denx.de/u-boot-mmc

7 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Tue, 4 Apr 2017 13:18:57 +0000 (09:18 -0400)]
Merge git://git.denx.de/u-boot-dm

7 years agoMerge git://www.denx.de/git/u-boot-marvell
Tom Rini [Tue, 4 Apr 2017 13:17:56 +0000 (09:17 -0400)]
Merge git://www.denx.de/git/u-boot-marvell

This includes Marvell mvpp2 patches with the ethernet support for the
ARMv8 Armada 7k/8k platforms. The ethernet patches are all acked by Joe
and he is okay with me pushing them via the Marvell tree.

7 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 4 Apr 2017 13:17:08 +0000 (09:17 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-i2c
Tom Rini [Tue, 4 Apr 2017 13:16:25 +0000 (09:16 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c

7 years agoapalis-tk1: disable external clock loopback on SDMMC3
Marcel Ziswiler [Sat, 25 Mar 2017 00:18:23 +0000 (01:18 +0100)]
apalis-tk1: disable external clock loopback on SDMMC3

Actually make use of that shiny new CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agommc: tegra: allow disabling external clock loopback
Marcel Ziswiler [Sat, 25 Mar 2017 00:18:22 +0000 (01:18 +0100)]
mmc: tegra: allow disabling external clock loopback

Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0
register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agoarm: tegra: initial support for apalis tk1
Marcel Ziswiler [Sat, 1 Apr 2017 22:43:16 +0000 (15:43 -0700)]
arm: tegra: initial support for apalis tk1

This patch adds board support for the Toradex Apalis TK1 a computer on
module which can be used on different carrier boards.

The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L
RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor
chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec.
Furthermore, there is a Kinetis MK20DN512 companion micro controller for
analogue, CAN and resistive touch functionality.

For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.

The following functionality is working so far:
- eMMC boot, environment storage and Toradex factory config block
- Gigabit Ethernet
- MMC/SD cards (both MMC1 as well as SD1 slot)
- USB client/host (dual role OTG port as client e.g. for DFU/UMS or host,
  other two ports as host)

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agoarcv2: Halt non-master cores
Alexey Brodkin [Thu, 30 Mar 2017 14:50:45 +0000 (17:50 +0300)]
arcv2: Halt non-master cores

Even though we expect only master core to execute U-Boot code
let's make sure even if for some reason slave cores attempt to
execute U-Boot in parallel with master they get halted very early.

If platform wants it may kick-start slave cores before passing control
to say Linux kernel or any other application that want to see all cores
of SMP SoC up and running.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
7 years agoaxs103: Support slave core kick-start on axs103 v1.1 firmware
Alexey Brodkin [Fri, 31 Mar 2017 08:14:35 +0000 (11:14 +0300)]
axs103: Support slave core kick-start on axs103 v1.1 firmware

In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit
compared t previous implementation.

In particular:
 * We used to have a generic START bit for all cores selected by CORE_SEL
   mask. But now we don't touch CORE_SEL at all because we have a dedicated
   START bit for each core:
     bit 0: Core 0 (master)
     bit 1: Core 1 (slave)
 * Now there's no need to select "manual" mode of core start

Additional challenge for us is how to tell which axs103 firmware we're
dealing with. For now we'll rely on ARC core version which was bumped
from 2.1c to 3.0.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
7 years agoaxs103: Clean-up smp_kick_all_cpus()
Alexey Brodkin [Thu, 30 Mar 2017 16:18:30 +0000 (19:18 +0300)]
axs103: Clean-up smp_kick_all_cpus()

 * Rely on default pulse polarity value
 * Don't mess with "multicore" value as it doesn't affect execution

In essence we now do a bare minimal stuff:
 1) Select HS38x2_1 with CORE_SEL=1 bits
 2) Select "manual" core start (via CREG) with START_MODE=0
 3) Generate cpu_start pulse with START=1

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
7 years agommc: omap_hsmmc: add support for CONFIG_BLK
Jean-Jacques Hiblot [Wed, 22 Mar 2017 15:00:34 +0000 (16:00 +0100)]
mmc: omap_hsmmc: add support for CONFIG_BLK

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agommc: omap_hsmmc: move the mmc_config to platdata when DM_MMC is used
Jean-Jacques Hiblot [Wed, 22 Mar 2017 15:00:33 +0000 (16:00 +0100)]
mmc: omap_hsmmc: move the mmc_config to platdata when DM_MMC is used

This is a preparation work for the support of CONFIG_BLK.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agommc: omap_hsmmc: use mmc_get_blk_desc() to get the block device desc
Jean-Jacques Hiblot [Wed, 22 Mar 2017 15:00:32 +0000 (16:00 +0100)]
mmc: omap_hsmmc: use mmc_get_blk_desc() to get the block device desc

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agommc: omap_hsmmc: use an accessor to get the private data
Jean-Jacques Hiblot [Wed, 22 Mar 2017 15:00:31 +0000 (16:00 +0100)]
mmc: omap_hsmmc: use an accessor to get the private data

For consistency, use an accessor to access the private data. Also for the
same reason, rename all priv_data to priv.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoarm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfig
Stefan Roese [Fri, 10 Mar 2017 10:08:44 +0000 (11:08 +0100)]
arm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfig

The Marvell PHY support is needed espescially for the A7040-DB with the
SGMII port (port 2). As without the marvell PHY driver configuration
for SGMII, ethernet won't work.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoarm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G
Stefan Roese [Thu, 9 Mar 2017 13:35:28 +0000 (14:35 +0100)]
arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G

The default configuration for the COMPHY-0 port should be 1G, as its
used as 1G SGMII connection. This change is necessary to get the
MAC2 port (SGMII) working on this DB.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool
Stefan Roese [Mon, 13 Mar 2017 05:50:04 +0000 (06:50 +0100)]
net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool

As pointed out by Stefan Chulski, this variable is unused and should be
removed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Configure SMI PHY address needed for PHY polling
Stefan Roese [Fri, 10 Mar 2017 05:07:45 +0000 (06:07 +0100)]
net: mvpp2: Configure SMI PHY address needed for PHY polling

On PPv2.2 we enable PHY polling, so we also need to configure the PHY
address in the specific PHY address rgisters.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Enable PHY polling mode on PPv2.2
Stefan Roese [Thu, 9 Mar 2017 11:01:57 +0000 (12:01 +0100)]
net: mvpp2: Enable PHY polling mode on PPv2.2

Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID
Stefan Roese [Wed, 22 Mar 2017 14:11:00 +0000 (15:11 +0100)]
net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID

Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should
be handled identical to PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add GoP and NetC support for port 0 (SFI)
Stefan Roese [Wed, 22 Mar 2017 14:09:38 +0000 (15:09 +0100)]
net: mvpp2: Add GoP and NetC support for port 0 (SFI)

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)
Stefan Roese [Wed, 22 Mar 2017 14:07:30 +0000 (15:07 +0100)]
net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII
Stefan Roese [Wed, 22 Mar 2017 13:15:40 +0000 (14:15 +0100)]
net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII

Read the "phy-speed" DT property to differentiate between 1 and 2.5GB
SGMII operations. Please note that its unclear right now, if this
DT property will be accepted in mainline Linux. If not, we need to
revisit this code and change it to use the accepted property.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Restructure probe / init functions
Stefan Roese [Wed, 22 Mar 2017 13:11:16 +0000 (14:11 +0100)]
net: mvpp2: Restructure probe / init functions

This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: include/phy.h: Add new PHY interface modes
Stefan Roese [Thu, 23 Feb 2017 10:58:26 +0000 (11:58 +0100)]
net: include/phy.h: Add new PHY interface modes

This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will
be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add RX and TX FIFO configuration for PPv2.2
Stefan Roese [Wed, 1 Mar 2017 12:09:42 +0000 (13:09 +0100)]
net: mvpp2: Add RX and TX FIFO configuration for PPv2.2

This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
driver. The RX FIFO packet data size is changed to the recommended
FIFO sizes. The TX FIFO configuration is newly added.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Handle eth device naming in multi-CP case correctly
Stefan Roese [Fri, 24 Feb 2017 09:12:41 +0000 (10:12 +0100)]
net: mvpp2: Handle eth device naming in multi-CP case correctly

Currently, the naming of the ethernet ports is not handled correctly in
the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP
also instantiates an ethernet controller with the same device ID's.
This patch now takes this into account and adds the required base-id
so that the slave-CP ethernet devices will be named "mvpp2-3 ...".

This patch also updates my Copyright notice to include 2017 as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoarm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver
Stefan Roese [Mon, 20 Feb 2017 11:25:26 +0000 (12:25 +0100)]
arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver

Since we've now integrated the A7k/8k support in the mvpp2 ethernet
driver, lets enable the support for both Marvell developments boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoarm64: marvell: dts: add PPv2.2 description to Armada 7K/8K
Thomas Petazzoni [Mon, 20 Feb 2017 11:27:25 +0000 (12:27 +0100)]
arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K

This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Enable compilation for Armada 7K/8K platforms
Stefan Roese [Wed, 15 Feb 2017 10:42:59 +0000 (11:42 +0100)]
net: mvpp2: Enable compilation for Armada 7K/8K platforms

Since Armada 7K/8K is also equipped with a newer version of the MVPP2
ethernet controller, lets enable compilation of this driver for these
platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2.c: Clear all buffer / descriptor areas before usage
Stefan Roese [Thu, 16 Feb 2017 12:29:08 +0000 (13:29 +0100)]
net: mvpp2.c: Clear all buffer / descriptor areas before usage

This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Move probe function from MISC to ETH DM driver
Stefan Roese [Thu, 16 Feb 2017 14:26:06 +0000 (15:26 +0100)]
net: mvpp2: Move probe function from MISC to ETH DM driver

This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_register().

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add MDIO support for PPv2.2
Stefan Roese [Thu, 16 Feb 2017 07:31:32 +0000 (08:31 +0100)]
net: mvpp2: Add MDIO support for PPv2.2

In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver,
currently only supporting the 32bit platforms (Armada 37x). This patch
now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF
can be used as well on these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: finally add the PPv2.2 compatible string
Thomas Petazzoni [Mon, 20 Feb 2017 10:54:31 +0000 (11:54 +0100)]
net: mvpp2: finally add the PPv2.2 compatible string

Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: adapt rxq distribution to PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 08:03:16 +0000 (09:03 +0100)]
net: mvpp2: adapt rxq distribution to PPv2.2

In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.

In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from the range of 32 RXQs available for each port. So port 0 must
use RXQs in the range 0->31, port 1 in the range 32->63, etc.

This commit adapts the mvpp2 to this difference between PPv2.1 and
PPv2.2:

- The constant definition MVPP2_MAX_RXQ is replaced by a new field
  'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of
  RXQs per port. This field is initialized during ->probe() depending
  on the IP version.

- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total
  number of RXQs by multiplying the number of ports by the maximum of
  RXQs per port. This was anyway used in only one place.

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted
  to cope with the different allocation strategy between PPv2.1 and
  PPv2.2. Due to this change, the 'next_first_rxq' argument of this
  function is no longer needed and is removed.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: rework RXQ interrupt group initialization for PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 07:46:37 +0000 (08:46 +0100)]
net: mvpp2: rework RXQ interrupt group initialization for PPv2.2

This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: add AXI bridge initialization for PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 07:41:07 +0000 (08:41 +0100)]
net: mvpp2: add AXI bridge initialization for PPv2.2

The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: handle misc PPv2.1/PPv2.2 differences
Thomas Petazzoni [Mon, 20 Feb 2017 10:42:51 +0000 (11:42 +0100)]
net: mvpp2: handle misc PPv2.1/PPv2.2 differences

This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).

Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot
version of this patch does not remove this function but simply adds the
check for MVPP21 before the mvpp2_port_fc_adv_enable() call.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: handle register mapping and access for PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 07:03:37 +0000 (08:03 +0100)]
net: mvpp2: handle register mapping and access for PPv2.2

This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.

Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:

- On PPv2.1, we had a first area for the common registers, and then one
  area per port.

- On PPv2.2, we have a first area for the common registers, and a
  second area for all the per-ports registers.

In addition, on PPv2.2, the area for the common registers is split into
so-called "address spaces" of 64 KB each. They allow to access the same
registers, but from different CPUs. Hence the introduction of cpu_base[]
in 'struct mvpp2', and the modification of the mvpp2_write() and
mvpp2_read() register accessors. For PPv2.1, the compatibility is
preserved by using an "address space" size of 0.

Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the
code, macros and variables introduced in the Linux patch version for this.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2
Thomas Petazzoni [Mon, 20 Feb 2017 10:36:57 +0000 (11:36 +0100)]
net: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2

In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>