Chris Forbes [Sun, 7 Dec 2014 02:32:11 +0000 (15:32 +1300)]
i965: Add 64-bit dirty flag handling to brw_upload_pull_constants
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Forbes [Thu, 6 Nov 2014 11:04:01 +0000 (00:04 +1300)]
i965: Add defines for all new Gen7/8 URB opcodes
Tessellation needs to emit URB reads and atomics;
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ben Widawsky [Wed, 26 Aug 2015 17:52:58 +0000 (10:52 -0700)]
i965/gen8+: Skip depth stalls on state change
Docs suggest this is no longer required starting with Gen8.
Perf (no regressions in n=20)
OglMultithread 0.67%
OglTerrainPanInst 0.12%
trex 0.45%
warsow 0.64%
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Dave Airlie [Mon, 7 Sep 2015 22:36:32 +0000 (08:36 +1000)]
r600: don't use shader key without verifying shader type (v2)
Since
7a32652231f96eac14c4bfce02afe77b4132fb77
r600: Turn 'r600_shader_key' struct into union
we were accessing key fields that might be aliased in the union
with other fields, so we should check what shader type we are
compiling for before using key values from it.
v1.1: make it compile
v2: have caffeine, make it work - we don't set type
until later, so don't reference it until we've set it.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ben Widawsky [Tue, 8 Sep 2015 17:19:22 +0000 (10:19 -0700)]
i965/skl: Use more compact hiz dimensions
I meant to do this here, but it was in the wrong place:
commit
c1151b18f2dce7c6f238f057e9c4fa8d912ce6b5
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date: Wed Jun 24 20:07:54 2015 -0700
i965/skl: Use more compact hiz dimensions
NOTE: Jordan did go back and look at the original mailing list post. I mailed
the right thing, and pushed the wrong one.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Ilia Mirkin [Tue, 8 Sep 2015 20:58:43 +0000 (16:58 -0400)]
st/mesa: increase viewport bounds limits for GL4 hw
According to the ARB_viewport_array spec, GL4 limit is higher than the
GL3 limit. Also take this opportunity to fix the GL3 limit.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sun, 6 Sep 2015 08:51:29 +0000 (04:51 -0400)]
nvc0: always emit a full shader colormask
Indications are that if the colormask indicates a single bit set on
fermi, that value will always be read from $r0 instead of a potentially
higher register (if e.g. green is set). Not to upset the counting logic,
always set the header up with a full color mask for each RT. Such a
situation can basically only ever happen with generated blit shaders.
Fixes the following piglit on Fermi (Kepler is unaffected):
fbo-stencil blit GL_DEPTH32F_STENCIL8
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Brian Paul [Tue, 8 Sep 2015 14:47:01 +0000 (08:47 -0600)]
docs: fix date formatting in index.html
Iago Toral Quiroga [Tue, 1 Sep 2015 09:32:29 +0000 (11:32 +0200)]
nir: UBO loads no longer use const_index[1]
Commit
2126c68e5cba killed the array elements parameter on load/store
intrinsics that was stored in const_index[1]. It looks like that
patch missed to remove this assignment in the UBO path.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Hans de Goede [Mon, 7 Sep 2015 19:50:48 +0000 (21:50 +0200)]
nv30: Fix max width / height checks in nv30 sifm code
The sifm object has a limit of 1024x1024 for its input size and 2048x2048
for its output. The code checking this was trying to be clever resulting
in it seeing a surface of e.g 1024x256 being outside of the input size
limit.
This commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Chris Wilson [Sat, 5 Sep 2015 18:19:33 +0000 (19:19 +0100)]
i965: Disallow fast blit paths for CopyTexImage with PixelTransfer ops
glCopyTexImage behaves similarly to glReadPixels with respect to the
pixel transfer operations. Therefore if any are set we cannot use the
simple blit-only fast paths.
(Though if would be possible to relax the blorp path to handle
pixel zoom, or we can just enhance meta.)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviwewed-by: Iago Toral <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Jon TURNEY [Fri, 4 Sep 2015 11:43:06 +0000 (12:43 +0100)]
mesa/tests: Remove unneeded X11_CFLAGS
X11_CFLAGS is never defined. Path to X11 headers is not needed here, so
just remove.
Future work: Using AM_CFLAGS here looks wrong, as this Makefile only builds
C++ files
Signed-off-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Jon TURNEY [Fri, 4 Sep 2015 11:43:05 +0000 (12:43 +0100)]
glxl/tests: Use X11_INCLUDES instead of X11_CFLAGS
X11_CFLAGS is undefined, so these tests will fail to build if x11proto is
installed in a non-standard location.
(See also commits
35189d76,
bc93c3798,
54b028ba,
d901d7e08, etc.)
Signed-off-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Thomas Hellstrom [Fri, 4 Sep 2015 10:26:05 +0000 (03:26 -0700)]
svga: Fix surface view error handling
Make sure errors are correcly propagated.
Also don't flush during state emission if emission fails.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Rob Clark [Thu, 3 Sep 2015 06:13:33 +0000 (23:13 -0700)]
xa: add xa_surface_from_handle2 v2
Like xa_surface_from_handle(), but takes a handle type, rather than
hard-coding 'shared' handle. This is needed to fix bugs seen with
xf86-video-freedreno with xrandr rotation, for example. The root issue
is that doing a GEM_OPEN ioctl on a bo that already has a GEM handle
associated with the drm_file will result in two unique handles for the
same bo. Which causes all sorts of follow-on fail.
v2:
- Add support for for fd handles.
- Avoid duplicating code.
- Bump xa version minor.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Alejandro Piñeiro [Sat, 5 Sep 2015 13:26:59 +0000 (15:26 +0200)]
i965/nir/vec4: removed unneeded tex src swizzle set
At that point the swizzle should be correct.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Ilia Mirkin [Mon, 7 Sep 2015 04:06:51 +0000 (00:06 -0400)]
util: make mesa-sha1.c completely empty when there are no SHA1 impls
My earlier attempt to fix this missed the fact that there was a #else
clause that assumes that you have openssh. This moves the whole thing
under #ifdef HAVE_SHA1 which should avoid this issue.
Fixes:
13bfa5201 (util: always include sha1 into the build)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91898
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@gmail.com>
Ilia Mirkin [Fri, 4 Sep 2015 20:43:22 +0000 (16:43 -0400)]
util: always include sha1 into the build
SHA1 is now used in all builds when HAVE_SHA1 is defined. Adjust src to
do the same thing, rather than predicating on shader cache.
Fixes:
04e201d0c02 ("mesa: change 'SHADER_SUBST' facility to work with env variables")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@gmail.com>
Ilia Mirkin [Sun, 6 Sep 2015 15:29:00 +0000 (11:29 -0400)]
st/mesa: don't fall back to 16F when 32F is requested
Nothing in the spec allows for the reduced precision, and this also
fixes st_QuerySamplesForFormat for nv50, which does not allow MS8 on
RGBA32F. Now this will be respected instead of reporting MS8 as
supported with an assumption that the format used will be RGBA16F.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sat, 5 Sep 2015 17:11:27 +0000 (13:11 -0400)]
st/mesa: properly handle u_upload_alloc failure
vbuf is never null. We want to make sure that a resource was allocated
for the vbuf, which is *vbuf.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Thu, 2 Jul 2015 22:44:18 +0000 (18:44 -0400)]
nouveau: don't mark full range as used on unmap with explicit flush
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Mon, 24 Aug 2015 15:49:05 +0000 (11:49 -0400)]
nv50: avoid using inline vertex data submit when gl_VertexID is used
The hardware only generates vertexid when vertices come from a VBO. This
fixes:
vertexid-drawelements
vertexid-drawarrays
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sat, 4 Jul 2015 00:32:53 +0000 (20:32 -0400)]
nv50: don't flush vertex arrays when index buffer changes
The index buffer is fed in inline over a pushbuf. It's not related to
vertices or any caching that might be done on them.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Sat, 4 Jul 2015 00:16:48 +0000 (20:16 -0400)]
nv50: rebind bo to bufctx when invalidating idxbuf storage
There is nothing to be done on a dirty idxbuf, but the bo may have
changed, so we have to rebind it to the bufctx.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Fri, 3 Jul 2015 23:21:21 +0000 (19:21 -0400)]
nv50: clear buffer status on all vertex bufs, not just the first one
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Thu, 1 Jan 2015 11:09:59 +0000 (06:09 -0500)]
nv50: fix drawing from tfb, direct-to-pushbuf submits
The stride was being set to 0, which is illegal (and also non-sensical).
Also we must wait for the buffer to become available for reading as
otherwise a wrong value may be prefetched. Since we must wait for the
buffer anyways, and it's mapped and in GART, we may as well avoid the
annoyance of the indirect pushbuf submit.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ben Widawsky [Fri, 4 Sep 2015 17:42:33 +0000 (10:42 -0700)]
i965: Remove base miplevel from sampler state.
Gen9 changes the meaning of this to coarse LOD quality mode. Although that's a
desirable thing to be setting, it doesn't match the gen8 behavior and this was
unintentional. More importantly, we don't ever use this field. So instead of
getting it "wrong" drop it entirely.
This is a respin of a patch which only [incorrectly] tried to address gen9.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Emil Velikov [Fri, 4 Sep 2015 22:11:40 +0000 (23:11 +0100)]
docs: add news item and link release notes for 10.6.6
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Fri, 4 Sep 2015 22:05:47 +0000 (23:05 +0100)]
docs: add sha256 checksums for 10.6.6
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
e3e2a3e0e581da39dcd9268951edb52f68916940)
Emil Velikov [Fri, 4 Sep 2015 21:16:07 +0000 (22:16 +0100)]
docs: add release notes for 10.6.6
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
4b05739e9d718a48415270b95c0a73b56666c364)
Oded Gabbay [Thu, 3 Sep 2015 16:00:26 +0000 (19:00 +0300)]
llvmpipe: convert double to long long instead of unsigned long long
round(val*dscale) produces a double result, as val and dscale are double.
However, LLVMConstInt receives unsigned long long, so there is an
implicit conversion from double to unsigned long long.
This is an undefined behavior. Therefore, we need to first explicitly
convert the round result to long long, and then let the compiler handle
conversion from that to unsigned long long.
This bug manifests itself in POWER, where all IMM values of -1 are being
converted to 0 implicitly, causing a wrong LLVM IR output.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Hans de Goede [Thu, 3 Sep 2015 10:38:01 +0000 (12:38 +0200)]
nv30: Implement color resolve for msaa
Note this is not ideal. Since the sifm can only do source sizes upto
1024x1024 we end up using the blitter on nv4x, which is not that fast.
And on nv3x we end up using the cpu which is really slow.
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Hans de Goede [Wed, 12 Aug 2015 11:39:42 +0000 (13:39 +0200)]
nv30: Fix creation of scanout buffers
Scanout buffers on nv30 must always be non-swizzled and have special
width alignment constraints.
These constrains have been taken from the xf86-video-nouveau
src/nv_accel_common.c: nouveau_allocate_surface() function.
nouveau_allocate_surface() applies these width constraints only when a
tiled attribute is set, which it sets for all surfaces allocated via
dri, and this "tiling" is not the same as swizzling, scanout surfaces
must be linear / have a uniform_pitch or only complete garbage is shown.
This commit fixes dri3 on nv30 showing a garbled display, with dri3 the
scanout buffers are allocated by mesa, rather then by the ddx, and the
wrong stride of these buffers was causing the garbled display.
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Boyan Ding [Wed, 26 Aug 2015 11:52:50 +0000 (19:52 +0800)]
vc4: Initialize pack field of qreg to 0 in qir_get_temp
This avoids generation of undefined packing in qir and qpu instructions,
fixing a lot of rendering errors.
Fixes
8b36d107fdd (vc4: Pack the unorm-packing bits into a src MUL
instruction when possible.)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Chris Wilson [Fri, 4 Sep 2015 18:02:28 +0000 (19:02 +0100)]
i965: Disallow PixelTransfer operations for tiled-memcpy TexImage/ReadPixels
The tiled memcpy fast paths perform a simple blit (with only a couple of
trivial pixel conversion routines) and do not accommodate PixelTransfer
operations. Therefore if any are set, fallback to the regular routines.
Note that PixelTransfer only applies to TexImage and ReadPixels, not to
GetTexImage.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Iago Toral Quiroga [Fri, 4 Sep 2015 11:23:20 +0000 (13:23 +0200)]
i965/vec4: Don't unspill the same register in consecutive instructions
If we have spilled/unspilled a register in the current instruction, avoid
emitting unspills for the same register in the same instruction or consecutive
instructions following the current one as long as they keep reading the spilled
register. This should allow us to avoid emitting costy unspills that come with
little benefit to register allocation.
v2:
- Apply the same logic when evaluating spilling costs (Curro).
v3:
- Abstract the logic that decides if a register can be reused in a function.
that can be used from both spill_reg and evaluate_spill_costs (Curro).
v4:
- Do not disallow reusing scratch_reg in predicated reads (Curro).
- Track if previous sources in the same instruction read scratch_reg (Curro).
- Return prev_inst_read_scratch_reg at the end (Curro).
- No need to explicitily skip scratch read/write opcodes in spill_reg (Curro).
- Fix the comments explaining what happens when we hit an instruction that
does not read or write scratch_reg (Curro)
- Return true early when the current or previous instructions read
scratch_reg with a compatible mask.
v5:
- Do not return true early, the loop should not be expensive anyway
and this adds more complexity (Curro).
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Thu, 23 Jul 2015 09:11:53 +0000 (11:11 +0200)]
i965: Add a debug option for spilling everything in vec4 code
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Thu, 3 Sep 2015 12:20:04 +0000 (15:20 +0300)]
dri/common: Tokenize driParseDebugString() argument before matching debug flags.
Fixes debug string parsing when one of the supported flags is a
substring of another.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 3 Sep 2015 11:50:12 +0000 (14:50 +0300)]
dri/common: Fix codestyle of driParseDebugString().
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Tapani Pälli [Thu, 3 Sep 2015 11:26:48 +0000 (14:26 +0300)]
glsl: error out on ES 3.1 if VS or FS present but not both
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tapani Pälli [Thu, 3 Sep 2015 11:20:46 +0000 (14:20 +0300)]
glsl: error on linking if no shaders are attached to program
This applies to OpenGL Core >= 4.5 and OpenGL ES >= 3.1.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Thu, 13 Aug 2015 21:52:55 +0000 (14:52 -0700)]
i965: Improve disassembly of data port read messages.
We now print out the name of the message instead of its numerical
value, and label the message control and surface numbers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Fri, 15 May 2015 17:08:19 +0000 (10:08 -0700)]
i965: Optimize VUE map comparisons.
The entire VUE map is computed based on the slots_valid bitfield;
calling brw_compute_vue_map on the same bitfield will return the
same result. So we can simply compare those.
struct brw_vue_map is 136 bytes; doing a single 8-byte comparison is
much cheaper and should work just as well.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 29 Aug 2015 06:47:25 +0000 (23:47 -0700)]
i965/gs: Don't reserve space for clip plane uniforms.
These were only for legacy userclipping, which we no longer support
in geometry shaders.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Fri, 28 Aug 2015 08:43:23 +0000 (01:43 -0700)]
i965: Don't do legacy userclipping in non-compatibility contexts.
According to the GLSL 1.50 specification, page 76:
"The shader must also set all values in gl_ClipDistance that have been
enabled via the OpenGL API, or results are undefined."
With this patch, we only enable clip distance writes when the shader
actually writes them. We no longer force a value to be written when
clip planes are enabled in the API. This could mean the first varying
slot would be used as clip distances - I believe it should be the safe
kind of undefined behavior.
Empirically, it doesn't seem to cause a problem.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Fri, 28 Aug 2015 01:24:39 +0000 (18:24 -0700)]
i965: Remove the brw_vue_prog_key base class.
The legacy userclip fields are only used for the vertex shader, and at
that point there's only program_string_id and the tex struct, which are
common to all keys. So there's no need for a "VUE" key base class.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Fri, 28 Aug 2015 07:29:05 +0000 (00:29 -0700)]
i965: Virtualize vec4_visitor::emit_urb_slot().
This avoids a downcast of key, which won't exist in the base class soon.
I'm not a huge fan of this patch, but given that we're currently using
inheritance, this seems like the "right" way to do it. The alternative
is to make key a void pointer in the parent class and continue
downcasting.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Fri, 28 Aug 2015 06:55:28 +0000 (23:55 -0700)]
i965: Store a key_tex pointer in vec4_visitor.
I'm about to remove the base class for VS/GS/HS/DS program keys, at
which point we won't be able to use key->tex anymore. Instead, we'll
need to store a direct pointer (like we do in the FS backend).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Fri, 28 Aug 2015 06:49:03 +0000 (23:49 -0700)]
i965: Move legacy clip plane handling to vec4_vs_visitor.
This is now only used for the vertex shader, so it makes sense to get it
out of any paths run by the geometry shader.
Instead of passing the gl_clip_plane array into the run() method (which
is shared among all subclasses), we add it as a vec4_vs_visitor
constructor parameter. This eliminates the bogus NULL parameter in the
GS case.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Fri, 28 Aug 2015 00:02:27 +0000 (17:02 -0700)]
i965: Delete the brw_vue_program_key::userclip_active flag.
There are two uses of this flag.
The primary use is checking whether we need to emit code to convert
legacy gl_ClipVertex/gl_Position clipping to clip distances. In this
case, we also have to upload the clip planes as uniforms, which means
setting nr_userclip_plane_consts to a positive value. Checking if it's
> 0 works for detecting this case.
Gen4-5 also wants to know whether we're doing clipping at all, so it can
emit user clip flags. Checking if output_reg[VARYING_SLOT_CLIP_DIST0]
is set to a real register suffices for this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Thu, 27 Aug 2015 21:04:40 +0000 (14:04 -0700)]
i965: Remove legacy clip plane handling from geometry shaders.
We only support geometry shaders in core profiles, where gl_ClipVertex
doesn't exist. Presumably the even older behavior of clipping to
gl_Position isn't supported either. In fact, GLSL 1.50 page 76 claims:
"The shader must also set all values in gl_ClipDistance that have been
enabled via the OpenGL API, or results are undefined."
So we don't need to handle legacy clipping in geometry shaders. I think
Paul added this back when we were considering supporting the old
GL_ARB_geometry_shader4 extension.
This removes a non-orthagonal state dependency on GS compilation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Fri, 28 Aug 2015 01:27:20 +0000 (18:27 -0700)]
i965: Move brw_setup_tex_for_precompile to brw_program.[ch].
This living in brw_fs.{h,cpp} is a historical artifact of us supporting
texturing for fragment shaders before any other stages. It's kind of
awkward given that we use it for all stages.
This avoids having to include brw_fs.h in geometry shader code in order
to access this function.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Tapani Pälli [Mon, 31 Aug 2015 06:54:23 +0000 (09:54 +0300)]
mesa: change 'SHADER_SUBST' facility to work with env variables
Patch modifies existing shader source and replace functionality to work
with environment variables rather than enable dumping on compile time.
Also instead of _mesa_str_checksum, _mesa_sha1_compute is used to avoid
collisions.
Functionality is controlled via two environment variables:
MESA_SHADER_DUMP_PATH - path where shader sources are dumped
MESA_SHADER_READ_PATH - path where replacement shaders are read
v2: cleanups, add strerror if fopen fails, put all functionality
inside HAVE_SHA1 since sha1 is required
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Suggested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tapani Pälli [Thu, 3 Sep 2015 05:34:42 +0000 (08:34 +0300)]
build: add HAVE_SHA1 define when using --with-sha1 option
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Brian Paul <brianp@vmware.com>
Kenneth Graunke [Wed, 2 Sep 2015 23:39:27 +0000 (16:39 -0700)]
i965: Fix copy propagation type changes.
commit
472ef9a02f2e5c5d0caa2809cb736a0f4f0d4693 introduced code to
change the types of SEL and MOV instructions for moves that simply
"copy bits around". It didn't account for type conversion moves,
however. So it would happily turn this:
mov(8) vgrf6:D, -vgrf5:D
mov(8) vgrf7:F, vgrf6:UD
into this:
mov(8) vgrf6:D, -vgrf5:D
mov(8) vgrf7:D, -vgrf5:D
which erroneously drops the conversion to float.
Cc: "11.0 10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Dave Airlie [Thu, 3 Sep 2015 22:02:14 +0000 (08:02 +1000)]
r600: fix loop overrun in cayman_mul_double_instr
Coverity warned about this. Ilia pointed it out.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ben Widawsky [Wed, 26 Aug 2015 23:35:40 +0000 (16:35 -0700)]
i965/gen9: Annotate input coverage mask change
As far as I can tell, the behavior is preserved from the previous generations.
Before we set a single bit to tell the FS whether or not we'll be using an input
coverage mask. Now we have some options which are implementing various
extensions. These bits are used for the various conservative rasterization
mechanisms (for collision detection, binning, and whatever else).
I believe that the behavior is preserved because the problem which conservative
rasterization is attempting to fix would go away with the "NORMAL" mode (at the
cost of performance, I believe).
This patch serves as documentation of the change by creating the enums, as well
as giving some of the history with the links here so that the next person who
comes along and looks at it doesn't spend as long as I had to in order to
determine if there is an issue or not.
Previously, this algorithm had been done in software, and this can still be used
as long as we don't export an extension stating otherwise.
References: https://www.opengl.org/registry/specs/NV/conservative_raster.txt
References: https://http.developer.nvidia.com/GPUGems2/gpugems2_chapter42.html
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Thu, 3 Sep 2015 17:23:36 +0000 (11:23 -0600)]
svga: update call to u_upload_alloc()
u_upload_alloc() no longer returns a return value.
Trivial.
Marek Olšák [Tue, 1 Sep 2015 02:14:43 +0000 (04:14 +0200)]
winsys/radeon: remove exported buffers from the cache
Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Tue, 1 Sep 2015 02:14:33 +0000 (04:14 +0200)]
winsys/amdgpu: remove exported buffers from the cache
Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Tue, 1 Sep 2015 02:07:54 +0000 (04:07 +0200)]
gallium/pb_bufmgr_cache: add a way to remove buffers from the cache explicitly
This must be done before exporting a buffer as dmabuf fds, because
we lose track of who is using it and can't trust the reference counter.
Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Wed, 2 Sep 2015 13:11:40 +0000 (15:11 +0200)]
u_upload_mgr: remove the return value from u_upload_data
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 2 Sep 2015 13:11:40 +0000 (15:11 +0200)]
u_upload_mgr: remove the return value from u_upload_buffer
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 2 Sep 2015 13:11:40 +0000 (15:11 +0200)]
u_upload_mgr: remove the return value from u_upload_alloc_buffer
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 2 Sep 2015 13:08:23 +0000 (15:08 +0200)]
u_upload_mgr: remove the return value from u_upload_alloc
The return buffer or the returned pointer can be used instead.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 2 Sep 2015 12:57:55 +0000 (14:57 +0200)]
u_upload_mgr: optimize u_upload_alloc
This is probably the most called util function. It does almost nothing,
yet it can consume 10% of the CPU on the profile. This drops it down to 5%.
Reviewed-by: Brian Paul <brianp@vmware.com>
Grazvydas Ignotas [Wed, 2 Sep 2015 22:54:32 +0000 (01:54 +0300)]
gallium/radeon: remove 'dirty' member from r600_atom
It's no longer used by both r600 and radeonsi now.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Wed, 2 Sep 2015 22:54:31 +0000 (01:54 +0300)]
r600g: simplify dirty atom tracking
Now that R600_NUM_ATOMS is below 64, dirty atom tracking can be
simplified.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Wed, 2 Sep 2015 22:54:30 +0000 (01:54 +0300)]
r600g: start numbering atoms from 1
There doesn't seem any reason to start from 4.
Start from 1 instead (0 is left reserved to catch uninitialized atoms).
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Wed, 2 Sep 2015 22:54:29 +0000 (01:54 +0300)]
r600g: make all viewport states use single atom
Similarly to scissor states, we can use single atom to track all viewport
states. This will allow to simplify dirty atom handling later.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Wed, 2 Sep 2015 22:54:28 +0000 (01:54 +0300)]
r600g: apply disable workaround on all scissors
During review of the "r600g: make all scissor states use single atom" patch
Marek Olšák noticed that scissor disable workaround should be applied on
all scissor states and not just first one, so let's do so.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Wed, 2 Sep 2015 22:54:27 +0000 (01:54 +0300)]
r600g: make all scissor states use single atom
As suggested by Marek Olšák, we can use single atom to track all scissor
states. This will allow to simplify dirty atom handling later.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Neil Roberts [Wed, 2 Sep 2015 10:29:16 +0000 (11:29 +0100)]
mesa/pbo: Handle zero width, height or depth when validating access
It's legal to call glTexSubImage with zero values for the width,
height or depth. Previously this was breaking the PBO access
validation because it tries to work out the last pixel accessed by
getting the pixel at height-1 and depth-1 which would end up with
bogus values.
This was causing GL errors to be generated during the Piglit
texsubimage test, although the test was passing anyway.
v2: Also check for width == 0. Don't validate the start pointer if any
of the dimensions are zero.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Thu, 3 Sep 2015 07:55:40 +0000 (00:55 -0700)]
glsl: Remove unused total_attribs_size variable.
Accidentally left behind by my previous patch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 2 Sep 2015 17:42:57 +0000 (10:42 -0700)]
glsl: Handle attribute aliasing in attribute storage limit check.
In various versions of OpenGL and GLSL, it's possible to declare
multiple VS input variables with aliasing attribute locations.
So, when computing the storage requirements for vertex attributes,
we can't simply add up the sizes. Instead, we need to look at the
enabled slots.
This patch begins tracking which attributes are double types that
are larger than 128-bits (i.e. take up two vec4 slots). We then
count normal attributes once, and count the double-size attributes
a second time.
Fixes deQP functional.attribute_location.bind_aliasing.max_cond_* tests
on i965, which regressed with commit
ad208d975a6d3aebe14f7c2c16039ee20.
No Piglit changes on llvmpipe (which actually supports dvecs).
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 2 Sep 2015 00:42:31 +0000 (17:42 -0700)]
i965/meta: Fix typo in comment
Trivial.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Tue, 1 Sep 2015 01:44:42 +0000 (18:44 -0700)]
mesa: Don't allow wrong type setters for matrix uniforms
Previously we would allow glUniformMatrix4fv on a dmat4 and
glUniformMatrix4dv on a mat4. Both are illegal. That later also
overwrites the storage for the mat4 and causes bad things to happen.
Should fix the (new) arb_gpu_shader_fp64-wrong-type-setter piglit test.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Cc: Dave Airlie <airlied@redhat.com>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Ian Romanick [Tue, 1 Sep 2015 01:30:48 +0000 (18:30 -0700)]
mesa: Pass the type to _mesa_uniform_matrix as a glsl_base_type
This matches _mesa_uniform, and it enables the bug fix in the next
patch.
v2: s/type/basicType/ in the assert in _mesa_uniform_matrix.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au> [v1]
Cc: Dave Airlie <airlied@redhat.com>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Ian Romanick [Wed, 26 Aug 2015 12:50:04 +0000 (13:50 +0100)]
mesa: Silence unused parameter warnings in bufferobj.c
main/bufferobj.c: In function 'count_buffer_size':
main/bufferobj.c:520:26: warning: unused parameter 'key' [-Wunused-parameter]
count_buffer_size(GLuint key, void *data, void *userData)
^
main/bufferobj.c: In function 'flush_mapped_buffer_range_fallback':
main/bufferobj.c:740:56: warning: unused parameter 'index' [-Wunused-parameter]
gl_map_buffer_index index)
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ian Romanick [Wed, 26 Aug 2015 12:55:54 +0000 (13:55 +0100)]
mesa: Remove target parameter from _mesa_handle_bind_buffer_gen
main/bufferobj.c: In function '_mesa_handle_bind_buffer_gen':
main/bufferobj.c:915:37: warning: unused parameter 'target' [-Wunused-parameter]
GLenum target,
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ian Romanick [Wed, 19 Aug 2015 21:25:48 +0000 (14:25 -0700)]
i965: Make gen7_enable_hw_binding_tables static
All of the other state upload functions are static because the only use
is in the brw_tracked_state structure.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Ian Romanick [Wed, 19 Aug 2015 20:54:21 +0000 (13:54 -0700)]
i965: Make gen8_upload_state_base_address static
All of the other state upload functions are static because the only use
is in the brw_tracked_state structure.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Ian Romanick [Wed, 19 Aug 2015 20:36:22 +0000 (13:36 -0700)]
linker: Silence GCC unused parameter warnings
linker.cpp:320:55: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_leave(ir_function *ir)
^
linker.cpp:327:53: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_leave(ir_return *ir)
^
linker.cpp:333:49: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_enter(ir_if *ir)
^
linker.cpp:339:49: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_leave(ir_if *ir)
^
linker.cpp:345:51: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_enter(ir_loop *ir)
^
linker.cpp:351:51: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_leave(ir_loop *ir)
^
linker.cpp:2824:53: warning: unused parameter 'ctx' [-Wunused-parameter]
link_calculate_subroutine_compat(struct gl_context *ctx, struct gl_shader_program *prog)
^
linker.cpp:2854:47: warning: unused parameter 'ctx' [-Wunused-parameter]
check_subroutine_resources(struct gl_context *ctx, struct gl_shader_program *prog)
^
linker.cpp:3368:49: warning: unused parameter 'ctx' [-Wunused-parameter]
link_assign_subroutine_types(struct gl_context *ctx,
^
Also make link_assign_subroutine_types static since it is only called
from this file.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ian Romanick [Wed, 19 Aug 2015 00:41:30 +0000 (17:41 -0700)]
mesa: Fix warning about static being in the wrong place
Because the compiler already has enough things to complain about.
grep -rl 'const static' src/ | while read f
do
sed --in-place -e 's/const static/static const/g' $f
done
brw_eu_emit.c: In function 'brw_reg_type_to_hw_type':
brw_eu_emit.c:98:7: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int imm_hw_types[] = {
^
brw_eu_emit.c:120:7: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int hw_types[] = {
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jordan Justen [Tue, 23 Sep 2014 23:46:39 +0000 (16:46 -0700)]
i965/cs: Setup push constant data for uniforms
brw_upload_cs_push_constants was based on gen6_upload_push_constants.
v2:
* Add FINISHME comments about more efficient ways to push uniforms
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Jordan Justen [Mon, 25 May 2015 19:23:05 +0000 (12:23 -0700)]
meta: Save/restore compute shaders
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Charmaine Lee [Fri, 21 Aug 2015 18:41:26 +0000 (11:41 -0700)]
svga: fix referencing a NULL framebuffer cbuf
Check for a valid framebuffer cbuf pointer before accessing its
associated surface.
Fix piglit test fbo-drawbuffers-none.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Fri, 21 Aug 2015 17:36:24 +0000 (10:36 -0700)]
svga: increment texture age when surface is to be marked as dirty
Commit
b9ba8492 removes an unneeded pipe_surface_release() from
st_render_texture(). This implies a surface can now be reused for a
render buffer. Currently, when we render to a texture, we mark the
surface as dirty. But in svga_mark_surface_dirty(), if the surface
is already marked as dirty, it does not increment the texture age.
Any view to this texture might not be updated properly then.
With this patch, the texture age is incremented regardless of whether
the surface is already marked as dirty or not.
Fix bug 1499181.
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Charmaine Lee [Thu, 13 Aug 2015 22:08:22 +0000 (15:08 -0700)]
svga: fix backed surface view regression
Commit
b9ba8492 removes an unneeded pipe_surface_release() from
st_render_texture() and exposes a bug in the backed surface view
creation. Currently a backed surface view for a conflicted surface view
is created at framebuffer emit time. But if shader sampler views are changed
but framebuffer surface views remain unchanged, emit_framebuffer() will not
be called and conflicted surface views will not be detected.
To fix this, also check for conflicted surface views when setting sampler
views. If there is any conflicted surface views, enable the
framebuffer dirty bit so that the framebuffer emit code has a chance to
create a backed surface view for the conflicted surface view.
Fix cinebench-r11-test regression.
Reviewed-by: Brian Paul <brianp@vmware.com>
Matt Turner [Wed, 2 Sep 2015 05:00:24 +0000 (22:00 -0700)]
i965/fs: Handle MRF destinations in lower_integer_multiplication().
The lowered code reads from the destination, which isn't possible from
message registers.
Fixes the following dEQP tests on SNB:
dEQP-GLES3.functional.shaders.precision.int.highp_mul_fragment
dEQP-GLES3.functional.shaders.precision.int.mediump_mul_fragment
dEQP-GLES3.functional.shaders.precision.int.lowp_mul_fragment
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Brian Paul [Thu, 13 Aug 2015 20:50:13 +0000 (13:50 -0700)]
docs: document VMware OpenGL 3.3 support
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Thu, 13 Aug 2015 18:00:58 +0000 (11:00 -0700)]
svga: update driver for version 10 GPU interface
This is a squash commit of roughly two years of development work.
Authors include:
Brian Paul
Charmaine Lee
Thomas Hellstrom
Jakob Bornecrantz
Sinclair Yeh
Mingcheng Chen
Kai Ninomiya
MengLin Wu
The driver supports OpenGL 3.3.
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 7 Aug 2015 21:41:17 +0000 (15:41 -0600)]
svga: add new version 10 device command prototypes
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 7 Aug 2015 21:23:51 +0000 (15:23 -0600)]
svga: add new svga_streamout.h file
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 7 Aug 2015 22:04:03 +0000 (16:04 -0600)]
svga: add new svga_state_tgsi_transform.c file
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 7 Aug 2015 21:22:18 +0000 (15:22 -0600)]
svga: add new svga_state_sampler.c file
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 7 Aug 2015 21:22:01 +0000 (15:22 -0600)]
svga: add new svga_state_gs.c file
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 7 Aug 2015 21:21:46 +0000 (15:21 -0600)]
svga: add new svga_pipe_streamout.c file
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 7 Aug 2015 21:21:29 +0000 (15:21 -0600)]
svga: add new svga_pipe_gs.c file
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 7 Aug 2015 21:21:10 +0000 (15:21 -0600)]
svga: add new svga_link.[ch] files
Signed-off-by: Brian Paul <brianp@vmware.com>