Samuel Pitoiset [Tue, 23 Aug 2022 08:34:54 +0000 (10:34 +0200)]
radv: stop gathering info for FS before other stages
This is no longer needed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Tue, 23 Aug 2022 08:05:36 +0000 (10:05 +0200)]
radv: link primitive ID/clip distance shader info from the new helper
No functional changes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Tue, 23 Aug 2022 07:39:47 +0000 (09:39 +0200)]
radv: add a helper that links shader info between stages
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Tue, 23 Aug 2022 17:07:43 +0000 (19:07 +0200)]
radv: remove redundant VS output parameter assignments
assign_outinfo_params() should already assign them.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Tue, 23 Aug 2022 06:48:56 +0000 (08:48 +0200)]
radv: fill radv_vs_output_info unconditionally for vertex related stages
That shouldn't change anything for VS as LS (or as ES) and for
TES as ES because radv_vs_output_info is only used by the last
vertex stage. So, if we have TES+GS, radv_vs_output_info for TES
will be overwritten by GS. This allows to decouple the shader info
pass from other stages.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Mon, 22 Aug 2022 17:23:57 +0000 (19:23 +0200)]
radv: stop duplicating radv_vs_output_info
Only the last vertex stage needs to access this.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Thu, 25 Aug 2022 07:17:40 +0000 (09:17 +0200)]
radv/llvm: remove unused parameter in handle_vs_outputs_post()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Mon, 22 Aug 2022 17:08:12 +0000 (19:08 +0200)]
radv: replace cs.uses_task_rings by ms.has_task
Task shaders always use a ring, so this field was useless somehow.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Mon, 22 Aug 2022 17:06:20 +0000 (19:06 +0200)]
radv: remove dead code about task ring when binding a compute pipeline
This is probably a leftover when task shader has been reworked, but it
has no effect.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Tue, 23 Aug 2022 06:00:50 +0000 (08:00 +0200)]
radv: compute the ESGS itemsize outside of radv_nir_shader_info_pass()
radv_nir_shader_info_pass() should run on individual shaders only, and
"linked" shader info should be done separately for better design.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Mon, 22 Aug 2022 16:46:06 +0000 (18:46 +0200)]
radv: use esgs_itemsize when calling ac_nir_lower_es_outputs_to_mem
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Mon, 22 Aug 2022 16:03:27 +0000 (18:03 +0200)]
radv: stop duplicating radv_es_output_info
This structure isn't really useful and it contains only one field.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Tue, 23 Aug 2022 11:08:45 +0000 (13:08 +0200)]
ac: constify ac_compute_cs_workgroup_size()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
Samuel Pitoiset [Fri, 26 Aug 2022 06:56:14 +0000 (08:56 +0200)]
aco: fix wrong size for 1D images and A16 on GFX9
Size is in bytes, not bits.
Fixes plenty of crashes in CI, like
dEQP-VK.synchronization.op.single_queue.event.write_image_fragment_read_image_tess_eval.image_128_r32_uint.
Fixes:
46f6e2ddbbb ("aco: Implement storage image A16.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18266>
Samuel Pitoiset [Thu, 25 Aug 2022 12:33:35 +0000 (14:33 +0200)]
radv: destroy the pipeline layout if creating a library failed
It should be properly cleaned.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18252>
Samuel Pitoiset [Thu, 25 Aug 2022 12:30:21 +0000 (14:30 +0200)]
radv: fix missing initialization of the pipeline layout when creating a lib
The base object won't be initialized otherwise.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18252>
Samuel Pitoiset [Thu, 25 Aug 2022 12:27:54 +0000 (14:27 +0200)]
radv: remove bogus assertion about independent set layouts with GPL
layout->independent_sets can't be TRUE here.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18252>
Samuel Pitoiset [Thu, 25 Aug 2022 08:29:00 +0000 (10:29 +0200)]
radv: re-emit viewports if negative one to one or depth clamp mode changed
The following sequence would be broken if we don't re-emit viewports.
vkCmdSetViewport()
VkCmdBindPipeline(negative_one_to_one = false)
vkCmdDraw()
VkCmdBindPipeline(negative_one_to_one = true)
vkCmdDraw()
Found by inspection.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18245>
Danylo Piliaiev [Fri, 12 Aug 2022 14:31:59 +0000 (17:31 +0300)]
tu: Update HS_WAVE_INPUT_SIZE formula
A better explanation for SP_HS_WAVE_INPUT_SIZE is that it is the size
of local memory to allocate per wave (which can be more than one
patch), in 256B units.
Then the maximum of 64 makes sense because only 16KB of local memory
is reserved for VS<->HS linkage.
The resulting formula matches the blob behaviour, even when
patch_control_points and tcs_vertices_out have different values,
while the past formula gave wrong answers on gen3+.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Suggested-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17957>
Danylo Piliaiev [Tue, 9 Aug 2022 10:50:27 +0000 (13:50 +0300)]
tu: Fix streamout with tess_use_shared
Mirrors
31835ac3b8e30abe2677454bbc1468b4cd04b394 change in freedreno.
Together with "tu: Fix HS input size formula for gen3+" fixes following
tests from GL CTS running via Zink:
dEQP-GLES31.functional.tessellation.invariance.inner_triangle_set.quads_fractional_odd_spacing
dEQP-GLES31.functional.tessellation.invariance.inner_triangle_set.triangles_fractional_odd_spacing
dEQP-GLES31.functional.tessellation.invariance.primitive_set.triangles_fractional_odd_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.primitive_set.triangles_fractional_odd_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.triangle_set.triangles_fractional_odd_spacing
dEQP-GLES31.functional.tessellation.primitive_discard.quads_fractional_odd_spacing_ccw
dEQP-GLES31.functional.tessellation.primitive_discard.quads_fractional_odd_spacing_cw
dEQP-GLES31.functional.tessellation.primitive_discard.triangles_fractional_odd_spacing_ccw
dEQP-GLES31.functional.tessellation.primitive_discard.triangles_fractional_odd_spacing_cw
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17957>
Danylo Piliaiev [Wed, 10 Aug 2022 10:20:32 +0000 (13:20 +0300)]
freedreno: PC_SO_STREAM_CNTL_STREAM_ENABLE has per-stream enable bits
PC_SO_STREAM_CNTL.STREAM_ENABLE mirrors VPC_SO_STREAM_CNTL.STREAM_ENABLE
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17957>
Danylo Piliaiev [Mon, 15 Aug 2022 17:45:51 +0000 (20:45 +0300)]
tu: Implement VK_EXT_attachment_feedback_loop_layout
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18064>
Erik Faye-Lund [Thu, 25 Aug 2022 07:43:06 +0000 (09:43 +0200)]
zink: wrap discard in a function
This makes discard less weird, and allows us to treat it as
control-flow. This makes things less bizarre for drivers.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7070
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
Erik Faye-Lund [Thu, 25 Aug 2022 07:42:43 +0000 (09:42 +0200)]
zink: add spirv_builder_function_call
It can be useful not just to create functions, but also being able to
call them. This adds the spirv_builder-helper for this.
Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
Erik Faye-Lund [Thu, 25 Aug 2022 07:23:57 +0000 (09:23 +0200)]
zink: type_main -> type_void_func
This type will be reused later on, so let's have the name describe what
is *is*, not what it's *used for*.
Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
Jordan Justen [Thu, 25 Aug 2022 17:19:35 +0000 (10:19 -0700)]
intel/pci_ids: Add 0x468b ADL-S PCI-id
Ref: bspec 53655
Fixes:
d399c3e861a ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>
Jordan Justen [Wed, 12 May 2021 19:09:35 +0000 (12:09 -0700)]
intel/pci_ids: Update ADL-S strings
Ref: bspec 53655
Fixes:
d399c3e861a ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>
Gert Wollny [Tue, 23 Aug 2022 15:31:57 +0000 (17:31 +0200)]
r600/sfn: Use a low number for unused target register
This reduces the number of registers reserved by the shader
units and makes more threads possible.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6856
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 14:21:39 +0000 (16:21 +0200)]
r600: Fix reporting TGSI IR support
When NIR is not explicitely enabled we still support TGSI.
Fixes:
33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 13:46:36 +0000 (15:46 +0200)]
r600/sfn: Use a heuristic to keep SSBO setup and store close
When SSBO instructions use constant address values the address loading
is immediately ready, scheduling the address loads early increases
the register pressure, so force a new instruction block to work around
this problem.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
v2: do handling in shader block to be thread save (hinted to by Filip)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 13:35:06 +0000 (15:35 +0200)]
r600/sfn: Don't scan the whole block for ready instructions
Limit the number of tested instructions and the number of
ready instructions that might be taken into account.
This reduces the time needed to run the scheduler significantly.
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 13:30:23 +0000 (15:30 +0200)]
r600/sfn: Don't schedule GDS instructions early
Atomic GDS instructions like inc, dec, or read will increase the
register pressure, therefore we shouldn't prioritize scheduling them.
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 13:03:48 +0000 (15:03 +0200)]
r600/sfn: Don't tag mem-ring and stream instructions as exports
Export instructions allow burst writes, so it makes send to try
to allocate consecutive registers, but for ring writes we don't
schedule the outputs correctly to exploit this, so for now
don't mark these instructions as export to let the RA restart
picking colors.
When the scheduler starts to emit the ring writes in the right order
to allow for bust writes we might revisit this.
This fixes
spec@glsl-1.50@execution@variable-indexing@gs-output-array-vec4-index-wr
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 07:27:10 +0000 (09:27 +0200)]
r600/sfn: Handle color0 writes all on R700 like on EG
Fixes:
069f3869ac3a140898224c8c37d5b3b6349361a4
r600/sfn: Fix color outputs when color0 writes all
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Lucas Stach [Thu, 25 Aug 2022 12:16:37 +0000 (14:16 +0200)]
etnaviv: add debug option to disable linear PE feature
Linear PE has already shown to have some rough corner cases in the hardware
and also has performance implications. Add a debug option to allow to disable
the feature, so users can more easily check if some issue is caused by this
feature.
CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
Lucas Stach [Wed, 24 Aug 2022 14:26:52 +0000 (16:26 +0200)]
etnaviv: use linear PE rendering only on properly aligned surfaces
When linear rendering is used together with TS, the color tiles must be fully
contained in a single row of pixels. When wrapping around to the next row
TS gets confused and records wrong tile status information, leading to visual
corruption when the surface is resolved/decompressed.
The corruption can be fixed by increasing the stride alignment for linear
render targets, but that would break some existing use-cases, as some display
engines used together with Vivante GPUs currently don't support strides that
don't match the horizontal display resolution.
For now only enable linear PE rendering when the surface is properly aligned
already. This allows to use the optimization in a lot of common use-cases, but
falls back to the proven tiled rendering with subsequent resolve into linear
for the problematic cases.
CC: mesa-stable #22.2
Fixes:
53445284a42 ("etnaviv: add linear PE support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
Lucas Stach [Wed, 13 Jul 2022 17:58:23 +0000 (19:58 +0200)]
etnaviv: move checking for MC2.0 for TS into screen init
The decision whether to use fast clear aka TS currently checks for two
feature bits: FAST_CEAR and MC20. We check for MC20, as TS on MC1.0 bypasses
the memory offset and we don't have any way to fixup the GPU address to
account for that. It could be done with some support of the kernel driver,
but then GPUs with MC1.0 are very rare to find these days, so not sure if we
are ever going to bother with that.
Instead of checking two separate feature bits to determine if TS can be used,
mask out the FAST_CLEAR bit from the features when MC20 isn't present. This
way we only have to check for a single feature bit.
CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
Samuel Pitoiset [Wed, 24 Aug 2022 15:41:42 +0000 (17:41 +0200)]
radv: stop emitting RMW context registers for updating sample locations
RMW context registers have been removed in RadeonSI a while ago
because they don't seem good for performance.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
Samuel Pitoiset [Wed, 24 Aug 2022 15:14:53 +0000 (17:14 +0200)]
radv: cleanup dynamic states in radv_emit_graphics_pipeline()
Some dynamic states always need to be emitted when the first pipeline
is emitted, some others depend on pipeline state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
Samuel Pitoiset [Wed, 24 Aug 2022 15:10:33 +0000 (17:10 +0200)]
radv: stop clearing bitfields for registers that are emitted dynamically
These fields aren't set at pipeline creation, so clearing them is
just useless.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
Samuel Pitoiset [Wed, 24 Aug 2022 15:09:42 +0000 (17:09 +0200)]
radv: stop setting CB_COLOR_CONTROL.ROP3 from the pipeline
This is useless because logic op is a dynamic state and it's already
emitted from the cmdbuf.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
Qiang Yu [Wed, 15 Jun 2022 09:51:25 +0000 (17:51 +0800)]
ac/llvm: cast tes_u/v_replaced to float
Otherwise LLVM float ops fail to operate on them.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Fri, 8 Jul 2022 13:35:18 +0000 (21:35 +0800)]
ac/nir/ngg: support clipdist culling
Port from radeonsi.
Besides vertex position based primitive culling, clipdist
attribute can also be used to cull a primitive. Normally
it's used by fixed-pipeline, but when NGG we can treate it
as a culling condition to filter out invisible primitive
before fixed-pipeline.
There are two kinds of clipdist:
1. user define a clip plane explicitly by glClipPlane(),
fixed-pipeline calculate with vertex position to get
clipdist, then cull. This is the legacy way.
2. Now GLSL define gl_ClipDistance/gl_CullDiatance so that
user can calculate clipdist in any way he like.
This implementation support both way.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Mon, 13 Jun 2022 09:29:06 +0000 (17:29 +0800)]
ac/nir/ngg: support component position store
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Thu, 9 Jun 2022 01:11:10 +0000 (09:11 +0800)]
ac/nir/ngg: add gs culling
Port from radeonsi.
Cull primitive after GS thread and before final vertex/primitive
export. GS culling is like VS/TES culling which read out saved
vertex positions of a primitive from LDS then call the primitive
culling algorithm to check whether it's visiable or not, only
passed primitives will be exported.
Unlike the VS/TES culling that read vertex index of a primitive
from VGPRs as shader args, GS will set a primitive complete flag
for each last vertex of a primitive in LDS, so that vertex thread
know the previous 1/2/3 vertex can form a primitive and do primitive
culling.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Fri, 22 Jul 2022 12:34:34 +0000 (20:34 +0800)]
ac/nir/ngg: save and restore position output base for nogs
radeonsi has different driver_location and io location.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Sat, 23 Jul 2022 08:22:49 +0000 (16:22 +0800)]
ac/nir/ngg: save and restore output bit size for gs
radeonsi does not have io nir variables, so need to save output
bit size when lower store_output intrinsic.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Wed, 13 Jul 2022 00:55:20 +0000 (08:55 +0800)]
ac/nir/ngg: use same driver location for gs output
driver_location and io location are different for radeonsi,
and radeonsi llvm rely on the correct driver_location to
index output variables.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Tue, 12 Jul 2022 14:11:48 +0000 (22:11 +0800)]
ac/nir/ngg: fix and simplify gs store output lower
Simplify: 64bit IO has been lowered by nir_lower_io with
nir_lower_io_lower_64bit_to_32, so no need to handle in the
ngg lower.
Fix: we need to increase io_sem.location by base_offset for
correct gs_output_info.
radeonsi has different driver_location and io location, so
also change the output variable index to io location.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Mon, 6 Jun 2022 09:06:41 +0000 (17:06 +0800)]
ac/nir/ngg: support line culling
Port from ac_llvm_cull.c
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Tue, 9 Aug 2022 13:47:11 +0000 (21:47 +0800)]
ac/nir/cull: support caller react when primitive is rejected
Make accept_func optional, and return accpect result for caller
react when primitive is rejected.
This is for GS culling.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Wed, 3 Aug 2022 09:56:36 +0000 (17:56 +0800)]
ac/nir/ngg,radv: use nir_load_viewport_xy_scale_and_offset
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Wed, 3 Aug 2022 08:45:36 +0000 (16:45 +0800)]
nir,ac/llvm: add nir_intrinsic_load_viewport_xy_scale_and_offset
Used by RADV/Radeonsi NGG culling. Pack them into a single vec4
load for radeonsi to reduce const buffer load.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Mon, 6 Jun 2022 08:37:16 +0000 (16:37 +0800)]
nir,ac/llvm: add nir_intrinsic_load_half_line_width_amd
Used by AMD GPU NGG line culling. We could use nir load
line width and viewport scale to calculate this in shader,
but this way needs expensive divide ops.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Dave Airlie [Thu, 11 Aug 2022 02:57:12 +0000 (12:57 +1000)]
gallivm: don't indirect image/sampler destroy.
These are pointless indirections, just call direct the destroy
functions.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
Dave Airlie [Mon, 8 Aug 2022 19:28:06 +0000 (05:28 +1000)]
gallivm/sample: remove unused base parameter from dynamic callbacks.
This parameters was never used anywhere, so just remove it.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
Dave Airlie [Mon, 8 Aug 2022 19:19:52 +0000 (05:19 +1000)]
gallivm: drop unused parameter to lp_build_sample_aos
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
Emma Anholt [Fri, 26 Aug 2022 02:40:38 +0000 (19:40 -0700)]
ci: disable the freedreno farm.
It seems to have gone down at the end of the day today. I'm off tomorrow,
someone else can debug.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18263>
Emma Anholt [Sun, 10 Jul 2022 03:28:42 +0000 (20:28 -0700)]
ci: Move 'never' rules includes above "on_success" rules includes.
The farm online-ness filters were listed after some of the checks for
whether code changed, so an offline farm might still be used in that case.
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18263>
Kenneth Graunke [Wed, 24 Aug 2022 22:11:32 +0000 (15:11 -0700)]
iris: Use linear for exported resources if we can't convey tiling
If we have modifiers, we can use those to convey the tiling of exported
resources. If we have the deprecated i915 GET/SET_TILING uAPI, we can
use that to convey the tiling.
If we have neither, then we have to fall back to linear.
Fixes:
e6588354360 ("iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6938
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18240>
Jesse Natalie [Thu, 11 Aug 2022 21:02:18 +0000 (14:02 -0700)]
dzn: Get max supported shader model
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 20:51:26 +0000 (13:51 -0700)]
d3d12: Get max supported shader model
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 20:40:49 +0000 (13:40 -0700)]
microsoft/compiler: Support SM6.7
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 20:02:27 +0000 (13:02 -0700)]
microsoft/compiler: SM6.6 is supported
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 20:00:39 +0000 (13:00 -0700)]
microsoft/compiler: Handle SM6.6 handles
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 19:48:12 +0000 (12:48 -0700)]
microsoft/compiler: Pass lower_bound, upper_bound, space to createhandle
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 19:37:56 +0000 (12:37 -0700)]
microsoft/compiler: Delete double-assignment of sampler metadata field
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 19:37:44 +0000 (12:37 -0700)]
microsoft/compiler: Add getters for res bind/props structs
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 17:23:22 +0000 (10:23 -0700)]
microsoft/compiler: Add dynamic create handle helper
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 16:46:42 +0000 (09:46 -0700)]
microsoft/compiler: Add struct and function defs for SM6.6 handle funcs
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 16:38:45 +0000 (09:38 -0700)]
microsoft/compiler: Support up to shader model 6.5
We don't actually use any of the new features, but that's okay, it's
still valid DXIL at the higher shader models.
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 16:35:58 +0000 (09:35 -0700)]
microsoft/compiler: Always emit a shader at the max-supported shader model
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Chia-I Wu [Thu, 25 Aug 2022 16:11:53 +0000 (09:11 -0700)]
turnip: improve tracing of secondary cmd buffers
This visualizes secondary cmd buffers in perfetto. I did not test
dynamic rendering, which appears to call tu_clone_trace_range already.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 23:37:28 +0000 (16:37 -0700)]
turnip: add cmd_buffer tracepoint
It is only used for primary cmd buffers for the moment.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 18:04:39 +0000 (11:04 -0700)]
turnip: rename some tracing stages
Rename SURFACE_STAGE_ID to RENDER_PASS_STAGE_ID. Indicate whether gmem
or bypass is used in the stage name.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 20:09:35 +0000 (13:09 -0700)]
turnip: clean up tu_perfetto.h
Move enums, stages, queues, and some function declarations to
tu_perfetto.cc.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 19:30:29 +0000 (12:30 -0700)]
turnip: convert tu_perfetto_state to a stack
A stage does not end until its nested stages end. tu_perfetto_state can
be a stack.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 22:54:42 +0000 (15:54 -0700)]
turnip: add tu_clone_trace_range helper
Remove some duplicated code.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 17:06:31 +0000 (10:06 -0700)]
util/u_trace: add PERFETTO HeaderScope
Headers with the PERFETTO scope will be included by the generated
perfetto utils header. This is needed because to_prim_type may have
header dependencies.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 17:23:17 +0000 (10:23 -0700)]
util/u_trace: include the generated header first
This is a good practice to make sure the generated header is
self-contained (no missing includes, declarations, etc.).
Remove unnecessary SOURCE header scope from the default.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 17:23:20 +0000 (10:23 -0700)]
turnip: tidy up tracepoint header includes
Remove unused util/u_dump.h. Add missing forward declarations.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Wed, 24 Aug 2022 01:18:02 +0000 (18:18 -0700)]
turnip: fix gem_store tracepoint
Set cmd->trace_renderpass_end after tu6_emit_tile_store in case of gmem.
To be able to do that, we push the update of cmd->trace_renderpass_end
down into tu_cmd_render_tiles/tu_cmd_render_sysmem.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Thu, 25 Aug 2022 15:47:50 +0000 (08:47 -0700)]
turnip: move trace_start_gmem_store before cond exec
Suggested by Danylo.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 21:03:04 +0000 (14:03 -0700)]
turnip: fix a missing trace_end_gmem_clear
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 01:15:24 +0000 (18:15 -0700)]
turnip: improve perfetto sync_timestamp
tu_device_get_gpu_timestamp takes >100us on my otherwise idle sc7180.
Read the cpu block again after the call returns.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Yiwei Zhang [Fri, 19 Aug 2022 19:45:05 +0000 (19:45 +0000)]
venus: avoid scrubing wsi/external sempahores
When the renderer supports sync_fd import for the binary semaphore,
venus can import the special signaled payload to the semaphore instead
of scrubing it. This avoids the bugs w.r.t timeline semaphore and device
group submission in the legacy scrub path.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 18 Aug 2022 21:57:47 +0000 (21:57 +0000)]
venus: re-implement sync_fd external sempahore
sync_wait is deferred to a submission that waits on the semaphore.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 18 Aug 2022 16:55:06 +0000 (16:55 +0000)]
venus: re-implement sync_fd external fence
Instead of waiting for signal before importing, we are able to retain
the imported sync file and handle the fence related commands on the
driver side.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Sat, 13 Aug 2022 06:55:38 +0000 (06:55 +0000)]
venus: query renderer sync_fd props to fill the feature stubs
This change enables the fixed code paths.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 22:20:09 +0000 (22:20 +0000)]
venus: fix vn_GetSemaphoreFdKHR
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 17:09:43 +0000 (17:09 +0000)]
venus: fix vn_GetFenceFdKHR
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 18:31:13 +0000 (18:31 +0000)]
venus: put android wsi on the sub-optimal path
Simplify Android wsi to only use performant path if fixed sync_fd fence
support is enabled. This removes hacky codes and allows us to deprecate
a special ring wait code path as well.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 05:55:34 +0000 (05:55 +0000)]
venus: stub out renderer sync_fd fencing features
With syncFdFencing feature, venus starts forwarding renderer sync_fd
fencing support. The driver side now can track the renderer sync_fd
fencing features. This change adds the initial stubs.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 05:45:44 +0000 (05:45 +0000)]
venus: sync to latest venus protocol headers for syncFdFencing
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 11 Aug 2022 22:38:20 +0000 (22:38 +0000)]
venus: avoid pre-allocating the feedback pool
Now that we don't create fence upon device creation, let's also defer
the feedback pool grow to the first event or non-external fence
creation. This makes venus device creation lighter and is good for CI.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 11 Aug 2022 22:33:26 +0000 (22:33 +0000)]
venus: lazily create queue wait fence and make it non-external
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 11 Aug 2022 22:08:43 +0000 (22:08 +0000)]
venus: use a separate sync fence for Android wsi
Also refactors the codes a bit.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Sat, 6 Aug 2022 05:18:49 +0000 (05:18 +0000)]
venus: avoid feedback for external fence
Sync fd fence export implies a payload reset operation, and application
can immediately do another submission with the same fence after export.
Concurrent use of the same feedback slot is incorrect. Keeping a list of
feedback slots for sync_fd external fence is a bit over designed given
those fences are usually not checked or waited by the app, but will hand
off the ownership via sync fd to an external client.
Fixes:
d7f2e6c8d03 ("venus: add fence feedback")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 4 Aug 2022 21:15:48 +0000 (21:15 +0000)]
venus: require necessary extensions for common wsi support
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Mon, 8 Aug 2022 18:19:03 +0000 (18:19 +0000)]
venus: fix external memory ext filtering
Fixes:
390722620e1 ("venus: clean up vn_device_fix_create_info")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>