Mike Blumenkrantz [Tue, 18 Oct 2022 15:36:10 +0000 (11:36 -0400)]
zink: add some spirv builder handling for sampled image ops
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 16:18:08 +0000 (12:18 -0400)]
zink: simplify image deref handling
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 17:22:25 +0000 (13:22 -0400)]
zink: add a nir pass for CL image typing and sampler tracking
cl images and samplers come through untyped, so they need to be typed
before they can be used
samplers are also not combined into the descriptor, so track a mask which
can be used later for emission
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 15:07:34 +0000 (11:07 -0400)]
zink: pass image type to image emission
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 15:00:37 +0000 (11:00 -0400)]
zink: rework sampler emission
this simplifies all the different sampler metadata tracking fields to be
more comprehensible
it also increases some array sizes in case future work increases them outside
the compiler areas
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 14:11:08 +0000 (10:11 -0400)]
zink: pass KERNEL shaders through successfully
basically just merging with COMPUTE cases
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 14:10:53 +0000 (10:10 -0400)]
zink: match bitsizes in bo rewriting
technically this matters
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Lionel Landwerlin [Thu, 15 Sep 2022 19:10:46 +0000 (22:10 +0300)]
intel/fs: use fs implementation of dump_instructions
This specialized version prints out the liveness count as well as the
maximum liveness count. It was eye opening when seeing the max
liveness jump after lowering of packing instructions which should not
have changed the count.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
Lionel Landwerlin [Tue, 13 Sep 2022 23:40:01 +0000 (02:40 +0300)]
intel/fs: reduce liveness of variables in lowering passes
When lowering a single instruction with a destination VGRF to 2 or
more, the VGRF is now considered partially written by each generated
instruction and that increases its liveness especially in loops. Thus
potentially increasing the number of spills/fills due to register
allocation.
Putting an UNDEF instruction in front of the lowered instructions
allows the IR to limit the liveness of the VGRF, reducing register
pressure.
This has a pretty dramatic effect on spills/fills for RT shaders. Here
the stats on Q2RTX shaders on DG2 (wipping out any spills/fills due to
register allocation) :
Instructions in all programs: 26150 -> 24955 (-4.6%)
SENDs in all programs: 1148 -> 1148 (+0.0%)
Loops in all programs: 4 -> 4 (+0.0%)
Cycles in all programs: 392179 -> 332787 (-15.1%)
Spills in all programs: 132 -> 116 (-12.1%)
Fills in all programs: 262 -> 154 (-41.2%)
Shader-db results on TGL :
total instructions in shared programs:
21158140 ->
21158377 (<.01%)
instructions in affected programs: 76629 -> 76866 (0.31%)
helped: 18
HURT: 20
helped stats (abs) min: 1 max: 60 x̄: 18.89 x̃: 12
helped stats (rel) min: 0.21% max: 3.61% x̄: 1.02% x̃: 0.77%
HURT stats (abs) min: 1 max: 79 x̄: 28.85 x̃: 18
HURT stats (rel) min: 0.04% max: 2.81% x̄: 1.13% x̃: 0.79%
95% mean confidence interval for instructions value: -4.82 17.30
95% mean confidence interval for instructions %-change: -0.34% 0.57%
Inconclusive result (value mean confidence interval includes 0).
total loops in shared programs: 5753 -> 5753 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total cycles in shared programs:
798856834 ->
798870688 (<.01%)
cycles in affected programs: 6208395 -> 6222249 (0.22%)
helped: 22
HURT: 17
helped stats (abs) min: 2 max: 8794 x̄: 1438.18 x̃: 782
helped stats (rel) min: 0.05% max: 2.28% x̄: 0.63% x̃: 0.44%
HURT stats (abs) min: 2 max: 19178 x̄: 2676.12 x̃: 1358
HURT stats (rel) min: 0.04% max: 23.49% x̄: 2.25% x̃: 0.71%
95% mean confidence interval for cycles value: -952.19 1662.65
95% mean confidence interval for cycles %-change: -0.64% 1.90%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 4078 -> 4066 (-0.29%)
spills in affected programs: 40 -> 28 (-30.00%)
helped: 2
HURT: 0
total fills in shared programs: 2856 -> 2832 (-0.84%)
fills in affected programs: 127 -> 103 (-18.90%)
helped: 2
HURT: 0
total sends in shared programs: 998554 -> 998554 (0.00%)
sends in affected programs: 0 -> 0
helped: 0
HURT: 0
LOST: 0
GAINED: 0
Total CPU time (seconds): 2346.06 -> 2304.80 (-1.76%)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
Lionel Landwerlin [Fri, 16 Sep 2022 20:35:08 +0000 (23:35 +0300)]
intel/fs: make split_virtual_grfs deal with partial undefs
v2: fix up UNDEFs instructions (Curro)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
Lionel Landwerlin [Thu, 22 Sep 2022 07:14:28 +0000 (10:14 +0300)]
intel/fs: require UNDEFs register offsets to be aligned to REG_SIZE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
Emma Anholt [Wed, 21 Sep 2022 19:49:07 +0000 (12:49 -0700)]
turnip: Fix reservation for indirect compute's IR3_DP_SUBGROUP_ID_SHIFT.
Fixes an assert in GravityMark.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19203>
Alyssa Rosenzweig [Fri, 21 Oct 2022 20:46:21 +0000 (16:46 -0400)]
pan/mdg: Don't schedule across memory barrier
Fixes KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-cs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 20:38:38 +0000 (16:38 -0400)]
panfrost: Lower MAX_BLOCK_SIZE on Midgard
To match PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, having it be higher in any
dimension is nonsensical and can confuse apps. Fixes tests in
KHR-GLES31.core.texture_buffer.* on Mali-T860.
Fixes:
9b19104a30b ("pan/mdg: Lower PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK on Midgard")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 19:36:03 +0000 (15:36 -0400)]
panfrost: Avoid a XFB special case
This worked around an issue that doesn't apply to the Valhall XFB lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 16:28:35 +0000 (12:28 -0400)]
panfrost: Use compute-based XFB on Midgard
Now we're back to a single XFB implementation for all gens. Fixes:
KHR-GLES31.core.draw_indirect.advanced-twoPasses-transformFeedback-arrays
KHR-GLES31.core.draw_indirect.advanced-twoPasses-transformFeedback-elements
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 19:34:52 +0000 (15:34 -0400)]
pan/mdg: Fix 64-bit address arithmetic
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 16:42:49 +0000 (12:42 -0400)]
pan/bi: Clean up sysval handling a bit
Combine some cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 20:22:21 +0000 (16:22 -0400)]
panfrost: Don't allow VS side effects on midgard
So we can use the common XFB lowering, and try to reduce the differences between
Midgard and Bifrost (given that Bifrost is conformant and actively maintained,
and Midgard is neither, getting Midgard as close to Bifrost is in the best
interests of Midgard's long term prospects upstream). Piles of KHR-GLES31 tests
from Fail -> Skip.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 20:01:56 +0000 (16:01 -0400)]
panfrost: Zero polygon list for fragment-only
Even with hierarchical tiling. Otherwise if there's garbage leftover (due to BO
caching), a fragment-only batch can raise DATA_INVALID_FAULT. Fixes many tests
in KHR-GLES31.core.compute_shader.* on Mali-T860, including
KHR-GLES31.core.compute_shader.build-separable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Tue, 25 Oct 2022 16:54:32 +0000 (12:54 -0400)]
nir/lower_idiv: Inline convert_instr_precise
Now that we only have one convert_instr path, this is simpler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19303>
Alyssa Rosenzweig [Tue, 25 Oct 2022 16:53:39 +0000 (12:53 -0400)]
nir/lower_idiv: Remove imprecise_32bit_lowering
NIR has two implementations of lower_idiv, keyed on the
imprecise_32bit_lowering flag. This flag is misleading: the results when
setting this flag "imprecise", they're completely wrong for some values.
If a backend has a native implementation of umul_high, the correct path
isn't that much more expensive. If it doesn't, it's substantially slower
for highp integer divison... but in practice, non-constant highp integer
division is pretty rare.
After a painful migration of the tree, this code path has no more users.
Remove it so nobody else gets the bright idea of using it again.
Closes: #6555
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19303>
Alyssa Rosenzweig [Tue, 25 Oct 2022 16:40:32 +0000 (12:40 -0400)]
etnaviv: Use correct idiv lowering
imprecise_32bit_lowering produces wrong outputs for some inputs. Do not
use it, it is wrong. The correct lowering generates umul_high
instructions, which need to be lowered via lower_alu. That lowering in
turn produces uadd_carry instructions which also need lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19303>
José Roberto de Souza [Thu, 27 Oct 2022 17:16:01 +0000 (10:16 -0700)]
hasvk: Fix build around intel_measure_state_changed() call
Fixes:
2bc82581ad22 ("anv: add support for mesh shading in INTEL_MEASURE")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19355>
Italo Nicola [Sun, 7 Aug 2022 13:30:19 +0000 (13:30 +0000)]
rusticl: fix MemConstant invalid arg size check
As a memory object, the MemConstant check should be the same as
MemGlobal.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19352>
Brian Paul [Wed, 26 Oct 2022 21:32:42 +0000 (15:32 -0600)]
llvmpipe: asst. clean-ups in lp_state_fs.c
Move var decls to first use. Add const qualifiers, comments, etc.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19330>
Brian Paul [Wed, 26 Oct 2022 21:23:25 +0000 (15:23 -0600)]
llvmpipe: fix comment typo
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19330>
Brian Paul [Wed, 26 Oct 2022 21:10:30 +0000 (15:10 -0600)]
llvmpipe: s/uint/enum pipe_prim_type/ in lp_setup_context.h
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19330>
Marcin Ślusarz [Mon, 24 Oct 2022 08:09:22 +0000 (10:09 +0200)]
anv: add mesh shading tracepoints
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19344>
Marcin Ślusarz [Thu, 27 Oct 2022 12:24:32 +0000 (14:24 +0200)]
intel/ds: add new category/stage for draw mesh events
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19344>
Marcin Ślusarz [Mon, 24 Oct 2022 07:54:11 +0000 (09:54 +0200)]
anv: add support for mesh shading in INTEL_MEASURE
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19344>
Mike Blumenkrantz [Tue, 25 Oct 2022 18:19:34 +0000 (14:19 -0400)]
zink: add docs for zink_surface
zink_surface is an abstraction that is a superset of pipe_surface,
used for all types of images
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19307>
Mike Blumenkrantz [Tue, 25 Oct 2022 17:53:52 +0000 (13:53 -0400)]
zink: add some breadcrumbs for VK_EXT_multisampled_render_to_single_sampled
at some point someone should hook this extension up to simplify/optimize
the existing msrtt handling
see also #7559
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19307>
Mike Blumenkrantz [Tue, 25 Oct 2022 17:47:40 +0000 (13:47 -0400)]
zink: delete unused zink_surface member
I think this was used before imageless_framebuffer became a requirement?
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19307>
Mike Blumenkrantz [Tue, 25 Oct 2022 17:38:34 +0000 (13:38 -0400)]
zink: use zink_resource_object::views to defer deferred storage view deletion
this is basically the same thing, so reuse the existing mechanism
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19307>
Mike Blumenkrantz [Tue, 25 Oct 2022 17:36:50 +0000 (13:36 -0400)]
zink: simplify conditional for surface rebind no-ops
the question isn't whether the storage imageview has been created,
it's whether the surface is current for the memory binding
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19307>
Mike Blumenkrantz [Tue, 25 Oct 2022 17:34:45 +0000 (13:34 -0400)]
zink: delete stale comment for zink_surface
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19307>
Mike Blumenkrantz [Tue, 25 Oct 2022 17:34:01 +0000 (13:34 -0400)]
zink: simplify swapchain imageview handling
the zink_resource_object::views array already handles this, so don't
duplicate its functionality
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19307>
Lucas Stach [Thu, 13 Oct 2022 21:21:44 +0000 (23:21 +0200)]
etnaviv: disable PE_COLOR_FORMAT_OVERWRITE with MSAA
This breaks MSAA, even when compression is not activated. The issue is
mostly theoretical, as we always enable color compression with MSAA, but
I ran into some GPU hangs when I disabled compression to run some tests.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 21:01:35 +0000 (23:01 +0200)]
etnaviv: set LOGIC_OP_UNK24 for MSAA rendering on SMALL_MSAA GPUs
Fixes MSAA corruptions on GC3000. 0x4 seems to be enough to fix the
misrendering, but blob seems to always emit 0x5.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 17:23:11 +0000 (19:23 +0200)]
etnaviv: properly size TS buffer for MSAA resources
On GPUs with the SMALL_MSAA feature, color tiles of the MSAA resource
are 256B, even if the GPU doesn't have the CACHE128B256BPERLINE feature.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 17:48:37 +0000 (19:48 +0200)]
etnaviv: rs: try to find exact format match first
For MSAA downsampling to work correctly, the RS engine needs to know
the exact format of the blit source/target. The compatible formats are
fine as long as the RS is only used as a tiler without doing any
conversion.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 17:34:34 +0000 (19:34 +0200)]
etnaviv: rs: fix MSAA alignment adjustment
The RS window alignment restrictions apply to the downsampled side of the
blit, so we must increase the blit size alignment by the MSAA scale to
avoid RS hangs. If a multi-pipe resolve is used (when the GPU doesn't have
the singlebuffer feature) then the Y alignment needs to be increased by
the number of pixel pipes.
The resource allocation has already been fixed to take this additional
alignment requirement into account.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 17:04:27 +0000 (19:04 +0200)]
etnaviv: increase alignment for MSAA resources
The RS window aligment restrictions apply to the downsampled size of a
MSAA resource, so in order to be able to do the downsample blit for all
possible sizes, we must make sure to increase the alignment of the
multisampled resource by the MSAA scale.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 16:56:14 +0000 (18:56 +0200)]
etnaviv: handle compressed texture formats in etna_layout_multiple
Instead of special casing compressed formats in the caller, handle
them properly when working out the resource alignment. For good measure
add an assert that the layout is linear, as expected.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 16:46:28 +0000 (18:46 +0200)]
etnaviv: compute linear resource Y alignment in etna_layout_multiple
Instead of adjusting the Y alignment in the callers, just do the
right (and consistent) thing in etna_layout_multiple.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 16:37:40 +0000 (18:37 +0200)]
etnaviv: assert valid layout in etna_layout_multiple
This function assigns proper values to the padding and halign parameters
for all valid layouts. Using unreachable() in the default path of the
switch statement asserts that we got a valid layout, so we can get rid of
some superfluous variable initializations and asserts in the call sites.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Lucas Stach [Thu, 13 Oct 2022 16:28:33 +0000 (18:28 +0200)]
etnaviv: move etna_layout_multiple into etnaviv_resource.c
The call sites of this function make a number of adjustments to the
padding/alignment returned by this function, which are inconsistent
and still don't cover all necessary cases. To be able to extend this
function move it out of the header and make the parameters passed
more useful by providing all necessary information at once.
No functional change, just a preparation for the following changes.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19066>
Rhys Perry [Fri, 14 Oct 2022 16:15:39 +0000 (17:15 +0100)]
ac/nir: add ac_nir_lower_ngg_options
These signatures were getting ridiculous.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19340>
Rhys Perry [Tue, 18 Oct 2022 18:52:15 +0000 (19:52 +0100)]
ac/nir: micro-optimize boolean expression
Ignoring SCC spilling, the old version is probably faster because this
mixes uniform and divergent booleans.
fossil-db (navi21):
Totals from 61167 (45.10% of 135636) affected shaders:
Instrs:
29961899 ->
29932551 (-0.10%)
CodeSize:
157407028 ->
157289636 (-0.07%)
Latency:
139671953 ->
139625186 (-0.03%); split: -0.03%, +0.00%
InvThroughput:
21221097 ->
21220756 (-0.00%)
SClause: 750438 -> 750439 (+0.00%)
Copies: 2672846 -> 2582332 (-3.39%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19340>
Martin Roukala (né Peres) [Thu, 27 Oct 2022 07:11:05 +0000 (10:11 +0300)]
zink: mark a test as a flake in RADV expectations
Having only-recently hooked monitoring up for zink-on-radv, I am
starting to capture some flakes. So, I am unsure about the reproduction
rate of this failure, but I can say it is not extremely common.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19335>
Iago Toral Quiroga [Thu, 27 Oct 2022 08:03:14 +0000 (10:03 +0200)]
v3dv: drop layout refs for all allocated sets from a pool on destroy / reset
In
7f6ecb8667c we added reference counting for descriptor set layouts,
however, we didn't realize that pools created without the flag
VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT don't free individual
descriptors and can only be reset or destroyed. Since we only drop
references when individual descriptor sets were destroyed, we would
leak set layouts referenced from descriptor sets allocated from these
pools.
Fix that by keeping a list of all allocated descriptor sets (no matter
whether VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT is present or
not) and then traversing the list dropping the references on pool resets
and destroys.
Fixes:
7f6ecb8667c ('v3dv: add reference counting for descriptor set layouts')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19337>
Lionel Landwerlin [Mon, 14 Dec 2020 10:30:33 +0000 (12:30 +0200)]
iris: enable protected contexts
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Thu, 17 Dec 2020 14:47:11 +0000 (16:47 +0200)]
iris: Emit protection & session ID on protected command buffers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Mon, 14 Dec 2020 12:17:33 +0000 (14:17 +0200)]
iris: handle protected BO creation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Wed, 26 Oct 2022 07:35:28 +0000 (10:35 +0300)]
st/gallium: plumb protected context creation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Mon, 14 Dec 2020 10:15:11 +0000 (12:15 +0200)]
egl: Add EGL_EXT_protected_content support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Tue, 18 Jan 2022 12:09:17 +0000 (14:09 +0200)]
gallium: rename PROTECTED_CONTENT cap into PROTECTED_SURFACE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Tue, 18 Jan 2022 12:03:13 +0000 (14:03 +0200)]
dri: rename PROTECTED_CONTENT in PROTECTED_SURFACE
Better suiting to the associated extension EXT_protected_surface.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Wed, 16 Dec 2020 12:09:55 +0000 (14:09 +0200)]
intel/common: add detection of protected context support
v2: Add anv bits
Fix missing i915 extension chaining helper
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Thu, 10 Dec 2020 16:38:06 +0000 (18:38 +0200)]
isl: add new MOCS field for protected buffers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
Lionel Landwerlin [Fri, 4 Dec 2020 09:00:09 +0000 (11:00 +0200)]
drm-uapi: bump headers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
David Heidelberg [Wed, 26 Oct 2022 13:54:16 +0000 (15:54 +0200)]
ci/zink: rename zink job to zink-lvp to better describe it
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19321>
Daniel Schürmann [Tue, 25 Oct 2022 07:44:43 +0000 (09:44 +0200)]
radv/rt: overwrite hit args with undef in case of a miss
This helps some variable coalescing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19188>
Daniel Schürmann [Fri, 14 Oct 2022 10:09:12 +0000 (12:09 +0200)]
radv/rt: create traversal shader independent from main shader
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19188>
Daniel Schürmann [Fri, 14 Oct 2022 10:08:05 +0000 (12:08 +0200)]
nir: add AMD RT traversal intrinsics
These I/O intrinsics help to create an enclosed traversal shader.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19188>
Jordan Justen [Mon, 24 Oct 2022 16:52:20 +0000 (12:52 -0400)]
intel/compiler: Broadcast lower code should check 64-bit int support
This will affect MTL which will have fp64 support without int64
support.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19284>
Lionel Landwerlin [Sat, 15 Oct 2022 20:02:31 +0000 (23:02 +0300)]
intel/clc: assert when libclc shader is not found
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7483
Reviewed-by: Luis Felipe Strano Moraes <luis.strano@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19091>
Iago Toral Quiroga [Tue, 27 Sep 2022 11:02:45 +0000 (13:02 +0200)]
v3dv: implement VK_EXT_pipeline_robustness
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18883>
Iago Toral Quiroga [Wed, 28 Sep 2022 06:31:57 +0000 (08:31 +0200)]
vulkan/runtime: include robustness info when hashing a shader stage
Suggested by Jason Ekstrand.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18883>
Iago Toral Quiroga [Wed, 28 Sep 2022 06:14:58 +0000 (08:14 +0200)]
broadcom/compiler: trivial code clean-up
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18883>
Iago Toral Quiroga [Tue, 27 Sep 2022 11:13:01 +0000 (13:13 +0200)]
v3dv: use enabled features from vk_device
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18883>
Iago Toral Quiroga [Wed, 28 Sep 2022 11:00:49 +0000 (13:00 +0200)]
v3dv: use NIR_PASS with v3d_nir_lower_robust_image_access
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18883>
Qiang Yu [Tue, 11 Oct 2022 08:36:49 +0000 (16:36 +0800)]
ac/nir/ngg: add one odd dword to nogs culling pervertex lds
radeonsi use like this.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Qiang Yu [Tue, 11 Oct 2022 08:29:44 +0000 (16:29 +0800)]
ac/nir/ngg,ac/llvm,aco: save nogs ngg culling one lds dword
TES rel patch id is <256, so we can use an existing unused LDS
byte instead of extra dword.
To ease the programing, change the index of repacked_arg_vars
for these variables.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Qiang Yu [Sun, 31 Jul 2022 09:53:19 +0000 (17:53 +0800)]
ac/nir/ngg: save and restore no_varying/no_sysval_output
These are used by radeonsi for param export count, should
be saved and restore.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Qiang Yu [Sat, 23 Jul 2022 09:30:52 +0000 (17:30 +0800)]
ac/nir/ngg: allow passthrough with vs primitive id output
vertex primtive id and passthrough are not exclusive, just need
to get correct vertex index when passthrough.
radeonsi won't disable passthrough when vs primitive id output,
this is also for fixing the crash of the assertion.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Qiang Yu [Fri, 22 Jul 2022 09:42:41 +0000 (17:42 +0800)]
ac/nir/ngg,radv: move LDS layout calculation out of nir ngg lowering
Use lds base load intrinsics in nir ngg lowering to get layout, left
its calulation to driver.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Qiang Yu [Fri, 22 Jul 2022 07:25:45 +0000 (15:25 +0800)]
nir: add two amd ngg lds base load intrinsics
These two values are not known when compile for radeonsi.
They are relocated when link/upload time.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Qiang Yu [Thu, 14 Jul 2022 11:56:59 +0000 (19:56 +0800)]
ac/nir/ngg: pass primitive_id_location as param for nogs lower
radeonsi need to use packed driver location for all outputs,
while radv need to use VARYING_SLOT_*. To meet both drivers'
needs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Qiang Yu [Fri, 10 Jun 2022 12:54:43 +0000 (20:54 +0800)]
ac/nir/ngg: support user edge flags for ngg lower
Pack user edge flag into arg code is ported from radeonsi
gfx10_ngg_build_export_prim.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Qiang Yu [Tue, 7 Jun 2022 07:46:36 +0000 (15:46 +0800)]
ac/llvm: get back intrinsics used by NGG
Will be used by radeonsi.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
Brian Paul [Wed, 26 Oct 2022 21:39:39 +0000 (15:39 -0600)]
glx: clean-ups in drisw_glx.c
Replace tabs with spaces. Fix up function pointer calls (don't use
the old style (*foo)(arg) syntax).
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19329>
Brian Paul [Wed, 26 Oct 2022 21:37:31 +0000 (15:37 -0600)]
glx: clean-ups in create_context.c
Replace tabs w/ spaces, remove trailing whitespace.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19329>
Brian Paul [Wed, 26 Oct 2022 21:36:15 +0000 (15:36 -0600)]
frontends/dri: clean-ups in dri_util.c
Replace tabs with spaces. Rename __ATTRIB macro to SIMPLE_CASE to
be a bit more readable.
NFC.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19329>
Brian Paul [Wed, 26 Oct 2022 21:34:38 +0000 (15:34 -0600)]
frontend/dri: assorted clean-ups in dri-screen.c
Replace tabs with spaces, fix indentation.
Move 'format' var decl and type (it's an integer array index, not
actually a mesa format).
NFC.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19329>
Yusuf Khan [Sun, 9 Oct 2022 00:39:01 +0000 (19:39 -0500)]
nv50/ir: nir_op_b2i8 and nir_op_b2i16
Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19256>
Yiwei Zhang [Mon, 24 Oct 2022 23:45:50 +0000 (23:45 +0000)]
docs: update to latest venus driver support
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19285>
Yiwei Zhang [Tue, 25 Oct 2022 05:37:42 +0000 (05:37 +0000)]
venus: add VK_EXT_depth_clip_control support
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19285>
Yiwei Zhang [Mon, 24 Oct 2022 23:38:38 +0000 (23:38 +0000)]
venus: add VK_EXT_primitives_generated_query support
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19285>
Yiwei Zhang [Mon, 24 Oct 2022 22:58:52 +0000 (22:58 +0000)]
venus: sync to latest venus protocol headers
This brings in:
- VK_KHR_push_descriptor
- VK_EXT_depth_clip_control
- VK_EXT_primitives_generated_query
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19285>
Yiwei Zhang [Tue, 25 Oct 2022 01:18:51 +0000 (01:18 +0000)]
venus: handle VkAndroidHardwareBufferFormatProperties2ANDROID
Fixes:
4d80ccbf2d0 ("venus: Enable VK_KHR_format_feature_flags2")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19287>
Yiwei Zhang [Mon, 24 Oct 2022 23:01:22 +0000 (23:01 +0000)]
venus: remove redundant codes
This is some left over from prior 1.3 effort.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19287>
Dave Airlie [Tue, 25 Oct 2022 03:43:56 +0000 (13:43 +1000)]
nir/lower_bool_to_int32: add support for lowering functions.
Change the function parameters to 32-bit.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19291>
Lionel Landwerlin [Wed, 26 Oct 2022 10:54:57 +0000 (13:54 +0300)]
nir/divergence_analysis: add missing desc_set_address_intel
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19320>
Lionel Landwerlin [Wed, 26 Oct 2022 10:54:26 +0000 (13:54 +0300)]
nir/divergence_analysis: add some missing RT intrinsics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19320>
Lionel Landwerlin [Fri, 21 Oct 2022 08:37:32 +0000 (11:37 +0300)]
vulkan/wsi/wl: correctly find whether the compositor uses the same GPU
Using the wl_drm protocol we can check whether the compositor uses the
same GPU as the application.
This allows to run vulkan applications using a DG2 GPU with the
compositor using another card.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19224>
Lionel Landwerlin [Fri, 21 Oct 2022 09:25:18 +0000 (12:25 +0300)]
anv: init major/minor before WSI
So that we can provide that information to WSI if it asks for it
immediately.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19224>
Lionel Landwerlin [Wed, 26 Oct 2022 14:40:34 +0000 (17:40 +0300)]
anv: disable mesh in memcpy
We can't have streamout and mesh enabled at the same time.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
ef04caea9b8b ("anv: Implement Mesh Shading pipeline")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19323>
Christophe [Wed, 26 Oct 2022 14:19:10 +0000 (16:19 +0200)]
Zink: add Zink profiles file
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19192>