ci: Set GALLIVM_PERF=no_filter_hacks for llvmpipe-piglit-quick_gl

Gives us 13 more passed tests.

(GALLIVM_PERF=nopt breaks some tests here)

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4986>

ci: Set GALLIVM_PERF=no_filter_hacks for llvmpipe-piglit-quick_shader

Gives us 1 more passed test.

(GALLIVM_PERF=nopt breaks some tests here)

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4986>

ci: Disable two radeonsi jobs

The machine to which these boards are connected to is having trouble
keeping up when the rootfs are expanded. This is causing jobs to time
out and fail.

So as a mitigation measure reduce the load by disabling two of these
jobs until the root problem is solved.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8930>

radeon/vcn: enable dynamic dpb Tier2 support

On VCN3 with codec AV1 and VP9

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8916>

radeon/vcn: implement dynamic dpb Tier2 support

Fill up the t2 message buffers based on reference lists, so to
avoid unnecessary allocation of the buffers.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8916>

radeon/vcn: add dynamic dpb Tier2 message buffer interface

Tier2 will dynamically manange the dpb buffers, so that can
save even more VRAMs

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8916>

radv: fix printing the debug option names

radv_dump_enabled_options() doesn't like holes. While we are at it,
use ull everywhere.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8925>

aco: optimize AC_FETCH_FORMAT_SNORM alpha adjust

This looks like it was copied from LLVM, which didn't have a fmax
intrinsic.

fossil-db (GFX8):
Totals from 43 (0.03% of 140385) affected shaders:
CodeSize: 49660 -> 49488 (-0.35%)
Instrs: 10434 -> 10348 (-0.82%)
Cycles: 41736 -> 41392 (-0.82%)
VMEM: 13793 -> 13719 (-0.54%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8918>

radv: Fix vram override with fully visible VRAM.

Fixes: cf2eebdf4f1 ("radv,gallium: Add driconf option to reduce advertised VRAM size.")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8915>

gallium/tgsi-to-nir: Take property NUM_CLIPDIST_ENABLED into account

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8919>

gallium/tgsi_to_nir: Handle SAMPLE_MASK output in FS

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8919>

radv: use the global BO list from the winsys

We had two different implements for the global BO list, one in RADV
and one in the winsys. This will also allow to make more BOs resident.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8868>

radv/winsys: enable the global BO list unconditionally

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8868>

radv/winsys: add the resident BOs to the list of BOs at submit time

The number of resident BOs is currently 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8868>

radv/winsys: add buffer_make_resident() to the API

To make a BO resident (or to evict one).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8868>

radv/winsys: set use_global_list to avoid adding a BO twice

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8868>

radv/winsys: move the debug_all_bos check outside of the add/del helpers

The add/del helpers will be used to implement the global BO list
directly in the winsys.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8868>

pan/bi: Don't check liveness unless the index is valid

Otherwise we will read out-of-bounds when the index is ~0.

Fixes: b8f042c9bb0 ("pan/bi: Dead code eliminate per-channel")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8923>

v3dv: initialize render_fd at the top of physical_device_init

This fixes an uninitialized variable warning.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8902>

gallium/u_tests: test no-op fragment shader instead of NULL fragment shader

radeonsi stopped supporting NULL fragment shaders. This makes the test pass.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8906>

tgsi_to_nir: translate FBFETCH

Tested by u_tests.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8906>

tgsi_to_nir: translate SAMPLEID

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8906>

st/mesa: do scissored clears on depth/stencil as well when supported

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8905>

zink: support nir_intrinsic_memory_barrier_buffer

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8884>

panfrost: Fix clear color packing for 12-byte formats

Make the case for 6 bytes the same as for 8 while we're at it.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8886>

radv: Update JSON generator if Windows

Use vulkan_radeon.dll, and apply current working directory.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8911>

nv50,nvc0: add scissored clear support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8901>

nv50: add PIPE_CAP_NIR_IMAGES_AS_DEREF to unsupported list

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8901>

radeonsi: don't use cp_dma prefetch on GFX6

It's not supported.

Fixes: 47587758f21 ("radeonsi: prefetch VB descriptors right after uploading")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4211
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8914>

spirv: Allow variable pointers pointing to an array of blocks

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8864>

ci: Move out expect files from .gitlab-ci

This way, when such a file is modified only the affected driver gets
tested.

It also helps to declutter the .gitlab-ci directory.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8757>

ci: Move container files into their own dir

To be more consistent and to declutter the .gitlab-ci dir.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8757>

ci: Fix selection of linker in Android builds

Otherwise, Clang will error out when it doesn't link:

Compiler stderr:
 clang: error: argument unused during compilation: '-fuse-ld=lld' [-Werror,-Wunused-command-line-argument]

When that happens when Meson is checking for the presence of macros in
sys/sysmacros.h, that file won't be included resulting in the following
errors:

ld.lld: error: undefined symbol: makedev
ld.lld: error: undefined symbol: major
ld.lld: error: undefined symbol: minor

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Eric Anholt <eric@anholt.net>
Gitlab: #4137
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8757>

pan/bi: Add nosched debug option

Forces a trivial schedule to replicate the old behaviour (for debugging
or benchmarking). Actually the new scheduler is still used, just highly
constrained; the net result should still do what's expected.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Remove older cube map lowering

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Remove old FAU assignment code

Replaced by the scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Switch to new scheduler

Delete the old.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Schedule blocks

Replicate the pattern, greedily select clauses until we run out of
instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant modifier handling

Once we've merged the clauses' constants, we need to....

1. Swap where necessary so non-pcrel constants are correctly encoded.
2. Swap where necessary so pcrel constants are in canonical positions.
3. Force M1 values for pcrel constants and final single constants.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant merging routines

These work as you would expect: first handling paired constants
(swapping to a canonical form to deduplicate), then handling unpaired
constants (packing together in a canonical form). Most of the added
complexity is from pcrel handling, but we impose strict invariants on
pcrel (no more than one PC-relative constant per clause, only M1=4 mode)
without which the algorithm would be even uglier.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant state constructor

Based on the tuple state's constants, satisfying the pcrel invariant we
impose.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant to passthrough rewrite

Mimicks the one previously done at pack time, but designed for schedule
time instead.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add trivial rewrite helpers

We need to do certain rewrites during scheduling before RA runs in order
to satsify scheduler post-conditions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Derive M0 from pcrel_idx while packing

Assumes the usual M1=4 mode.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add pcrel_idx to bi_clause

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Move bi_constant_field to bifrost.h

It's a hardware invariant, and useful for the scheduler (not just
packing).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add bi_foreach_instr_and_src_in_tuple

Rather specialized but keeps down obnoxious indentation in scheduler
passes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Extract bi_ec0_packed helper

Useful for scheduling decisions as well as packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add passthrough register rewriting helper

Passthroughs are _required_ for correct scheduling, so we have to handle
this now. The legitimacy of using passthroughs is justified by the
constraint checks and verified with asserts at pack time.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Destructively schedule a single instruction

Wrapper to select the best legal instruction, pop it off the worklist,
update the clause/tuple states, and return it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Choose instructions to schedule

In the future we'll want a heuristic minimizing register pressure but
for in-order this will suffice.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add bi_instr_schedulable predicate

Using the previously defined checks for architectural scheduling
constraints, define one top-level predicate to check if an instruction
on the worklist is ready for scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add writes_reg predicate

ATEST is a bit of a wrinkle in this, so let's keep it in one place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add T0/T1 constraint check

Not visible on real shaders yet, but it will be when we schedule
out-of-order (or implement 64-bit multiplication).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Validate reads_t

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add bi_count_succ_reads helper

The number of register writes in a tuple must be bounded by a number
based on the number of register reads in the succeeding tuple, since
writes and reads are interleaved. This helper calculates that number of
reads, noting that not every read actually counts - if the preceding
tuple writes to a read source, that will become a temporary instead of
consuming a register slot.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add bi_tuple_is_new_src

To determine the number of register reads in a tuple (which must be
bounded by 3, or 5 if you force writes), we need to count "new" sources:
those that are not already in a partially scheduled tuple.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add FAU update helper

This comes in destructive and nondestructive flavours, to be used to
insert an instruction into a tuple and check if an instruction is
insertable respectively. It is responsible for FAU slot matching.

It's annoying this sort of logic is duplicated in 3 places
(bi_lower_fau, here, and packing) but they each work with different sets
of assumptions...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant count estimates to scheduler

Needed to satisfy max constant constaints. These aren't precise but
they should be a good enough approximation for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Stub worklist routines

In the near future we'll schedule out-of-order via a dependendency graph
and worklist. For now, emulate in-order operation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Flatten block lists

From Midgard scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add cubeface lowering

For the new schedule infrastructure. This supports multiple tuples per
clause, unlike the old hack lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add scheduler data structures

To satisfy the numerous architectural scheduler constraints, quite a bit
of state is required per-tuple, per-clause, and per-block. These data
structures allow maintaining this state separate from the main IR
data structures, allowing for partial constructions and nondestructive
operations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Include ATEST datum in the instruction

Rather than doing this at pack time like before, or adding extra
constraints to the already overcomplicated scheduler, let's just include
it like a regular FAU source.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Dead code eliminate per-channel

We already track the full liveness so this is a trivial optimization,
with an especial win for shaders reading only a subset of components of
gl_FragCoord.

More importantly, it's required for proper scheduling (in soft mode)
when vectors are used and some (but not all components) are promoted to
temporary registers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Cleanup terminal block check

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Print program size in shader-db

Less critical than other metrics, but still matters for instruction
cache hit rate, and worth being aware of.

And, fine, it makes the scheduler look like a bigger win on another
axis.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Fix shader prefetch size

The prefetch buffer size is larger than first thought, but includes
the final clause, so subtract the size of the final clause from the
prefetch size.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Return the size of the last clause from bi_pack

Will be used for calculating prefetch size.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Lower transcendentals on G71

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower FP32 transcendentals where required

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Fix bi quirks detection

There is no Bifrost v8...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Rename NO_FP32_TRANSCENDENTALS quirk

Make it more obvious what the issue is. "_FAST" is not a suffix on
Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower flog2 to a table and polynomial

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower FEXP2 with a table

Connor's code, not the blob's, amusingly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower frsq to Newton-Raphson

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower frcp to Newton-Raphson

For G71 but should work on any Bifrost, probably overlaps some CL stuff.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Fix FLOG_TABLE modifier handling

These should not be in a union together.

[Note: this does not need to be backported, since the affected
instruction is not emitted under any circumstances in the stable
branches]

Fixes: dd11e5076e6 ("pan/bi: Add new bi_instr data structure")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Add bi_fmul_f32 convenience method

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

v3dv: add a perf trace when a device is created with robust buffer access

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>

v3dv: serialize pipeline compilation when debugging shaders

It is possible to compile pipelines in multiple threads, but when we
are dumping debug information for shaders, we want all the outputs
serialized so we can make sense of it.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>

v3d/common: use spaces instead of TABs

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>

CI: always expose docs artifacts

This makes it easier to preview docs changes in merge-requests. Also
make sure we build the docs right away, rather than waiting for when
marge merges. This allows us to see the artifacts right away.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8398>

radv: stop using VM_ALWAYS_VALID on APUs

It seems that VM_ALWAYS_VALID means that all BOs must fit in
memory (VRAM+GTT) for each submission. This is causing a lot of
troubles when the total allocated memory is greater than the
available memory, especially on APUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8779>

radv: add radeon_winsys_bo::use_global_list

This will allow us to use the global BO list even without
RADEON_FLAG_PREFER_LOCAL_BO which can cause a lot of troubles
on APUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8779>

nouveau: print warning about unhandled cap only once

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8831>

radv: use less AMDGPU contexts by creating only one per queue priority

It should be more efficient. Suggested by Bas.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8878>

radv/winsys: stop zeroing radv_amdgpu_cs_request

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove unused fields in radv_amdgpu_cs_request

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: simplify the user fence logic for submission

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove unused radeon_bo_usage enum

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove useless is_local check in radv_amdgpu_cs_add_buffer()

radv_cs_add_buffer() already guarantees that and virtual buffers
are added via radv_amdgpu_cs_add_virtual_buffer().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove useless continue preamble CS for IBs path

It's only used for the sysmem path which is GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove the radv_amdgpu_winsys_bo::ws indirection

This saves a 64-bit pointer from radv_amdgpu_winsys_bo and it's
also common to pass a winsys pointer as the first parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: use an array for the global BO list instead of a list

This allows to remove one 64-bit pointer from radv_amdgpu_winsys_bo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

Revert "broadcom/compiler: improve generation of if conditions"

This reverts commit 93f8f83a95383e38769bca8cd3c236d3b1c4c87f.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8903>

ci/freedreno: Run a3xx gles3 in parallel and increase coverage.

It seems that recent fixes have made its results stable (other than
existing flakiness in texturegrad), so we can use all the CPUs and a
couple more boards and get more coverage.

Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>

ci/freedreno: bump VK coverage to 1/4 of the CTS.

With the runner fixes, we were down to 2 minutes of boot time and 2
minutes of CTS time for a total of 4 minutes.  We've got plenty of time
budget now to increase our coverage.

Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>

ci/deqp: Bump runner to 0.5.1 for recent runtime perf improvements.

3 commits in 0.5.0:

- 20-40s savings on many of our CI runs by dropping the clever test size
  scaling code.

- Even bigger savings (especially on deqp-vk runs) by increasing maximuim
  test group size (~1/4 of runtime was spawning deqp on cheza, that cost
  is cut by ~75%)

- No more needing to manually set MESA_DEBUG=silent

2 commits in 0.5.1:

- Fixed automatic thread pool sizing to keep all CPUs busy (thanks for
  catching that Bas!).

- Automatically size down test groups on short test lists and many CPUs,
  so split the list evenly between CPUs (such as on freedreno -options
  jobs).

Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>

nir/algebraic: Partially revert 3f782cdd2591

I'm not sure what the logic was, but there is no opportunity for
anything to flush to zero here.  'a' is a Boolean value, and b2f
produces 1.0 or 0.0.

This was originally part of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3765/.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: Andres Gomez <agomez@igalia.com>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8910>