Bjorn Helgaas [Thu, 2 Sep 2021 19:56:51 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/endpoint'
- Add max-virtual-functions to endpoint binding (Kishon Vijay Abraham I)
- Add pci_epf_add_vepf() API to add virtual function to endpoint (Kishon
Vijay Abraham I)
- Add pci_epf_vepf_link() to link virtual function to endpoint physical
function (Kishon Vijay Abraham I)
- Add virtual function number to pci_epc_ops endpoint ops interfaces
(Kishon Vijay Abraham I)
- Simplify register base address computation for endpoint BAR configuration
(Kishon Vijay Abraham I)
- Add support to configure virtual functions in cadence endpoint driver
(Kishon Vijay Abraham I)
- Add SR-IOV configuration to endpoint test driver (Kishon Vijay Abraham I)
- Document configfs usage to create virtual functions for endpoints (Kishon
Vijay Abraham I)
* remotes/lorenzo/pci/endpoint:
Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV
misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device
PCI: cadence: Add support to configure virtual functions
PCI: cadence: Simplify code to get register base address for configuring BAR
PCI: endpoint: Add virtual function number in pci_epc ops
PCI: endpoint: Add support to link a physical function to a virtual function
PCI: endpoint: Add support to add virtual function in endpoint core
dt-bindings: PCI: pci-ep: Add binding to specify virtual function
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:51 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/xilinx-nwl'
- Document optional clock DT property (Michal Simek)
- Enable PCIe ref clock (Hyun Kwon)
* remotes/lorenzo/pci/xilinx-nwl:
PCI: xilinx-nwl: Enable the clock through CCF
dt-bindings: pci: xilinx-nwl: Document optional clock property
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:51 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/xgene'
- Remove redundant dev_err() after devm_ioremap_resource() (ErKun Yang)
* remotes/lorenzo/pci/xgene:
PCI: xgene-msi: Remove redundant dev_err() call in xgene_msi_probe()
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:50 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/tegra194'
- Fix handling BME_CHGED event (Om Prakash Singh)
- Fix MSI-X programming (Om Prakash Singh)
- Disable interrupts before entering L2 (Om Prakash Singh)
- Don't allow suspend when Tegra PCIe is in EP mode (Om Prakash Singh)
* remotes/lorenzo/pci/tegra194:
PCI: tegra194: Cleanup unused code
PCI: tegra194: Don't allow suspend when Tegra PCIe is in EP mode
PCI: tegra194: Disable interrupts before entering L2
PCI: tegra194: Fix MSI-X programming
PCI: tegra194: Fix handling BME_CHGED event
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:50 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/tegra'
- Remove unused struct tegra_pcie_bus (Krzysztof Wilczyński)
* remotes/lorenzo/pci/tegra:
PCI: tegra: make const array err_msg static
PCI: tegra: Use 'seq_puts' instead of 'seq_printf'
PCI: tegra: Fix OF node reference leak
PCI: tegra: Remove unused struct tegra_pcie_bus
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:49 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/rcar'
- Fix runtime PM imbalance in rcar_pcie_ep_probe() (Dinghao Liu)
* remotes/lorenzo/pci/rcar:
PCI: rcar: Add L1 link state fix into data abort hook
PCI: rcar: Fix runtime PM imbalance in rcar_pcie_ep_probe()
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:49 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/mediatek'
- Split DT bindings for PCIe controllers with independent MSI domains into
separate nodes for MT2712/MT7622 (Chuanjia Liu)
- Locate shared registers from "mediatek,generic-pciecfg" property
(Chuanjia Liu)
- Get IRQ from "pcie_irq" if "interrupt-names" property is present to fix
an MSI issue (Chuanjia Liu)
- Get PCI domain from "linux,pci-domain" property if present (Chuanjia Liu)
* remotes/lorenzo/pci/mediatek:
PCI: mediatek: Use PCI domain to handle ports detection
PCI: mediatek: Add new method to get irq number
PCI: mediatek: Add new method to get shared pcie-cfg base address
dt-bindings: PCI: mediatek: Update the Device tree bindings
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:48 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/keembay'
- Add Intel Keem Bay PCIe controller driver and DT binding (Srikanth
Thokala)
* remotes/lorenzo/pci/keembay:
PCI: keembay: Add support for Intel Keem Bay
dt-bindings: PCI: Add Intel Keem Bay PCIe controller
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:48 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/iproc'
- Don't fail devm_pci_alloc_host_bridge() on missing 'ranges' (Rob Herring)
- Fix BCMA probe resource handling (Rob Herring)
* remotes/lorenzo/pci/iproc:
PCI: iproc: Fix BCMA probe resource handling
PCI: of: Don't fail devm_pci_alloc_host_bridge() on missing 'ranges'
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:47 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/hyper-v'
- Add domain_nr in struct pci_host_bridge (Boqun Feng)
- Use host bridge MSI domain for root buses if present (Boqun Feng)
- Allow ARM64 virtual host bridge with no ACPI companion (e.g., Hyper-V)
(Boqun Feng)
- Make Hyper-V enumeration more generic (Arnd Bergmann)
- Set Hyper-V domain_nr at probe-time (Boqun Feng)
- Set up Hyper-V MSI domain at bridge probe-time (Boqun Feng)
- Enable Hyper-V bridge probing on ARM64 (Boqun Feng)
* remotes/lorenzo/pci/hyper-v:
PCI: hv: Turn on the host bridge probing on ARM64
PCI: hv: Set up MSI domain at bridge probing time
PCI: hv: Set ->domain_nr of pci_host_bridge at probing time
PCI: hv: Generify PCI probing
arm64: PCI: Support root bridge preparation for Hyper-V
arm64: PCI: Restructure pcibios_root_bridge_prepare()
PCI: Support populating MSI domains of root buses via bridges
PCI: Introduce domain_nr in pci_host_bridge
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:47 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/hv'
- Support Hyper-V Create Interrupt v3 message (Sunil Muthuswamy)
* remotes/lorenzo/pci/hv:
PCI: hv: Support for create interrupt v3
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:47 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/cadence'
- Convert bool in structs to bitfield (Kishon Vijay Abraham I)
- Work around J7200 non-PCIe SERDES lane electrical issue that prevents
PCIe link training (Nadeem Athani)
- Add J7200 PCIe support to j721e (Kishon Vijay Abraham I)
- Add AM64 PCIe support to j721e (Kishon Vijay Abraham I)
- Add J7200 and AM64 device IDs to endpoint test (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/cadence:
misc: pci_endpoint_test: Add deviceID for AM64 and J7200
PCI: j721e: Add PCIe support for AM64
PCI: j721e: Add PCIe support for J7200
PCI: cadence: Add quirk flag to set minimum delay in LTSSM Detect.Quiet state
PCI: cadence: Use bitfield for *quirk_retrain_flag* instead of bool
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:46 +0000 (14:56 -0500)]
Merge branch 'remotes/lorenzo/pci/aardvark'
- Fix PIO config access status checking (Evan Wang)
- Increase config access polling delay to 1.5s (Pali Rohár)
- Add PCIe Root Capabilities to bridge emulation (Pali Rohár)
- Report Config Request Retry Status when Software Visibility enabled (Pali
Rohár)
- Add back configuration of PCIe resources from 'ranges' DT property and
pay attention to DT size and CPU/PCI offset to fix issues with I/O port
space (Pali Rohár)
- Serialize masking and unmasking legacy INTx interrupts (Pali Rohár)
* remotes/lorenzo/pci/aardvark:
PCI: aardvark: Fix masking and unmasking legacy INTx interrupts
PCI: aardvark: Configure PCIe resources from 'ranges' DT property
PCI: aardvark: Fix reporting CRS value
PCI: pci-bridge-emul: Add PCIe Root Capabilities Register
PCI: aardvark: Increase polling delay to 1.5s while waiting for PIO response
PCI: aardvark: Fix checking for PIO status
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:46 +0000 (14:56 -0500)]
Merge branch 'pci/visconti'
- Add Toshiba Visconti PCIe host controller driver (Nobuhiro Iwamatsu)
* pci/visconti:
MAINTAINERS: Add entries for Toshiba Visconti PCIe controller
PCI: visconti: Add Toshiba Visconti PCIe host controller driver
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:45 +0000 (14:56 -0500)]
Merge branch 'pci/rockchip-dwc'
- Add Rockchip RK356X host controller driver (Simon Xue)
* pci/rockchip-dwc:
PCI: rockchip-dwc: Add Rockchip RK356X host controller driver
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:45 +0000 (14:56 -0500)]
Merge branch 'pci/dwc'
- Remove surplus break statement (Krzysztof Wilczyński)
* pci/dwc:
PCI: dwc: Remove surplus break statement after return
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:45 +0000 (14:56 -0500)]
Merge branch 'pci/artpec6'
- Remove surplus break statement and local code block (Krzysztof
Wilczyński)
* pci/artpec6:
PCI: artpec6: Remove local code block from switch statement
PCI: artpec6: Remove surplus break statement after return
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:44 +0000 (14:56 -0500)]
Merge branch 'pci/misc'
- Add pci_numachip_init() declaration (Krzysztof Wilczyński)
- Allocate pci_dev_str_match_path() string atomically (Dan Carpenter)
- Drop error message when Precision Time Measurement supported but not
enabled (Jakub Kicinski)
- Correct the pci_iomap.h header guard #endif comment (Jonathan Cameron)
- Add schedule point in proc_bus_pci_read() (Krzysztof Wilczyński)
- Make saved capability state private to core (Bjorn Helgaas)
- Sync __pci_register_driver() stub for CONFIG_PCI=n (Andy Shevchenko)
- Convert sta2x11 from PCI-DMA-API to generic DMA-API (Christophe JAILLET)
* pci/misc:
x86/PCI: sta2x11: switch from 'pci_' to 'dma_' API
PCI: Sync __pci_register_driver() stub for CONFIG_PCI=n
PCI: Make saved capability state private to core
PCI: Add schedule point in proc_bus_pci_read()
PCI: Correct the pci_iomap.h header guard #endif comment
PCI/PTM: Remove error message at boot
PCI: Fix pci_dev_str_match_path() alloc while atomic bug
x86/PCI: Add pci_numachip_init() declaration
# Conflicts:
# include/linux/pci.h
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:44 +0000 (14:56 -0500)]
Merge branch 'pci/vpd'
- Check Resource Item Names against those defined for type (Bjorn Helgaas)
- Treat initial 0xff as missing EEPROM (Heiner Kallweit)
- Reject resource tags with invalid size (Bjorn Helgaas)
- Don't check Large Resource Item Names for validity (Bjorn Helgaas)
- Allow access to valid parts of VPD if some is invalid (Bjorn Helgaas)
- Remove pci_vpd_size() old_size argument (Heiner Kallweit)
- Make pci_vpd_wait() uninterruptible (Heiner Kallweit)
- Remove struct pci_vpd.flag (Heiner Kallweit)
- Remove struct pci_vpd_ops (Heiner Kallweit)
- Remove struct pci_vpd.valid member (Heiner Kallweit)
- Embed struct pci_vpd in struct pci_dev (Heiner Kallweit)
- Determine VPD size in pci_vpd_init() (Heiner Kallweit)
- Treat invalid VPD like missing VPD capability (Heiner Kallweit)
- Add pci_vpd_alloc() to allocate buffer and read VPD into it (Heiner
Kallweit)
- Add pci_vpd_find_ro_info_keyword() (Heiner Kallweit)
- Add pci_vpd_check_csum() (Heiner Kallweit)
- Add pci_vpd_find_id_string() (Heiner Kallweit)
- Read VPD with pci_vpd_alloc() (bnx2x, bnxt, sfc, sfc falcon, tg3 drivers)
(Heiner Kallweit)
- Search VPD with pci_vpd_find_ro_info_keyword() (bnx2, bnx2x, bnxt, cxgb4,
cxlflash SCSI, sfc, sfc falcon, tg3 drivers) (Heiner Kallweit)
- Search VPD with pci_vpd_find_id_string() (cxgb4 driver) (Heiner Kallweit)
- Validate VPD checksum with pci_vpd_check_csum() (cxgb4, tg3 drivers)
(Heiner Kallweit)
- Replace open-coded byte swapping with swab32s() in bnx2 (Heiner Kallweit)
- Remove unused vpd_param member ec (Heiner Kallweit)
- Stop exporting pci_vpd_find_tag(), pci_vpd_find_info_keyword() (Heiner
Kallweit)
- Move several VPD defines and inlines to internal PCI core (Heiner
Kallweit)
* pci/vpd:
PCI/VPD: Use unaligned access helpers
PCI/VPD: Clean up public VPD defines and inline functions
cxgb4: Use pci_vpd_find_id_string() to find VPD ID string
PCI/VPD: Add pci_vpd_find_id_string()
PCI/VPD: Include post-processing in pci_vpd_find_tag()
PCI/VPD: Stop exporting pci_vpd_find_info_keyword()
PCI/VPD: Stop exporting pci_vpd_find_tag()
scsi: cxlflash: Search VPD with pci_vpd_find_ro_info_keyword()
cxgb4: Search VPD with pci_vpd_find_ro_info_keyword()
cxgb4: Remove unused vpd_param member ec
cxgb4: Validate VPD checksum with pci_vpd_check_csum()
bnxt: Search VPD with pci_vpd_find_ro_info_keyword()
bnxt: Read VPD with pci_vpd_alloc()
bnx2x: Search VPD with pci_vpd_find_ro_info_keyword()
bnx2x: Read VPD with pci_vpd_alloc()
bnx2: Replace open-coded byte swapping with swab32s()
bnx2: Search VPD with pci_vpd_find_ro_info_keyword()
sfc: falcon: Search VPD with pci_vpd_find_ro_info_keyword()
sfc: falcon: Read VPD with pci_vpd_alloc()
tg3: Search VPD with pci_vpd_find_ro_info_keyword()
tg3: Validate VPD checksum with pci_vpd_check_csum()
tg3: Read VPD with pci_vpd_alloc()
sfc: Search VPD with pci_vpd_find_ro_info_keyword()
sfc: Read VPD with pci_vpd_alloc()
PCI/VPD: Add pci_vpd_check_csum()
PCI/VPD: Add pci_vpd_find_ro_info_keyword()
PCI/VPD: Add pci_vpd_alloc()
PCI/VPD: Treat invalid VPD like missing VPD capability
PCI/VPD: Determine VPD size in pci_vpd_init()
PCI/VPD: Embed struct pci_vpd in struct pci_dev
PCI/VPD: Remove struct pci_vpd.valid member
PCI/VPD: Remove struct pci_vpd_ops
PCI/VPD: Reorder pci_read_vpd(), pci_write_vpd()
PCI/VPD: Remove struct pci_vpd.flag
PCI/VPD: Make pci_vpd_wait() uninterruptible
PCI/VPD: Remove pci_vpd_size() old_size argument
PCI/VPD: Allow access to valid parts of VPD if some is invalid
PCI/VPD: Don't check Large Resource Item Names for validity
PCI/VPD: Reject resource tags with invalid size
PCI/VPD: Treat initial 0xff as missing EEPROM
PCI/VPD: Check Resource Item Names against those valid for type
PCI/VPD: Correct diagnostic for VPD read failure
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:43 +0000 (14:56 -0500)]
Merge branch 'pci/virtualization'
- Add ACS quirks for NXP LX2xx0 and LX2xx2 platforms (Wasim Khan)
- Add ACS quirks for Cavium multi-function devices (George Cherian)
- Enforce pci=noats with Transaction Blocking (Alex Williamson)
* pci/virtualization:
PCI/ACS: Enforce pci=noats with Transaction Blocking
PCI: Add ACS quirks for Cavium multi-function devices
PCI: Add ACS quirks for NXP LX2xx0 and LX2xx2 platforms
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:43 +0000 (14:56 -0500)]
Merge branch 'pci/resource'
- Refactor pci_ioremap_bar() and pci_ioremap_wc_bar() (Krzysztof
Wilczyński)
- Optimize pci_resource_len() to reduce kernel size (Zhen Lei)
* pci/resource:
PCI: Optimize pci_resource_len() to reduce kernel size
PCI: Refactor pci_ioremap_bar() and pci_ioremap_wc_bar()
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:42 +0000 (14:56 -0500)]
Merge branch 'pci/reset'
- Cache PCIe Device Capabilities register (Amey Narkhede)
- Add pcie_reset_flr() with 'probe' argument (Amey Narkhede)
- Add pdev->reset_methods[] array to track reset method ordering (Amey
Narkhede)
- Remove reset_fn field from pci_dev (Amey Narkhede)
- Add sysfs interface to query and set device reset mechanism (Amey
Narkhede)
- Add pci_set_acpi_fwnode() to set ACPI_COMPANION (Shanker Donthineni)
- Use acpi_pci_power_manageable() instead of duplicating logic (Shanker
Donthineni)
- Set ACPI fwnode early and at the same time with OF (Shanker Donthineni)
- Add support for ACPI _RST reset method (Shanker Donthineni)
- Change reset function 'probe' argument to bool (Amey Narkhede)
* pci/reset:
PCI: Change the type of probe argument in reset functions
PCI: Add support for ACPI _RST reset method
PCI: Setup ACPI fwnode early and at the same time with OF
PCI: Use acpi_pci_power_manageable()
PCI: Add pci_set_acpi_fwnode() to set ACPI_COMPANION
PCI: Allow userspace to query and set device reset mechanism
PCI: Remove reset_fn field from pci_dev
PCI: Add array to track reset method ordering
PCI: Add pcie_reset_flr() with 'probe' argument
PCI: Cache PCIe Device Capabilities register
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:42 +0000 (14:56 -0500)]
Merge branch 'pci/portdrv'
- Enable Bandwidth Notification only if port supports it (Stuart Hayes)
* pci/portdrv:
PCI/portdrv: Enable Bandwidth Notification only if port supports it
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:42 +0000 (14:56 -0500)]
Merge branch 'pci/irq'
- Convert irq_find_mapping() + generic_handle_irq() to
generic_handle_domain_irq() (Marc Zyngier)
* pci/irq:
PCI: Bulk conversion to generic_handle_domain_irq()
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:41 +0000 (14:56 -0500)]
Merge branch 'pci/iommu'
- Allow PASID on fake PCIe devices, e.g., HiSilicon KunPeng920 and
KunPeng930 AMBA devices, without TLP prefixes (Zhangfei Gao)
- Allow SVA / dma-can-stall on fake PCIe devices (Zhangfei Gao)
* pci/iommu:
PCI: Set dma-can-stall for HiSilicon chips
PCI: Allow PASID on fake PCIe devices without TLP prefixes
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:41 +0000 (14:56 -0500)]
Merge branch 'pci/hotplug'
- Fix ibmphp double unmap of io_mem (Vishal Aslot)
* pci/hotplug:
PCI: ibmphp: Fix double unmap of io_mem
Bjorn Helgaas [Thu, 2 Sep 2021 19:56:40 +0000 (14:56 -0500)]
Merge branch 'pci/enumeration'
- Call Max Payload Size-related fixup quirks early, so they're considered
by pci_configure_mps() (Marek Behún)
- Restrict Max Payload Size Supported to work around ASMedia ASM1062 SATA
erratum (Marek Behún)
- Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure (Krzysztof
Wilczyński)
* pci/enumeration:
PCI: Return int from pciconfig_read() syscall
PCI: Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure
PCI: Restrict ASMedia ASM1062 SATA Max Payload Size Supported
PCI: Call Max Payload Size-related fixup quirks early
Vishal Aslot [Wed, 18 Aug 2021 16:57:51 +0000 (11:57 -0500)]
PCI: ibmphp: Fix double unmap of io_mem
ebda_rsrc_controller() calls iounmap(io_mem) on the error path. Its caller,
ibmphp_access_ebda(), also calls iounmap(io_mem) on good and error paths.
Remove the iounmap(io_mem) invocation from ebda_rsrc_controller().
[bhelgaas: remove item from TODO]
Link: https://lore.kernel.org/r/20210818165751.591185-1-os.vaslot@gmail.com
Signed-off-by: Vishal Aslot <os.vaslot@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Christophe JAILLET [Sun, 22 Aug 2021 18:49:20 +0000 (20:49 +0200)]
x86/PCI: sta2x11: switch from 'pci_' to 'dma_' API
The wrappers in include/linux/pci-dma-compat.h should go away.
The patch has been generated with the coccinelle script below.
It has been hand modified to use 'dma_set_mask_and_coherent()' instead of
'pci_set_dma_mask()/pci_set_consistent_dma_mask()' when applicable.
This is less verbose.
It has been compile tested.
@@
@@
- PCI_DMA_BIDIRECTIONAL
+ DMA_BIDIRECTIONAL
@@
@@
- PCI_DMA_TODEVICE
+ DMA_TO_DEVICE
@@
@@
- PCI_DMA_FROMDEVICE
+ DMA_FROM_DEVICE
@@
@@
- PCI_DMA_NONE
+ DMA_NONE
@@
expression e1, e2, e3;
@@
- pci_alloc_consistent(e1, e2, e3)
+ dma_alloc_coherent(&e1->dev, e2, e3, GFP_)
@@
expression e1, e2, e3;
@@
- pci_zalloc_consistent(e1, e2, e3)
+ dma_alloc_coherent(&e1->dev, e2, e3, GFP_)
@@
expression e1, e2, e3, e4;
@@
- pci_free_consistent(e1, e2, e3, e4)
+ dma_free_coherent(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
- pci_map_single(e1, e2, e3, e4)
+ dma_map_single(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
- pci_unmap_single(e1, e2, e3, e4)
+ dma_unmap_single(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4, e5;
@@
- pci_map_page(e1, e2, e3, e4, e5)
+ dma_map_page(&e1->dev, e2, e3, e4, e5)
@@
expression e1, e2, e3, e4;
@@
- pci_unmap_page(e1, e2, e3, e4)
+ dma_unmap_page(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
- pci_map_sg(e1, e2, e3, e4)
+ dma_map_sg(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
- pci_unmap_sg(e1, e2, e3, e4)
+ dma_unmap_sg(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
- pci_dma_sync_single_for_cpu(e1, e2, e3, e4)
+ dma_sync_single_for_cpu(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
- pci_dma_sync_single_for_device(e1, e2, e3, e4)
+ dma_sync_single_for_device(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
- pci_dma_sync_sg_for_cpu(e1, e2, e3, e4)
+ dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4)
@@
expression e1, e2, e3, e4;
@@
- pci_dma_sync_sg_for_device(e1, e2, e3, e4)
+ dma_sync_sg_for_device(&e1->dev, e2, e3, e4)
@@
expression e1, e2;
@@
- pci_dma_mapping_error(e1, e2)
+ dma_mapping_error(&e1->dev, e2)
@@
expression e1, e2;
@@
- pci_set_dma_mask(e1, e2)
+ dma_set_mask(&e1->dev, e2)
@@
expression e1, e2;
@@
- pci_set_consistent_dma_mask(e1, e2)
+ dma_set_coherent_mask(&e1->dev, e2)
Link: https://lore.kernel.org/r/99656452963ba3c63a6cb12e151279d81da365eb.1629658069.git.christophe.jaillet@wanadoo.fr
Link: https://lore.kernel.org/kernel-janitors/20200421081257.GA131897@infradead.org/
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Thu, 26 Aug 2021 18:58:07 +0000 (20:58 +0200)]
PCI/VPD: Use unaligned access helpers
Use unaligned access helpers to simplify the code.
Link: https://lore.kernel.org/r/0f1c7e21-5330-72ab-139d-f5ce3c65f04a@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Thu, 26 Aug 2021 18:57:01 +0000 (20:57 +0200)]
PCI/VPD: Clean up public VPD defines and inline functions
After recent introduction of new VPD API functions and user migration
these defines and inline functions aren't used outside VPD core any
longer.
Link: https://lore.kernel.org/r/d33e06bf-bc5e-ece7-bf35-7245ae224d1b@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Thu, 26 Aug 2021 18:56:22 +0000 (20:56 +0200)]
cxgb4: Use pci_vpd_find_id_string() to find VPD ID string
Use pci_vpd_find_id_string() to find the VPD ID string. This simplifies the
code and avoids the need for pci_vpd_lrdt_size().
Link: https://lore.kernel.org/r/19ea2e9b-6e94-288a-6612-88db01b1b417@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Thu, 26 Aug 2021 18:55:43 +0000 (20:55 +0200)]
PCI/VPD: Add pci_vpd_find_id_string()
Add a pci_vpd_find_id_string() API function to retrieve the ID string from
VPD.
This way callers don't need pci_vpd_lrdt_size() any longer, and it can be
made private to the VPD core.
Link: https://lore.kernel.org/r/c5225bf6-8d29-970d-e271-0d7b52252630@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Thu, 26 Aug 2021 18:55:07 +0000 (20:55 +0200)]
PCI/VPD: Include post-processing in pci_vpd_find_tag()
Move pci_vpd_find_tag() post-processing from pci_vpd_find_ro_info_keyword()
to pci_vpd_find_tag(). This simplifies function pci_vpd_find_id_string()
that will be added in a subsequent patch.
Link: https://lore.kernel.org/r/fb15393f-d3b2-e140-2643-570d3abd7382@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Thu, 26 Aug 2021 18:54:23 +0000 (20:54 +0200)]
PCI/VPD: Stop exporting pci_vpd_find_info_keyword()
Now that the last users have been migrated to pci_vpd_find_ro_keyword()
we can stop exporting this function. It's still used in VPD core code.
Link: https://lore.kernel.org/r/96ca2a56-383e-9b61-9cba-4f1e5611dc15@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Thu, 26 Aug 2021 18:53:42 +0000 (20:53 +0200)]
PCI/VPD: Stop exporting pci_vpd_find_tag()
Now that the last users have been migrated to pci_vpd_find_ro_keyword()
we can stop exporting this function. It's still used in VPD core code.
Link: https://lore.kernel.org/r/71131eca-0502-7878-365f-30b6614161cf@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Zhangfei Gao [Tue, 13 Jul 2021 02:54:36 +0000 (10:54 +0800)]
PCI: Set dma-can-stall for HiSilicon chips
HiSilicon KunPeng920 and KunPeng930 have devices that appear as PCI but are
actually on the AMBA bus. These fake PCI devices can support SVA via the
SMMU stall feature.
DT systems can indicate this in the device tree, but ACPI systems don't
have that mechanism, so add a "dma-can-stall" property manually for them.
[bhelgaas: add text from Robin as comment near quirk]
Link: https://lore.kernel.org/r/1626144876-11352-4-git-send-email-zhangfei.gao@linaro.org
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Simon Xue [Fri, 25 Jun 2021 06:55:11 +0000 (14:55 +0800)]
PCI: rockchip-dwc: Add Rockchip RK356X host controller driver
Add a driver for the DesignWare-based PCIe controller found on
RK356X. The existing pcie-rockchip-host driver is only used for
the Rockchip-designed IP found on RK3399.
Link: https://lore.kernel.org/r/20210625065511.1096935-1-xxm@rock-chips.com
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Krzysztof Wilczyński [Thu, 1 Jul 2021 21:02:52 +0000 (21:02 +0000)]
PCI: dwc: Remove surplus break statement after return
As part of code refactoring completed in
a0fd361db8e5 ("PCI: dwc: Move
"dbi", "dbi2", and "addr_space" resource setup into common code"),
dw_plat_add_pcie_ep() was removed and the call to the dw_pcie_ep_init() was
moved into dw_plat_pcie_probe().
This left a break statement behind that is not needed any more as as
dw_plat_pcie_probe() returns immediately after calling dw_pcie_ep_init().
Remove this surplus break statement that became dead code.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20210701210252.1638709-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Krzysztof Wilczyński [Thu, 1 Jul 2021 20:44:01 +0000 (20:44 +0000)]
PCI: artpec6: Remove local code block from switch statement
The switch statement in the artpec6_pcie_probe() has a local code block
where "val" is defined and immediately used by the artpec6_pcie_readl().
This extra code block adds brackets at the same indentation level as the
switch statement itself which can hinder readability of the code.
Move the "val" declaration to the top of the function and remove
the extra code block from the switch statement.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20210701204401.1636562-2-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Krzysztof Wilczyński [Thu, 1 Jul 2021 20:44:00 +0000 (20:44 +0000)]
PCI: artpec6: Remove surplus break statement after return
As part of code refactoring completed in
a0fd361db8e5 ("PCI: dwc: Move
"dbi", "dbi2", and "addr_space" resource setup into common code"),
artpec6_add_pcie_ep() was removed and the call to the dw_pcie_ep_init()
was moved into artpec6_pcie_probe().
This left a break statement behind that is not needed any more as
artpec6_pcie_probe() returns immediately after calling dw_pcie_ep_init().
Remove this surplus break statement that became dead code.
Link: https://lore.kernel.org/r/20210701204401.1636562-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Nobuhiro Iwamatsu [Wed, 11 Aug 2021 08:38:30 +0000 (17:38 +0900)]
MAINTAINERS: Add entries for Toshiba Visconti PCIe controller
Add entries for Toshiba Visconti PCIe controller binding and driver.
Link: https://lore.kernel.org/r/20210811083830.784065-4-nobuhiro1.iwamatsu@toshiba.co.jp
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Nobuhiro Iwamatsu [Wed, 11 Aug 2021 08:38:29 +0000 (17:38 +0900)]
PCI: visconti: Add Toshiba Visconti PCIe host controller driver
Add support for the PCIe RC controller on Toshiba Visconti ARM SoCs. This
PCIe controller is based on the Synopsys DesignWare PCIe core.
Link: https://lore.kernel.org/r/20210811083830.784065-3-nobuhiro1.iwamatsu@toshiba.co.jp
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Stuart Hayes [Wed, 12 May 2021 21:33:14 +0000 (03:03 +0530)]
PCI/portdrv: Enable Bandwidth Notification only if port supports it
Previously we assumed that all Root Ports and Switch Downstream Ports
supported Link Bandwidth Notification. Per spec, this is only required
for Ports supporting Links wider than x1 and/or multiple Link speeds
(PCIe r5.0, sec 7.5.3.6).
Because we assumed all Ports supported it, we tried to set up a Bandwidth
Notification IRQ, which failed for devices that don't support IRQs at all,
which meant pcieport didn't attach to the Port at all.
Check the Link Bandwidth Notification Capability bit and enable the service
only when the Port supports it.
[bhelgaas: commit log]
Fixes:
e8303bb7a75c ("PCI/LINK: Report degraded links via link bandwidth notification")
Link: https://lore.kernel.org/r/20210512213314.7778-1-stuart.w.hayes@gmail.com
Signed-off-by: Stuart Hayes <stuart.w.hayes@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lukas Wunner <lukas@wunner.de>
Cc: stable@vger.kernel.org
Zhangfei Gao [Tue, 13 Jul 2021 02:54:34 +0000 (10:54 +0800)]
PCI: Allow PASID on fake PCIe devices without TLP prefixes
Some systems, e.g., HiSilicon KunPeng920 and KunPeng930, have devices that
appear as PCI but are actually on the AMBA bus. Some of these fake PCI
devices support a PASID-like feature and they do have a working PASID
capability even though they do not use the PCIe Transport Layer Protocol
and do not support TLP prefixes.
Add a pasid_no_tlp bit for this "PASID works without TLP prefixes" case and
update pci_enable_pasid() so it can enable PASID on these devices.
Set this bit for HiSilicon KunPeng920 and KunPeng930.
[bhelgaas: squashed, commit log]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/1626144876-11352-2-git-send-email-zhangfei.gao@linaro.org
Link: https://lore.kernel.org/r/1626144876-11352-3-git-send-email-zhangfei.gao@linaro.org
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Chuanjia Liu [Mon, 23 Aug 2021 03:27:58 +0000 (11:27 +0800)]
PCI: mediatek: Use PCI domain to handle ports detection
Use of_get_pci_domain_nr() to get the pci domain.
If the "linux,pci-domain" property is present, we assume that the PCIe
bridge is an individual bridge, hence we only need to parse one port.
Link: https://lore.kernel.org/r/20210823032800.1660-5-chuanjia.liu@mediatek.com
Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Chuanjia Liu [Mon, 23 Aug 2021 03:27:57 +0000 (11:27 +0800)]
PCI: mediatek: Add new method to get irq number
Use platform_get_irq_byname() to get the irq number
if the "interrupt-names" property is defined.
Link: https://lore.kernel.org/r/20210823032800.1660-4-chuanjia.liu@mediatek.com
Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Chuanjia Liu [Mon, 23 Aug 2021 03:27:56 +0000 (11:27 +0800)]
PCI: mediatek: Add new method to get shared pcie-cfg base address
For the new dts format, add a new method to get
shared pcie-cfg base address and use it to configure
the PCIECFG controller
Link: https://lore.kernel.org/r/20210823032800.1660-3-chuanjia.liu@mediatek.com
Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Chuanjia Liu [Mon, 23 Aug 2021 03:27:55 +0000 (11:27 +0800)]
dt-bindings: PCI: mediatek: Update the Device tree bindings
There are two independent PCIe controllers in MT2712 and MT7622
platform. Each of them should contain an independent MSI domain.
In old dts architecture, MSI domain will be inherited from the root
bridge, and all of the devices will share the same MSI domain.
Hence that, the PCIe devices will not work properly if the irq number
which required is more than 32.
Split the PCIe node for MT2712 and MT7622 platform to comply with
the hardware design and fix MSI issue.
Link: https://lore.kernel.org/r/20210823032800.1660-2-chuanjia.liu@mediatek.com
Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh+dt@kernel.org>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Pali Rohár [Fri, 20 Aug 2021 15:50:20 +0000 (17:50 +0200)]
PCI: aardvark: Fix masking and unmasking legacy INTx interrupts
irq_mask and irq_unmask callbacks need to be properly guarded by raw spin
locks as masking/unmasking procedure needs atomic read-modify-write
operation on hardware register.
Link: https://lore.kernel.org/r/20210820155020.3000-1-pali@kernel.org
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Heiner Kallweit [Sun, 22 Aug 2021 14:01:08 +0000 (16:01 +0200)]
scsi: cxlflash: Search VPD with pci_vpd_find_ro_info_keyword()
Use pci_vpd_find_ro_info_keyword() to search for keywords in VPD to
simplify the code.
Link: https://lore.kernel.org/r/b5f71c97-61fb-86cb-6bec-84b042392ce7@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:59:21 +0000 (15:59 +0200)]
cxgb4: Search VPD with pci_vpd_find_ro_info_keyword()
Use pci_vpd_find_ro_info_keyword() to search for keywords in VPD to
simplify the code.
Link: https://lore.kernel.org/r/db576a3e-e877-b37b-98ed-cfc03d225ab3@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:58:26 +0000 (15:58 +0200)]
cxgb4: Remove unused vpd_param member ec
Member ec isn't used, so remove it.
Link: https://lore.kernel.org/r/30648e95-bfb9-9af3-0c8f-dd3e34df8b6b@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:57:27 +0000 (15:57 +0200)]
cxgb4: Validate VPD checksum with pci_vpd_check_csum()
Validate the VPD checksum with pci_vpd_check_csum() to simplify the code.
Link: https://lore.kernel.org/r/70404ece-0036-c0ce-f824-f5637e54115e@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:56:24 +0000 (15:56 +0200)]
bnxt: Search VPD with pci_vpd_find_ro_info_keyword()
Use pci_vpd_find_ro_info_keyword() to search for keywords in VPD to
simplify the code.
Link: https://lore.kernel.org/r/f062921c-ad33-3b3e-8ada-b53427a9cd4a@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:55:23 +0000 (15:55 +0200)]
bnxt: Read VPD with pci_vpd_alloc()
Use pci_vpd_alloc() to dynamically allocate a properly sized buffer and
read the full VPD data into it.
This simplifies the code, and we no longer have to make assumptions about
VPD size.
Link: https://lore.kernel.org/r/62522a24-f39a-2b35-1577-1fbb41695bed@gmail.com
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:54:23 +0000 (15:54 +0200)]
bnx2x: Search VPD with pci_vpd_find_ro_info_keyword()
Use pci_vpd_find_ro_info_keyword() to search for keywords in VPD to
simplify the code.
Use strncasecmp() to match Vendor ID instead of comparing with lower- and
upper-case hex string.
[bhelgaas: convert to strncasecmp()]
Link: https://lore.kernel.org/r/a9f730cf-e31e-902b-7b39-0ff2e99636e0@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:53:23 +0000 (15:53 +0200)]
bnx2x: Read VPD with pci_vpd_alloc()
Use pci_vpd_alloc() to dynamically allocate a properly sized buffer and
read the full VPD data into it.
This simplifies the code, and we no longer have to make assumptions about
VPD size.
Link: https://lore.kernel.org/r/821a334d-ff9d-386e-5f42-9b620ab3dbfa@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:52:01 +0000 (15:52 +0200)]
bnx2: Replace open-coded byte swapping with swab32s()
Read NVRAM directly into buffer and use swab32s() to byte swap it in-place
instead of reading it into the end of the buffer and swapping it manually
while copying it.
[bhelgaas: commit log]
Link: https://lore.kernel.org/r/e4ac6229-1df5-8760-3a87-1ad0ace87137@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:50:50 +0000 (15:50 +0200)]
bnx2: Search VPD with pci_vpd_find_ro_info_keyword()
Use pci_vpd_find_ro_info_keyword() to search for keywords in VPD to
simplify the code.
Link: https://lore.kernel.org/r/7ca2b8b5-4c94-f644-1d80-b2ffb8df2d05@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:49:36 +0000 (15:49 +0200)]
sfc: falcon: Search VPD with pci_vpd_find_ro_info_keyword()
Use pci_vpd_find_ro_info_keyword() to search for keywords in VPD to
simplify the code.
Replace netif_err() with pci_err() because the netdevice isn't registered
yet, which results in very ugly messages.
Use kmemdup_nul() instead of open-coding it.
This is the same as
37838aa437c7 ("sfc: Search VPD with
pci_vpd_find_ro_info_keyword()"), just for the falcon chip version.
Link: https://lore.kernel.org/r/898282a1-13bd-17bc-2e9a-d3dcd336b46c@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Sun, 22 Aug 2021 13:48:33 +0000 (15:48 +0200)]
sfc: falcon: Read VPD with pci_vpd_alloc()
Use pci_vpd_alloc() to dynamically allocate a properly sized buffer and
read the full VPD data into it.
This avoids having to allocate a buffer on the stack, and we don't have to
make any assumptions on VPD size and location of information in VPD.
This is the same as
5119e20facfa ("sfc: Read VPD with pci_vpd_alloc()"),
just for the falcon chip version.
Link: https://lore.kernel.org/r/2a8d069e-9516-50d8-6520-2614222c8f5f@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Boqun Feng [Mon, 26 Jul 2021 18:06:57 +0000 (02:06 +0800)]
PCI: hv: Turn on the host bridge probing on ARM64
Now we have everything we need, just provide a proper sysdata type for
the bus to use on ARM64 and everything else works.
Link: https://lore.kernel.org/r/20210726180657.142727-9-boqun.feng@gmail.com
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Boqun Feng [Mon, 26 Jul 2021 18:06:56 +0000 (02:06 +0800)]
PCI: hv: Set up MSI domain at bridge probing time
Since PCI_HYPERV depends on PCI_MSI_IRQ_DOMAIN which selects
GENERIC_MSI_IRQ_DOMAIN, we can use dev_set_msi_domain() to set up the
MSI domain at probing time, and this works for both x86 and ARM64.
Therefore use it as the preparation for ARM64 Hyper-V PCI support.
As a result, no longer need to maintain ->fwnode in x86 specific
pci_sysdata, and make hv_pcibus_device own it instead.
Link: https://lore.kernel.org/r/20210726180657.142727-8-boqun.feng@gmail.com
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Boqun Feng [Mon, 26 Jul 2021 18:06:55 +0000 (02:06 +0800)]
PCI: hv: Set ->domain_nr of pci_host_bridge at probing time
No functional change, just store and maintain the PCI domain number in
the ->domain_nr of pci_host_bridge. Note that we still need to keep
the copy of domain number in x86-specific pci_sysdata, because x86 is
not a PCI_DOMAINS_GENERIC=y architecture, so the ->domain_nr of
pci_host_bridge doesn't work for it yet.
Link: https://lore.kernel.org/r/20210726180657.142727-7-boqun.feng@gmail.com
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Arnd Bergmann [Mon, 26 Jul 2021 18:06:54 +0000 (02:06 +0800)]
PCI: hv: Generify PCI probing
In order to support ARM64 Hyper-V PCI, we need to set up the bridge at
probing time because ARM64 is a PCI_DOMAIN_GENERIC=y arch and we don't
have pci_config_window (ARM64 sysdata) for a PCI root bus on Hyper-V, so
it's impossible to retrieve the information (e.g. PCI domains, MSI
domains) from bus sysdata on ARM64 after creation.
Originally in create_root_hv_pci_bus(), pci_create_root_bus() is used to
create the root bus and the corresponding bridge based on x86 sysdata.
Now we create a bridge first and then call pci_scan_root_bus_bridge(),
which allows us to do the necessary set-ups for the bridge.
Link: https://lore.kernel.org/r/20210726180657.142727-6-boqun.feng@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Boqun Feng [Mon, 26 Jul 2021 18:06:53 +0000 (02:06 +0800)]
arm64: PCI: Support root bridge preparation for Hyper-V
Currently at root bridge preparation, the corresponding ACPI device will
be set as the companion, however for a Hyper-V virtual PCI root bridge,
there is no corresponding ACPI device, because a Hyper-V virtual PCI
root bridge is discovered via VMBus rather than ACPI table. In order to
support this, we need to make pcibios_root_bridge_prepare() work with
cfg->parent being NULL.
Use a NULL pointer as the ACPI device if there is no corresponding ACPI
device, and this is fine because: 1) ACPI_COMPANION_SET() can work with
the second parameter being NULL, 2) semantically, if a NULL pointer is
set via ACPI_COMPANION_SET(), ACPI_COMPANION() (the read API for this
field) will return NULL, and since ACPI_COMPANION() may return NULL, so
users must have handled the cases where it returns NULL, and 3) since
there is no corresponding ACPI device, it would be wrong to use any
other value here.
Link: https://lore.kernel.org/r/20210726180657.142727-5-boqun.feng@gmail.com
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Boqun Feng [Mon, 26 Jul 2021 18:06:52 +0000 (02:06 +0800)]
arm64: PCI: Restructure pcibios_root_bridge_prepare()
Restructure the pcibios_root_bridge_prepare() as the preparation for
supporting cases when no real ACPI device is related to the PCI host
bridge.
No functional change.
Link: https://lore.kernel.org/r/20210726180657.142727-4-boqun.feng@gmail.com
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Boqun Feng [Mon, 26 Jul 2021 18:06:51 +0000 (02:06 +0800)]
PCI: Support populating MSI domains of root buses via bridges
Currently, at probing time, the MSI domains of root buses are populated
if either the information of MSI domain is available from firmware (DT
or ACPI), or arch-specific sysdata is used to pass the fwnode of the MSI
domain. These two conditions don't cover all, e.g. Hyper-V virtual PCI
on ARM64, which doesn't have the MSI information in the firmware and
couldn't use arch-specific sysdata because running on an architecture
with PCI_DOMAINS_GENERIC=y.
To support populating MSI domains of the root buses at the probing when
neither of the above condition is true, the ->msi_domain of the
corresponding bridge device is used: in pci_host_bridge_msi_domain(),
which should return the MSI domain of the root bus, the ->msi_domain of
the corresponding bridge is fetched first as a potential value of the
MSI domain of the root bus.
In order to use the approach to populate MSI domains, the driver needs
to dev_set_msi_domain() on the bridge before calling
pci_register_host_bridge(), and makes sure GENERIC_MSI_IRQ_DOMAIN=y.
Another advantage of this new approach is providing an arch-independent
way to populate MSI domains, which allows sharing the driver code as
much as possible between architectures.
Originally-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210726180657.142727-3-boqun.feng@gmail.com
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Boqun Feng [Mon, 26 Jul 2021 18:06:50 +0000 (02:06 +0800)]
PCI: Introduce domain_nr in pci_host_bridge
Currently we retrieve the PCI domain number of the host bridge from the
bus sysdata (or pci_config_window if PCI_DOMAINS_GENERIC=y). Actually
we have the information at PCI host bridge probing time, and it makes
sense that we store it into pci_host_bridge. One benefit of doing so is
the requirement for supporting PCI on Hyper-V for ARM64, because the
host bridge of Hyper-V doesn't have pci_config_window, whereas ARM64 is
a PCI_DOMAINS_GENERIC=y arch, so we cannot retrieve the PCI domain
number from pci_config_window on ARM64 Hyper-V guest.
As the preparation for ARM64 Hyper-V PCI support, we introduce the
domain_nr in pci_host_bridge and a sentinel value to allow drivers to
set domain numbers properly at probing time. Currently
CONFIG_PCI_DOMAINS_GENERIC=y archs are only users of this
newly-introduced field.
Link: https://lore.kernel.org/r/20210726180657.142727-2-boqun.feng@gmail.com
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Andy Shevchenko [Fri, 13 Aug 2021 15:36:19 +0000 (18:36 +0300)]
PCI: Sync __pci_register_driver() stub for CONFIG_PCI=n
The CONFIG_PCI=y case got a new parameter long time ago. Sync the stub as
well.
[bhelgaas: add parameter names]
Fixes:
725522b5453d ("PCI: add the sysfs driver name to all modules")
Link: https://lore.kernel.org/r/20210813153619.89574-1-andriy.shevchenko@linux.intel.com
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Zhen Lei [Tue, 13 Jul 2021 07:22:36 +0000 (15:22 +0800)]
PCI: Optimize pci_resource_len() to reduce kernel size
pci_resource_end() can be 0 only when pci_resource_start() is 0.
Otherwise, it is definitely an error. In this case, pci_resource_len()
should be regarded as 0. Therefore, determining whether
pci_resource_start() and pci_resource_end() are both 0 can be reduced to
determining only whether pci_resource_end() is 0.
Although only one condition judgment is reduced, the macro function
pci_resource_len() is widely referenced in the kernel. I used defconfig to
compile the latest kernel on X86, and its binary code size was reduced by
about 3KB.
Before:
[ 2] .rela.text RELA
0000000000000000 093bfcb0
0000000001a67168 0000000000000018 I 68 1 8
After:
[ 2] .rela.text RELA
0000000000000000 093bfcb0
0000000001a66598 0000000000000018 I 68 1 8
Link: https://lore.kernel.org/r/20210713072236.3043-1-thunder.leizhen@huawei.com
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Mon, 2 Aug 2021 22:17:28 +0000 (17:17 -0500)]
PCI: Make saved capability state private to core
Interfaces and structs for saving and restoring PCI Capability state were
declared in include/linux/pci.h, but aren't needed outside drivers/pci/.
Move these to drivers/pci/pci.h:
struct pci_cap_saved_data
struct pci_cap_saved_state
void pci_allocate_cap_save_buffers()
void pci_free_cap_save_buffers()
int pci_add_cap_save_buffer()
int pci_add_ext_cap_save_buffer()
struct pci_cap_saved_state *pci_find_saved_cap()
struct pci_cap_saved_state *pci_find_saved_ext_cap()
Link: https://lore.kernel.org/r/20210802221728.1469304-1-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Krzysztof Wilczyński [Sun, 15 Aug 2021 15:08:24 +0000 (15:08 +0000)]
PCI: Add schedule point in proc_bus_pci_read()
PCI configuration space reads from /proc/bus/pci can often take several
milliseconds to complete.
Add a schedule point in proc_bus_pci_read() to reduce the maximum latency.
A similar change was made for sysfs by
2ce02a864ac1 ("PCI: Add schedule
point in pci_read_config()").
Link: https://lore.kernel.org/r/20200824052025.48362-1-benbjiang@tencent.com
Link: https://lore.kernel.org/r/20210815150824.96773-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jonathan Cameron [Tue, 3 Aug 2021 12:30:14 +0000 (20:30 +0800)]
PCI: Correct the pci_iomap.h header guard #endif comment
Update the include/asm-generic/pci_iomap.h header guard #endif comment to
match the corresponding #ifndef.
Link: https://lore.kernel.org/r/20210803123014.2963814-1-Jonathan.Cameron@huawei.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Alex Williamson [Fri, 18 Jun 2021 20:55:14 +0000 (14:55 -0600)]
PCI/ACS: Enforce pci=noats with Transaction Blocking
PCIe Address Translation Services (ATS) provides a mechanism for a device
to provide an on-device caching translation agent (device IOTLB). We
already have a means to disable support for this feature via the pci=noats
option. For untrusted and externally facing devices, we not only disable
ATS support for the device, but we use Access Control Services (ACS)
Transaction Blocking to actively prevent devices from sending TLPs with
non-default AT field values.
Extend pci=noats to also make use of PCI_ACS_TB so that not only is ATS
disabled at the device, but blocked at the downstream ports. This provides
a means to further lock-down ATS for cases such as device assignment, where
it may not be the hardware configuration of the device that makes it
untrusted, but the driver running on the device.
Link: https://lore.kernel.org/r/162404966325.2362347.12176138291577486015.stgit@omen
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rajat Jain <rajatja@google.com>
George Cherian [Tue, 10 Aug 2021 12:24:25 +0000 (17:54 +0530)]
PCI: Add ACS quirks for Cavium multi-function devices
Some Cavium endpoints are implemented as multi-function devices without ACS
capability, but they actually don't support peer-to-peer transactions.
Add ACS quirks to declare DMA isolation for the following devices:
- BGX device found on Octeon-TX (8xxx)
- CGX device found on Octeon-TX2 (9xxx)
- RPM device found on Octeon-TX3 (10xxx)
Link: https://lore.kernel.org/r/20210810122425.1115156-1-george.cherian@marvell.com
Signed-off-by: George Cherian <george.cherian@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jakub Kicinski [Wed, 11 Aug 2021 18:59:55 +0000 (11:59 -0700)]
PCI/PTM: Remove error message at boot
Since
39850ed51062 ("PCI/PTM: Save/restore Precision Time Measurement
Capability for suspend/resume"), devices that have PTM capability but
don't enable it see this message on calls to pci_save_state():
no suspend buffer for PTM
Drop the message, it's perfectly fine not to use a capability.
Fixes:
39850ed51062 ("PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume")
Link: https://lore.kernel.org/r/20210811185955.3112534-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David E. Box <david.e.box@linux.intel.com>
Heiner Kallweit [Wed, 18 Aug 2021 19:06:40 +0000 (21:06 +0200)]
tg3: Search VPD with pci_vpd_find_ro_info_keyword()
Use pci_vpd_find_ro_info_keyword() to search for keywords in VPD to
simplify the code.
Link: https://lore.kernel.org/r/0ae9d4c0-590d-682a-a0af-2272e5f71630@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Wed, 18 Aug 2021 19:05:26 +0000 (21:05 +0200)]
tg3: Validate VPD checksum with pci_vpd_check_csum()
Validate the VPD checksum with pci_vpd_check_csum() to simplify the code.
Link: https://lore.kernel.org/r/7297fce9-47db-3b86-366e-10b9ef43beaf@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Wed, 18 Aug 2021 19:04:37 +0000 (21:04 +0200)]
tg3: Read VPD with pci_vpd_alloc()
Use pci_vpd_alloc() to dynamically allocate a properly sized buffer and
read the full VPD data into it.
This simplifies the code, and we no longer have to make assumptions about
VPD size.
Link: https://lore.kernel.org/r/bd3cd19c-b74f-9704-5786-476bf35ab5de@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Wed, 18 Aug 2021 19:03:44 +0000 (21:03 +0200)]
sfc: Search VPD with pci_vpd_find_ro_info_keyword()
Use pci_vpd_find_ro_info_keyword() to search for keywords in VPD to
simplify the code.
Replace netif_err() with pci_err() because the netdevice isn't registered
yet, which results in very ugly messages.
Use kmemdup_nul() instead of open-coding it.
Link: https://lore.kernel.org/r/bf5d4ba9-61a9-2bfe-19ec-75472732d74d@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Wed, 18 Aug 2021 19:02:33 +0000 (21:02 +0200)]
sfc: Read VPD with pci_vpd_alloc()
Use pci_vpd_alloc() to dynamically allocate a properly sized buffer and
read the full VPD data into it.
This avoids having to allocate a buffer on the stack, and we don't have to
make any assumptions on VPD size and location of information in VPD.
Link: https://lore.kernel.org/r/e58f1e40-c043-0266-9a0f-e5a7f3f6883c@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Fri, 20 Aug 2021 20:32:42 +0000 (15:32 -0500)]
PCI/VPD: Add pci_vpd_check_csum()
VPD checksum information and checksum calculation are specified by PCIe
r5.0, sec 6.28.2.2. Therefore checksum handling can and should be moved
into the PCI VPD core.
Add pci_vpd_check_csum() to validate the VPD checksum.
[bhelgaas: split to separate patch]
Link: https://lore.kernel.org/r/1643bd7a-088e-1028-c9b0-9d112cf48d63@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Wed, 18 Aug 2021 19:00:57 +0000 (21:00 +0200)]
PCI/VPD: Add pci_vpd_find_ro_info_keyword()
All users of pci_vpd_find_info_keyword() are interested in the VPD RO
section only. In addition all calls are followed by the same activities to
calculate start of tag data area and size of the data area.
Add pci_vpd_find_ro_info_keyword() that combines these functionalities.
pci_vpd_find_info_keyword() can be phased out once all users are converted.
[bhelgaas: split pci_vpd_check_csum() to separate patch]
Link: https://lore.kernel.org/r/1643bd7a-088e-1028-c9b0-9d112cf48d63@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Wed, 18 Aug 2021 18:59:31 +0000 (20:59 +0200)]
PCI/VPD: Add pci_vpd_alloc()
Several users of the VPD API use a fixed-size buffer and read the VPD into
it for further usage. This requires special handling for the case that the
buffer isn't big enough to hold the full VPD data. Also the buffer is
often allocated on the stack, which isn't too nice.
Add pci_vpd_alloc() to dynamically allocate buffer of the correct size and
read VPD into it.
Link: https://lore.kernel.org/r/955ff598-0021-8446-f856-0c2c077635d7@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Srikanth Thokala [Thu, 5 Aug 2021 21:10:10 +0000 (02:40 +0530)]
PCI: keembay: Add support for Intel Keem Bay
Add driver for Intel Keem Bay SoC PCIe controller. This controller
is based on DesignWare PCIe core.
In Root Complex mode, only internal reference clock is possible for
Keem Bay A0. For Keem Bay B0, external reference clock can be used
and will be the default configuration. Currently, keembay_pcie_of_data
structure has one member. It will be expanded later to handle this
difference.
Endpoint mode link initialization is handled by the boot firmware.
Link: https://lore.kernel.org/r/20210805211010.29484-3-srikanth.thokala@intel.com
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Signed-off-by: Srikanth Thokala <srikanth.thokala@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Srikanth Thokala [Thu, 5 Aug 2021 21:10:09 +0000 (02:40 +0530)]
dt-bindings: PCI: Add Intel Keem Bay PCIe controller
Document DT bindings for PCIe controller found on Intel Keem Bay SoC.
Link: https://lore.kernel.org/r/20210805211010.29484-2-srikanth.thokala@intel.com
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Signed-off-by: Srikanth Thokala <srikanth.thokala@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Pali Rohár [Thu, 24 Jun 2021 21:55:45 +0000 (23:55 +0200)]
PCI: aardvark: Configure PCIe resources from 'ranges' DT property
In commit
6df6ba974a55 ("PCI: aardvark: Remove PCIe outbound window
configuration") was removed aardvark PCIe outbound window configuration and
commit description said that was recommended solution by HW designers.
But that commit completely removed support for configuring PCIe IO
resources without removing PCIe IO 'ranges' from DTS files. After that
commit PCIe IO space started to be treated as PCIe MEM space and accessing
it just caused kernel crash.
Moreover implementation of PCIe outbound windows prior that commit was
incorrect. It completely ignored offset between CPU address and PCIe bus
address and expected that in DTS is CPU address always same as PCIe bus
address without doing any checks. Also it completely ignored size of every
PCIe resource specified in 'ranges' DTS property and expected that every
PCIe resource has size 128 MB (also for PCIe IO range). Again without any
check. Apparently none of PCIe resource has in DTS specified size of 128
MB. So it was completely broken and thanks to how aardvark mask works,
configuration was completely ignored.
This patch reverts back support for PCIe outbound window configuration but
implementation is a new without issues mentioned above. PCIe outbound
window is required when DTS specify in 'ranges' property non-zero offset
between CPU and PCIe address space. To address recommendation by HW
designers as specified in commit description of
6df6ba974a55, set default
outbound parameters as PCIe MEM access without translation and therefore
for this PCIe 'ranges' it is not needed to configure PCIe outbound window.
For PCIe IO space is needed to configure aardvark PCIe outbound window.
This patch fixes kernel crash when trying to access PCIe IO space.
Link: https://lore.kernel.org/r/20210624215546.4015-2-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org # 6df6ba974a55 ("PCI: aardvark: Remove PCIe outbound window configuration")
Kishon Vijay Abraham I [Wed, 11 Aug 2021 12:33:36 +0000 (18:03 +0530)]
misc: pci_endpoint_test: Add deviceID for AM64 and J7200
Add device ID specific to AM64 and J7200 in pci_endpoint_test so that
endpoints configured with those deviceIDs can use pci_endpoint_test
driver.
Link: https://lore.kernel.org/r/20210811123336.31357-6-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Wed, 11 Aug 2021 12:33:35 +0000 (18:03 +0530)]
PCI: j721e: Add PCIe support for AM64
AM64 has the same PCIe IP as in J7200 with certain erratas not
applicable (quirk_detect_quiet_flag). Add support for "ti,am64-pcie-host"
compatible and "ti,am64-pcie-ep" compatible that is specific to AM64.
Link: https://lore.kernel.org/r/20210811123336.31357-5-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Wed, 11 Aug 2021 12:33:34 +0000 (18:03 +0530)]
PCI: j721e: Add PCIe support for J7200
J7200 has the same PCIe IP as in J721E with minor changes in the
wrapper. J7200 allows byte access of bridge configuration space
registers and the register field for LINK_DOWN interrupt is different.
J7200 also requires "quirk_detect_quiet_flag" to be set. Configure these
changes as part of driver data applicable only to J7200.
Link: https://lore.kernel.org/r/20210811123336.31357-4-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Nadeem Athani [Wed, 11 Aug 2021 12:33:33 +0000 (18:03 +0530)]
PCI: cadence: Add quirk flag to set minimum delay in LTSSM Detect.Quiet state
PCIe fails to link up if SERDES lanes not used by PCIe are assigned to
another protocol. For example, link training fails if lanes 2 and 3 are
assigned to another protocol while lanes 0 and 1 are used for PCIe to
form a two lane link. This failure is due to an incorrect tie-off on an
internal status signal indicating electrical idle.
Status signals going from SERDES to PCIe Controller are tied-off when a
lane is not assigned to PCIe. Signal indicating electrical idle is
incorrectly tied-off to a state that indicates non-idle. As a result,
PCIe sees unused lanes to be out of electrical idle and this causes
LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to
occur. If a receiver is not detected on the first receiver detection
attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and
again moves forward to Detect.Active state without waiting for 12ms as
required by PCIe base specification. Since wait time in Detect.Quiet is
skipped, multiple receiver detect operations are performed back-to-back
without allowing time for capacitance on the transmit lines to
discharge. This causes subsequent receiver detection to always fail even
if a receiver gets connected eventually.
Add a quirk flag "quirk_detect_quiet_flag" to program the minimum
time the LTSSM should wait on entering Detect.Quiet state here.
This has to be set for J7200 as it has an incorrect tie-off on unused
lanes.
Link: https://lore.kernel.org/r/20210811123336.31357-3-kishon@ti.com
Signed-off-by: Nadeem Athani <nadeem@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Wed, 11 Aug 2021 12:33:32 +0000 (18:03 +0530)]
PCI: cadence: Use bitfield for *quirk_retrain_flag* instead of bool
No functional change. As we are intending to add additional 1-bit
members in struct j721e_pcie_data/struct cdns_pcie_rc, use bitfields
instead of bool since it takes less space. As discussed in [1],
the preference is to use bitfileds instead of bool inside structures.
[1] -> https://lore.kernel.org/linux-fsdevel/CA+55aFzKQ6Pj18TB8p4Yr0M4t+S+BsiHH=BJNmn=76-NcjTj-g@mail.gmail.com/
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20210811123336.31357-2-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Thu, 19 Aug 2021 12:33:43 +0000 (18:03 +0530)]
Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV
Add Documentation to help users use PCI endpoint to create virtual
functions using configfs. An endpoint function is designated as a
virtual endpoint function device when it is linked to a physical
endpoint function device (instead of a endpoint controller).
Link: https://lore.kernel.org/r/20210819123343.1951-9-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Thu, 19 Aug 2021 12:33:42 +0000 (18:03 +0530)]
misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device
Populate sriov_configure ops with pci_sriov_configure_simple to
configure SR-IOV device.
Link: https://lore.kernel.org/r/20210819123343.1951-8-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Thu, 19 Aug 2021 12:33:41 +0000 (18:03 +0530)]
PCI: cadence: Add support to configure virtual functions
Now that support for SR-IOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.
Link: https://lore.kernel.org/r/20210819123343.1951-7-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Thu, 19 Aug 2021 12:33:40 +0000 (18:03 +0530)]
PCI: cadence: Simplify code to get register base address for configuring BAR
No functional change. Simplify code to get register base address for
configuring PCI BAR.
Link: https://lore.kernel.org/r/20210819123343.1951-6-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Thu, 19 Aug 2021 12:33:39 +0000 (18:03 +0530)]
PCI: endpoint: Add virtual function number in pci_epc ops
Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.
Link: https://lore.kernel.org/r/20210819123343.1951-5-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Thu, 19 Aug 2021 12:33:38 +0000 (18:03 +0530)]
PCI: endpoint: Add support to link a physical function to a virtual function
While the physical function has to be linked to endpoint controller, the
virtual function has to be linked to a physical function. Add support to
link a physical function to a virtual function in pci-ep-cfs.
Link: https://lore.kernel.org/r/20210819123343.1951-4-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>