Lei Huang [Mon, 19 Mar 2018 18:52:20 +0000 (18:52 +0000)]
[PowerPC][Power9]Legalize and emit code for quad-precision add/div/mul/sub
Legalize and emit code for quad-precision floating point operations:
* xsaddqp
* xssubqp
* xsdivqp
* xsmulqp
Differential Revision: https://reviews.llvm.org/D44506
llvm-svn: 327878
Nemanja Ivanovic [Mon, 19 Mar 2018 18:50:02 +0000 (18:50 +0000)]
[PowerPC] Make AddrSpaceCast noop
PowerPC targets do not use address spaces. As a result, we can get selection
failures with address space casts. This patch makes those casts noops.
Patch by Valentin Churavy.
Differential revision: https://reviews.llvm.org/D43781
llvm-svn: 327877
Vitaly Buka [Mon, 19 Mar 2018 18:22:35 +0000 (18:22 +0000)]
Fix CMake/MSVC when compiler-rt and llvm are built separately
Summary:
For some reason CMake can't find the `append` macro if LLVM is built separately and imported via `LLVM_CONFIG_PATH`.
Patch by Loo Rong Jie
Reviewers: rnk, vitalybuka
Reviewed By: rnk, vitalybuka
Subscribers: dberris, mgorny, llvm-commits, #sanitizers
Differential Revision: https://reviews.llvm.org/D43458
llvm-svn: 327876
Andrey Churbanov [Mon, 19 Mar 2018 18:05:15 +0000 (18:05 +0000)]
Fix for Fix for https://bugs.llvm.org/show_bug.cgi?id=36705.
Differential Revision: https://reviews.llvm.org/D44637
llvm-svn: 327875
Craig Topper [Mon, 19 Mar 2018 17:58:41 +0000 (17:58 +0000)]
[X86] Add the rest of the TEST with immediate instructions to the scheduler models to match their 8-bit counterpart.
llvm-svn: 327874
Alexey Bataev [Mon, 19 Mar 2018 17:53:56 +0000 (17:53 +0000)]
[OPENMP, NVPTX] Reworked castToType() function, NFC.
Reworked function castToType to use more frontend functionality rather
than the backend.
llvm-svn: 327873
Craig Topper [Mon, 19 Mar 2018 17:46:59 +0000 (17:46 +0000)]
[X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to match MOV8ri. Correct SchedRW and itinerary for MOV32ri64.
llvm-svn: 327872
Zaara Syeda [Mon, 19 Mar 2018 17:40:14 +0000 (17:40 +0000)]
[ELF] Add basic support for PPC LE
This patch adds changes to start supporting the Power 64-Bit ELF V2 ABI.
This includes:
- Changing the ElfSym::GlobalOffsetTable to be named .TOC.
- Creating a GotHeader so the first entry in the .got is .TOC.
- Setting the e_flags to be 1 for ELF V1 and 2 for ELF V2
Differential Revision: https://reviews.llvm.org/D44483
llvm-svn: 327871
Akira Hatanaka [Mon, 19 Mar 2018 17:38:40 +0000 (17:38 +0000)]
[ObjC] Allow declaring __weak pointer fields in C structs in ARC.
This patch uses the infrastructure added in r326307 for enabling
non-trivial fields to be declared in C structs to allow __weak fields in
C structs in ARC.
This recommits r327206, which was reverted because it caused
module-enabled builders to fail. I discovered that the
CXXRecordDecl::CanPassInRegisters flag wasn't being set correctly in
some cases after I moved it to RecordDecl.
Thanks to Eric Liu for helping me investigate the bug.
rdar://problem/
33599681
https://reviews.llvm.org/D44095
llvm-svn: 327870
Craig Topper [Mon, 19 Mar 2018 17:31:41 +0000 (17:31 +0000)]
[X86] Remove sse41 specific code from lowering v16i8 multiply
With the SRAs removed from the SSE2 code in D44267, then there doesn't appear to be any advantage to the sse41 code. The punpcklbw instruction and pmovsx seem to have the same latency and throughput on most CPUs. And the SSE41 code requires moving the upper 64-bits into the lower 64-bit before the sign extend can be done. The unpckhbw in sse2 code can do better than that.
llvm-svn: 327869
Alexey Bataev [Mon, 19 Mar 2018 17:18:13 +0000 (17:18 +0000)]
[OPENMP] Fix build with MSVC, NFC.
llvm-svn: 327868
Alexey Bataev [Mon, 19 Mar 2018 17:04:07 +0000 (17:04 +0000)]
[OPENMP, NVPTX] Emit correct thread id.
We emitted fake thread id for the outined function in NVPTX codegen.
Patch adds emission of the real thread id.
llvm-svn: 327867
Craig Topper [Mon, 19 Mar 2018 16:38:33 +0000 (16:38 +0000)]
[X86] Make the multiply and divide itineraries more consistent.
Sometimes we used the same itinerary for MEM and REG forms, but that seems inconsistent with our usual usage.
We also used the MUL8 itinerary for MULX32/64 which was also weird.
The test changes are because we were using IIC_IMUL32_RR and IIC_IMUL64_RR instead of IIC_IMUL32_REG/IIC_IMUL64_REG for the 32 and 64 bit multiplies that produce double width result.
llvm-svn: 327866
Vedant Kumar [Mon, 19 Mar 2018 16:24:58 +0000 (16:24 +0000)]
Xcode: Include DWARFUnit.{h,cpp} in the build
This should address a bot failure due to r327809.
llvm-svn: 327865
Zaara Syeda [Mon, 19 Mar 2018 16:19:44 +0000 (16:19 +0000)]
Revert [MachineLICM] This reverts commit rL327856
Failing build bots. Revert the commit now.
llvm-svn: 327864
Serge Pavlov [Mon, 19 Mar 2018 16:13:43 +0000 (16:13 +0000)]
[Driver] Avoid invalidated iterator in insertTargetAndModeArgs
Doing an .insert() can potentially invalidate iterators by reallocating the
vector's storage. When all the stars align just right, this causes segfaults
or glibc aborts.
Gentoo Linux bug (crashes while building Chromium): https://bugs.gentoo.org/650082.
Patch by Hector Martin!
Differential Revision: https://reviews.llvm.org/D44607
llvm-svn: 327863
Matt Davis [Mon, 19 Mar 2018 16:06:40 +0000 (16:06 +0000)]
[CodeGen] Avoid handling DBG_VALUE in the LivePhysRegs (addUses,removeDefs,stepForward)
Summary:
This patch prevents DBG_VALUE instructions from influencing
LivePhysRegs::stepBackwards and stepForwards. In at least one case,
specifically branch folding, the stepBackwards logic was having an
influence on code generation. The result was that certain code
compiled with '-g -O2' would differ from that compiled with '-O2'
alone. It seems that the original logic, accounting for DBG_VALUE,
was influencing the placement of an IMPLICIT_DEF which had a later
impact on how blocks were processed in branch folding.
Reviewers: kparzysz, MatzeB
Reviewed By: kparzysz
Subscribers: bjope, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D43850
llvm-svn: 327862
Krasimir Georgiev [Mon, 19 Mar 2018 15:33:40 +0000 (15:33 +0000)]
[clang-format] Remove empty lines before }[;] // comment
Summary:
This addresses bug 36766 and a FIXME in tests about empty lines before
`}[;] // comment` lines.
Subscribers: klimek, cfe-commits
Differential Revision: https://reviews.llvm.org/D44631
llvm-svn: 327861
Petr Hosek [Mon, 19 Mar 2018 15:19:19 +0000 (15:19 +0000)]
[CMake] Use libc++ and compiler-rt as default libraries in Fuchsia toolchain
Fuchsia already defaults to libc++ and compiler-rt, but we want to use
these as default runtimes even on the host platform.
Differential Revision: https://reviews.llvm.org/D39930
llvm-svn: 327860
Erik Pilkington [Mon, 19 Mar 2018 15:18:23 +0000 (15:18 +0000)]
[demangler] Recopy the demangler from libcxxabi.
Some significant work has gone into libcxxabi's copy of this file:
- Uses an AST to represent mangled names.
- Support/bugfixes for many C++ features.
- Uses LLVM coding style.
llvm-svn: 327859
Sanjay Patel [Mon, 19 Mar 2018 15:14:30 +0000 (15:14 +0000)]
[InstCombine] canonicalize fcmp+select to fabs
This is complicated by -0.0 and nan. This is based on the DAG patterns
as shown in D44091. I'm hoping that we can just remove those DAG folds
and always rely on IR canonicalization to handle the matching to fabs.
We would still need to delete the broken code from DAGCombiner to fix
PR36600:
https://bugs.llvm.org/show_bug.cgi?id=36600
Differential Revision: https://reviews.llvm.org/D44550
llvm-svn: 327858
Tobias Grosser [Mon, 19 Mar 2018 15:05:30 +0000 (15:05 +0000)]
Move code generation test case to test/CodeGen/
llvm-svn: 327857
Zaara Syeda [Mon, 19 Mar 2018 14:52:25 +0000 (14:52 +0000)]
[MachineLICM] Add functions to MachineLICM to hoist invariant stores
This patch adds functions to allow MachineLICM to hoist invariant stores.
Currently, MachineLICM does not hoist any store instructions, however
when storing the same value to a constant spot on the stack, the store
instruction should be considered invariant and be hoisted. The function
isInvariantStore iterates each operand of the store instruction and checks
that each register operand satisfies isCallerPreservedPhysReg. The store
may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore.
This patch also adds the PowerPC changes needed to consider the stack
register as caller preserved.
Differential Revision: https://reviews.llvm.org/D40196
llvm-svn: 327856
Simon Pilgrim [Mon, 19 Mar 2018 14:46:07 +0000 (14:46 +0000)]
[X86] Generalize schedule classes to support multiple stages
Currently the WriteResPair style multi-classes take a single pipeline stage and latency, this patch generalizes this to make it easier to create complex schedules with ResourceCycles and NumMicroOps be overriden from their defaults.
This has already been done for the Jaguar scheduler to remove a number of custom schedule classes and adding it to the other x86 targets will make it much tidier as we add additional classes in the future to try and replace so many custom cases.
I've converted some instructions but a lot of the models need a bit of cleanup after the patch has been committed - memory latencies not being consistent, the class not actually being used when we could remove some/all customs, etc. I'd prefer to keep this as NFC as possible so later patches can be smaller and target specific.
Differential Revision: https://reviews.llvm.org/D44612
llvm-svn: 327855
Miklos Vajna [Mon, 19 Mar 2018 14:43:59 +0000 (14:43 +0000)]
run-clang-tidy: forward clang-tidy exit status
Exit with a non-zero value in case any of the underlying clang-tidy
invocations exit with a non-zero value.
This is useful in case WarningsAsErrors is enabled for some of the
checks: if any of those checks find something, the exit status now
reflects that.
Also add the ability to use run-clang-tidy.py via lit, and assert that
the exit code is not 0 when modernize-use-auto is triggered
intentionally.
Reviewers: alexfh, aaron.ballman
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D44366
llvm-svn: 327854
Sanjay Patel [Mon, 19 Mar 2018 14:26:50 +0000 (14:26 +0000)]
[x86] put nops into the WriteNop class and customize for Jaguar
1. Given that we already have a classification bucket with 'nop' in the name,
that's where 'nop' belongs. Right now, it's only used for prefix bytes and 'pause'.
2. Make the latency of this class '1' for Jaguar to tell the scheduler (and presumably
llvm-mca) how to model the resource requirements better even though a nop has no
dependencies.
Differential Revision: https://reviews.llvm.org/D44608
llvm-svn: 327853
Ilya Biryukov [Mon, 19 Mar 2018 14:20:25 +0000 (14:20 +0000)]
Updated a usage of createTemporaryFile that does not expect file to be created.
Summary:
This fixes a usage of createTemporaryFile in clang repo after
a change in llvm repo.
Reviewers: klimek, bkramer, krasimir, espindola, ilya-biryukov
Reviewed By: ilya-biryukov
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D36828
llvm-svn: 327852
Ilya Biryukov [Mon, 19 Mar 2018 14:19:58 +0000 (14:19 +0000)]
Changed createTemporaryFile without FD to actually create a file.
Summary:
This commit changes semantics of createUniqueFile and
createTemporaryFile variants that do not return file descriptors.
Previously they only checked if files exist, therefore being subject
to race conditions. Now they will create an empty file to avoid them.
Functions that do not create a file are now called
getPotentiallyUniqueTempFileName and getPotentiallyUniqueFileName.
Reviewers: klimek, bkramer, krasimir, JDevlieghere, espindola
Reviewed By: klimek
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36827
llvm-svn: 327851
Nicolai Haehnle [Mon, 19 Mar 2018 14:14:28 +0000 (14:14 +0000)]
TableGen: Explicitly forbid self-references to field members
Summary:
Otherwise, patterns like in the test case produce cryptic error
messages about fields being resolved incompletely.
Change-Id: I713c0191f00fe140ad698675803ab1f8823dc5bd
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44476
llvm-svn: 327850
Nicolai Haehnle [Mon, 19 Mar 2018 14:14:20 +0000 (14:14 +0000)]
TableGen: Check the dynamic type of !cast<Rec>(string)
Summary:
The docs already claim that this happens, but so far it hasn't. As a
consequence, existing TableGen files get this wrong a lot, but luckily
the fixes are all reasonably straightforward.
To make this work with all the existing forms of self-references (since
the true type of a record is only built up over time), the lookup of
self-references in !cast is delayed until the final resolving step.
Change-Id: If5923a72a252ba2fbc81a889d59775df0ef31164
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D44475
llvm-svn: 327849
Nicolai Haehnle [Mon, 19 Mar 2018 14:14:10 +0000 (14:14 +0000)]
TableGen: Explicitly test some cases of self-references and !cast errors
Summary:
These are cases of self-references that exist today in practice. Let's
add tests for them to avoid regressions.
The self-references in PPCInstrInfo.td can be expressed in a simpler
way. Allowing this type of self-reference while at the same time
consistently doing late-resolve even for self-references is problematic
because there are references to fields that aren't in any class. Since
there's no need for this type of self-reference anyway, let's just
remove it.
Change-Id: I914e0b3e1ae7adae33855fac409b536879bc3f62
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: nemanjai, wdng, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D44474
llvm-svn: 327848
Nicolai Haehnle [Mon, 19 Mar 2018 14:14:04 +0000 (14:14 +0000)]
TableGen: Only fold when some operand made resolve progress
Summary:
Make sure that we always fold immediately, so there's no point in
attempting to re-fold when nothing changes.
Change-Id: I069e1989455b6f2ca8606152f6adc1a5e817f1c8
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44198
llvm-svn: 327847
Nicolai Haehnle [Mon, 19 Mar 2018 14:13:59 +0000 (14:13 +0000)]
TableGen: Remove OpInit::Fold
Summary:
Virtual dispatch is not actually used anywhere.
Change-Id: I9829c5c59920ea27fb9bc17f1442156a3bb09a65
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44197
llvm-svn: 327846
Nicolai Haehnle [Mon, 19 Mar 2018 14:13:54 +0000 (14:13 +0000)]
TableGen: Move GenStrConcat to a helper function in BinOpInit
Summary:
Make it accessible for more users.
Change-Id: Ib05f09ba14e7942ced5d2f24b205efa285e40cd5
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44196
llvm-svn: 327845
Nicolai Haehnle [Mon, 19 Mar 2018 14:13:37 +0000 (14:13 +0000)]
TableGen: Remove the cast-from-string-to-variable-reference feature
Summary:
Cast-from-string for records isn't going away, but cast-from-string for
variables is a pretty dodgy feature to have, especially when referencing
template arguments. It's doubtful that this ever worked in a reliable
way, and nobody seems to be using it, so let's get rid of it and get
some related cleanups.
Change-Id: I395ac8a43fef4cf98e611f2f552300d21e99b66a
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44195
llvm-svn: 327844
Matt Arsenault [Mon, 19 Mar 2018 14:07:23 +0000 (14:07 +0000)]
AMDGPU/GlobalISel: RegBankSelect for basic int ops
llvm-svn: 327843
Matt Arsenault [Mon, 19 Mar 2018 14:07:15 +0000 (14:07 +0000)]
AMDGPU: Don't leave dead illegal VGPR->SGPR copies
Normally DCE kills these, but at -O0 these get left behind
leaving suspicious looking illegal copies.
Replace with IMPLICIT_DEF to avoid iterator issues.
llvm-svn: 327842
Karl-Johan Karlsson [Mon, 19 Mar 2018 13:48:40 +0000 (13:48 +0000)]
[NFC] Fix minor typos in comments
llvm-svn: 327841
Clement Courbet [Mon, 19 Mar 2018 13:37:04 +0000 (13:37 +0000)]
[MergeICmps] Re-land 324317 "Enable the MergeICmps Pass by default."
Now that PR36557 is fixed.
llvm-svn: 327840
Sjoerd Meijer [Mon, 19 Mar 2018 13:35:25 +0000 (13:35 +0000)]
[ARM] Support for v4f16 and v8f16 vectors
This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which
uses v4f16 and v8f16 vector operands and return values. All the moving parts
are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16
intrinsic. In a follow-up patch the rest of the intrinsics and tests will be
added.
Differential Revision: https://reviews.llvm.org/D44538
llvm-svn: 327839
Xin Tong [Mon, 19 Mar 2018 13:35:23 +0000 (13:35 +0000)]
Stylish change. NFC
llvm-svn: 327838
Andrea Di Biagio [Mon, 19 Mar 2018 13:23:07 +0000 (13:23 +0000)]
[llvm-mca] Add pipeline stall events.
This patch introduces a new class named HWStallEvent (see HWEventListener.h),
and updates the event listener interface. A HWStallEvent represents a pipeline
stall caused by the lack of hardware resources. Similarly to HWInstructionEvent,
the event type is an unsigned, and the exact meaning depends on the subtarget.
At the moment, HWStallEvent supports a few generic dispatch events.
The main goals of this patch is to remove the logic that counts dispatch stalls
from the DispatchUnit to the BackendStatistics view.
Previously, DispatchUnit was responsible for counting and classifying dispatch
stall events. With this patch, we delegate the task of counting and classifying
stall events to the listeners (i.e. in our case, it is view
"BackendStatistics"). So, the DispatchUnit doesn't have to do extra
(unnecessary) bookkeeping.
This patch also helps futher simplifying the Backend interface. Now class
BackendStatistics no longer has to query the Backend interface to obtain the
number of dispatch stalls. As a consequence, we can get rid of all the
'getNumXXX()' methods from class Backend.
The long term goal is to remove all the remaining dependencies between the
Backend and the BackendStatistics interface.
Differential Revision: https://reviews.llvm.org/D44621
llvm-svn: 327837
Sjoerd Meijer [Mon, 19 Mar 2018 13:22:49 +0000 (13:22 +0000)]
[ARM] Pass half or i16 types for NEON intrinsics
For generating NEON intrinsics, this determines the NEON data type, and whether
it should be a half type or an i16 type. I.e., we always pass a half type for
AArch64, this hasn't changed, but now also for ARM but only when FullFP16 is
enabled, and i16 otherwise.
This is intended to be non-functional change, but together with the backend
work in D44538 which adds support for f16 vectors, this enables adding the
AArch32 FP16 (vector) intrinsics.
Differential Revision: https://reviews.llvm.org/D44561
llvm-svn: 327836
Hans Wennborg [Mon, 19 Mar 2018 13:05:37 +0000 (13:05 +0000)]
build_llvm_package.bat: Drop LLDB from the package.
I don't think anyone ever got this to work, what with getting exactly
the right Python dependency and so on. Removing it simplifies the
script, removes a number of hairy dependencies, and cuts ~30 MB off the
installer size.
llvm-svn: 327835
Jonas Paulsson [Mon, 19 Mar 2018 13:05:22 +0000 (13:05 +0000)]
[SystemZ] Bugfix of CC liveness in emitMemMemWrapper (CLC).
If DoneMBB becomes empty it must have CC added to its live-in list, since it
will fall-through into EndMBB. This happens when the CLC loop does the
complete range.
Review: Ulrich Weigand
llvm-svn: 327834
Alexander Kornienko [Mon, 19 Mar 2018 13:02:32 +0000 (13:02 +0000)]
[clang-tidy] New check bugprone-unused-return-value
Summary:
Detects function calls where the return value is unused.
Checked functions can be configured.
Reviewers: alexfh, aaron.ballman, ilya-biryukov, hokein
Reviewed By: alexfh, aaron.ballman
Subscribers: hintonda, JonasToth, Eugene.Zelenko, mgorny, xazax.hun, cfe-commits
Tags: #clang-tools-extra
Patch by Kalle Huttunen!
Differential Revision: https://reviews.llvm.org/D41655
llvm-svn: 327833
Hans Wennborg [Mon, 19 Mar 2018 12:55:58 +0000 (12:55 +0000)]
HexagonISelLowering.cpp: fix 'enum in bool context' warning
llvm-svn: 327832
Alex Bradbury [Mon, 19 Mar 2018 11:54:28 +0000 (11:54 +0000)]
[RISCV] Peephole optimisation for load/store of global values or constant addresses
(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)
This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.
llvm-svn: 327831
Alexander Potapenko [Mon, 19 Mar 2018 10:08:04 +0000 (10:08 +0000)]
[MSan] fix the types of RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
Despite their names, RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
used to be i8* instead of i8**.
This is important, because these pointers are dereferenced twice
(first in CreateLoad(), then in getShadowOriginPtr()), but for some
reason MSan allowed this - most certainly because it was possible
to optimize getShadowOriginPtr() away at compile time.
Differential revision: https://reviews.llvm.org/D44520
llvm-svn: 327830
Alexander Potapenko [Mon, 19 Mar 2018 10:03:47 +0000 (10:03 +0000)]
[MSan] Don't create zero offsets in getShadowPtrForArgument(). NFC
For MSan instrumentation with MS.ParamTLS and MS.ParamOriginTLS being
TLS variables, the CreateAdd() with ArgOffset==0 is a no-op, because
the compiler is able to fold the addition of 0.
But for KMSAN, which receives ParamTLS and ParamOriginTLS from a call
to the runtime library, this introduces a stray instruction which
complicates reading/testing the IR.
Differential revision: https://reviews.llvm.org/D44514
llvm-svn: 327829
Alexander Potapenko [Mon, 19 Mar 2018 09:59:44 +0000 (09:59 +0000)]
[MSan] Introduce insertWarningFn(). NFC
This is a step towards the upcoming KMSAN implementation patch.
KMSAN is going to use a different warning function,
__msan_warning_32(uptr origin), so we'd better create the warning
calls in one place.
Differential Revision: https://reviews.llvm.org/D44513
llvm-svn: 327828
Mikhail Maltsev [Mon, 19 Mar 2018 09:48:58 +0000 (09:48 +0000)]
[ARM] Fix warnings about missing parentheses in ARMAsmParser
llvm-svn: 327827
Serguei Katkov [Mon, 19 Mar 2018 08:32:09 +0000 (08:32 +0000)]
[SCEV] Factor out isKnownViaInduction. NFC.
This just extracts the isKnownViaInduction from isKnownPredicate.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44554
llvm-svn: 327824
Peter Smith [Mon, 19 Mar 2018 06:52:51 +0000 (06:52 +0000)]
[ELF] Recommit 327248 with Arm using the .got for _GLOBAL_OFFSET_TABLE_
This is the same as 327248 except Arm defining _GLOBAL_OFFSET_TABLE_ to
be the base of the .got section as some existing code is relying upon it.
For most Targets the _GLOBAL_OFFSET_TABLE_ symbol is expected to be at
the start of the .got.plt section so that _GLOBAL_OFFSET_TABLE_[0] =
reserved value that is by convention the address of the dynamic section.
Previously we had defined _GLOBAL_OFFSET_TABLE_ as either the start or end
of the .got section with the intention that the .got.plt section would
follow the .got. However this does not always hold with the current
default section ordering so _GLOBAL_OFFSET_TABLE_[0] may not be consistent
with the reserved first entry of the .got.plt.
X86, X86_64 and AArch64 will use the .got.plt. Arm, Mips and Power use .got
Fixes PR36555
Differential Revision: https://reviews.llvm.org/D44259
llvm-svn: 327823
Serguei Katkov [Mon, 19 Mar 2018 06:35:30 +0000 (06:35 +0000)]
[SCEV] Re-land: Fix isKnownPredicate
This is re-land of https://reviews.llvm.org/rL327362 with a fix
and regression test.
The crash was due to it is possible that for found MDL loop,
LHS or RHS may contain an invariant unknown SCEV which
does not dominate the MDL. Please see regression
test for an example.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44553
llvm-svn: 327822
Craig Topper [Mon, 19 Mar 2018 04:21:42 +0000 (04:21 +0000)]
[X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a couple scheduler models.
llvm-svn: 327821
Craig Topper [Mon, 19 Mar 2018 04:21:40 +0000 (04:21 +0000)]
[X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the scheduler models to match ADD8i8.
Also move ADC8i8 and SBB8i8 in the Sandy Bridge model to the same class as ADC8ri and SBB8ri. That seems more accurate since its the 8i8 is just the register forced to AL instead of coming from modrm.
llvm-svn: 327820
Craig Topper [Mon, 19 Mar 2018 02:07:32 +0000 (02:07 +0000)]
[X6] Remove two unused InstrItinClass
llvm-svn: 327819
Jan Vesely [Mon, 19 Mar 2018 01:01:10 +0000 (01:01 +0000)]
remainder: Port from amd builtins
Mostly ported from amd_builtins, uses only denormal path for fp32.
Passes CTS on carrizo and turks
Reviewer: Aaron Watry <awatry@gmail.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 327818
Craig Topper [Mon, 19 Mar 2018 00:56:12 +0000 (00:56 +0000)]
[X86] Use IIC_CMOV64_RR/RM on 64-bit cmov instructions.
llvm-svn: 327817
Craig Topper [Mon, 19 Mar 2018 00:56:11 +0000 (00:56 +0000)]
[X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single regular expressions in scheduler models.
llvm-svn: 327816
Craig Topper [Mon, 19 Mar 2018 00:56:09 +0000 (00:56 +0000)]
[X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in the scheduler models as much as possible. NFCI
This reduces the total number of generated scheduler classes from 5404 to 5316.
llvm-svn: 327815
Dylan McKay [Mon, 19 Mar 2018 00:55:50 +0000 (00:55 +0000)]
[AVR] Lower i128 divisions to runtime library calls
This patch adds i128 division support by instruction LLVM to lower
128-bit divisions to the __udivmodti4 and __divmodti4 rtlib functions.
This also adds test for 64-bit division and 128-bit division.
Patch by Peter Nimmervoll.
llvm-svn: 327814
Craig Topper [Sun, 18 Mar 2018 22:16:54 +0000 (22:16 +0000)]
[Mips] Remove duplicate lines from MipsScheduleP5600.td and enable FullInstRWOverlapCheck.
This fixes the errors found by the new check added in r327808.
llvm-svn: 327813
Craig Topper [Sun, 18 Mar 2018 22:16:53 +0000 (22:16 +0000)]
[AArch64] Fix a few InstRWs in the A53 scheduler model and enable FullInstRWOverlapCheck.
This fixes the errors found by the new check added in r327808.
llvm-svn: 327812
Craig Topper [Sun, 18 Mar 2018 21:28:11 +0000 (21:28 +0000)]
[SelectionDAG] Don't default the SelectionDAG* parameter to SDValue::dump to nullptr. Use two different signatures instead.
This matches what we do in SDNode.
This should allow SDValue::dump to be used in the debugger without getting an error if you don't pass an argument.
llvm-svn: 327811
Jan Kratochvil [Sun, 18 Mar 2018 20:11:02 +0000 (20:11 +0000)]
Move the codebase to use: DWARFCompileUnit -> DWARFUnit
Now the codebase can use the DWARFUnit superclass. It will make it later
seamlessly work also with DWARFPartialUnit for DWZ.
This patch is only a search-and-replace easily undone, nothing interesting
in it.
Differential revision: https://reviews.llvm.org/D42892
llvm-svn: 327810
Jan Kratochvil [Sun, 18 Mar 2018 20:09:02 +0000 (20:09 +0000)]
DWARFUnit split out of DWARFCompileUnit
DW_TAG_partial_unit for DWZ can be then presented by DWARFPartialUnit also
inherited from DWARFUnit.
Differential revision: https://reviews.llvm.org/D40466
llvm-svn: 327809
Craig Topper [Sun, 18 Mar 2018 19:56:15 +0000 (19:56 +0000)]
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check.
So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag.
A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found.
llvm-svn: 327808
Simon Pilgrim [Sun, 18 Mar 2018 19:54:42 +0000 (19:54 +0000)]
[X86][Btver2] Fix crc32 schedule costs
The default is currently FAdd for some reason
llvm-svn: 327807
Marshall Clow [Sun, 18 Mar 2018 19:29:21 +0000 (19:29 +0000)]
Updated C++2a status with changes from Jacksonville WG21 meeting
llvm-svn: 327806
Simon Pilgrim [Sun, 18 Mar 2018 18:55:34 +0000 (18:55 +0000)]
[X86][Btver2] Add crc32 resource tests
llvm-svn: 327805
Simon Pilgrim [Sun, 18 Mar 2018 18:45:57 +0000 (18:45 +0000)]
[X86][Btver2] FADD/FHADD ymm instructions are double pumped on the JFPA functional pipe
llvm-svn: 327804
Simon Pilgrim [Sun, 18 Mar 2018 17:10:12 +0000 (17:10 +0000)]
[X86][Btver2] Float bitwise ymm instructions are double pumped on the JFPX (JFPA/JFPM) functional pipes
llvm-svn: 327803
Bjorn Pettersson [Sun, 18 Mar 2018 16:07:20 +0000 (16:07 +0000)]
Resolve unused variable 'VR' warning in RetainCountChecker.cpp
Getting rid of
error: unused variable 'VR' [-Werror,-Wunused-variable]
warning/error at
lib/StaticAnalyzer/Checkers/RetainCountChecker.cpp:1933
llvm-svn: 327802
Simon Pilgrim [Sun, 18 Mar 2018 15:59:51 +0000 (15:59 +0000)]
[X86][Btver2] F16C instructions are performed on the JSTC functional pipe
llvm-svn: 327801
Anastasis Grammenos [Sun, 18 Mar 2018 15:59:19 +0000 (15:59 +0000)]
[LICM] Salvage DI from dying Instructions
LICM deletes trivially dead instructions which it won't attempt to sink.
Attempt to salvage debug values which reference these instructions.
llvm-svn: 327800
Roman Lebedev [Sun, 18 Mar 2018 15:53:02 +0000 (15:53 +0000)]
[InstCombine] peek through unsigned FP casts for zero-equality compares (PR36682)
Summary:
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
See also D44416
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44424
llvm-svn: 327799
Andrea Di Biagio [Sun, 18 Mar 2018 15:33:27 +0000 (15:33 +0000)]
[llvm-mca] Allow the definition of multiple register files.
This is a refactoring in preparation for other two changes that will allow
scheduling models to define multiple register files. This is the first step
towards fixing PR36662.
class RegisterFile (in Dispatch.h) now can emulate multiple register files.
Internally, it tracks the number of available physical registers in each
register file (described by class RegisterFileInfo).
Each register file is associated to a list of MCRegisterClass indices. Knowing
the register class indices allows to map physical registers to register files.
The long term goal is to allow processor models to optionally specify how many
register files are implemented via tablegen.
Differential Revision: https://reviews.llvm.org/D44488
llvm-svn: 327798
Sanjay Patel [Sun, 18 Mar 2018 14:32:54 +0000 (14:32 +0000)]
[InstCombine] add nnan requirement for sqrt(x) * sqrt(y) -> sqrt(x*y)
This is similar to D43765.
llvm-svn: 327797
Sanjay Patel [Sun, 18 Mar 2018 14:12:25 +0000 (14:12 +0000)]
[InstSimplify] loosen FMF for sqrt(X) * sqrt(X) --> X
As shown in the code comment, we don't need all of 'fast',
but we do need reassoc + nsz + nnan.
Differential Revision: https://reviews.llvm.org/D43765
llvm-svn: 327796
Simon Pilgrim [Sun, 18 Mar 2018 13:16:11 +0000 (13:16 +0000)]
[X86][Btver2] Strip default latency/resource values. NFCI.
llvm-svn: 327795
Simon Pilgrim [Sun, 18 Mar 2018 13:05:09 +0000 (13:05 +0000)]
[X86][Btver2] SSE4A EXTRQ/INSERTQ instructions are performed on the JVALU0/JVALU1 functional pipes
llvm-svn: 327794
Simon Pilgrim [Sun, 18 Mar 2018 12:37:35 +0000 (12:37 +0000)]
[X86][Btver2] Modelled float bitwise instructions as being performed on the float cluster (FPA/FPM) not the integer.
llvm-svn: 327793
Jonas Devlieghere [Sun, 18 Mar 2018 12:27:05 +0000 (12:27 +0000)]
[dsymutil] Fix add_llvm_tool_symlink
Update the arguments to add_llvm_tool_symlink to symlink llvm-dsymutil
to dsymutil.
llvm-svn: 327792
Simon Pilgrim [Sun, 18 Mar 2018 12:09:17 +0000 (12:09 +0000)]
[X86][Btver2] Correctly distinguish between scheduling pipe and functional unit for JWriteResFpuPair defs
Jaguar's FPU has 2 scheduler pipes (JFPU0/JFPU1) which forward to multiple functional sub-units each. We need to model that an micro-op will both consume the scheduler pipe and a functional unit.
This patch just handles the ops defined through JWriteResFpuPair, I'll go through the custom cases later.
llvm-svn: 327791
Jonas Devlieghere [Sun, 18 Mar 2018 11:38:41 +0000 (11:38 +0000)]
[dsymutil] Rename llvm-dsymutil -> dsymutil
Now that almost all functionality of Apple's dsymutil has been
upstreamed, the open source variant can be used as a drop in
replacement. Hence we feel it's no longer necessary to have the llvm
prefix.
Differential revision: https://reviews.llvm.org/D44527
llvm-svn: 327790
Simon Pilgrim [Sun, 18 Mar 2018 10:22:35 +0000 (10:22 +0000)]
[X86][Btver2] Merge equivalent VBLENDVY + VPERMILY schedule groups
Thanks to Craig Topper for noticing this.
llvm-svn: 327789
Simon Pilgrim [Sun, 18 Mar 2018 09:32:38 +0000 (09:32 +0000)]
[X86][Btver2] Add llvm-mca tests to show pipe resource usage of most vector instructions
Hopefully these tests can be easily reused should any other subtarget get in depth llvm-mca coverage (we can either copy the tests or move them into a common dir and run it with multiple prefixes).
llvm-svn: 327788
Craig Topper [Sun, 18 Mar 2018 08:38:06 +0000 (08:38 +0000)]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models.
llvm-svn: 327787
Craig Topper [Sun, 18 Mar 2018 08:38:04 +0000 (08:38 +0000)]
[X86] Fix a couple typos in the Zen scheduler model.
llvm-svn: 327786
Craig Topper [Sun, 18 Mar 2018 08:38:03 +0000 (08:38 +0000)]
[TableGen] Remove unnecessary uses of make_range.
llvm-svn: 327785
Craig Topper [Sun, 18 Mar 2018 08:38:02 +0000 (08:38 +0000)]
[TableGen] Move some variables into for loop declaration. NFC
They aren't needed after the loop.
llvm-svn: 327784
Craig Topper [Sun, 18 Mar 2018 03:24:42 +0000 (03:24 +0000)]
[X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models.
The information was so wildly inaccurate and incomplete its better to just remove it.
MMX_MASKMOVQ64 showed up twice in several scheduler models. In Haswell and Broadwell they were on adjacent lines. On Skylake the copies had different information.
MMX_MASKMOVQ and MASKMOVDQU were completely missing.
MMX_MASKMOVQ64 was listed on Haswell/Broadwell as 1 cycle on port 1 despite it being a store instruction.
Filed PR36780 to track fixing this right.
llvm-svn: 327783
Zhihao Yuan [Sat, 17 Mar 2018 21:42:10 +0000 (21:42 +0000)]
[C++17] Allow an empty expression in an if init statement
Summary:
This fixes [PR35381](https://llvm.org/pr35381) and an additional bug where clang didn't warn about the C++17 extension when having an expression in the init statement.
Thanks Nicolas Lesser for contributing the patch.
Reviewers: rsmith
Reviewed By: rsmith
Subscribers: erik.pilkington, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D40445
llvm-svn: 327782
Aaron Ballman [Sat, 17 Mar 2018 21:08:40 +0000 (21:08 +0000)]
Implement DR2229, which prohibits unnamed bit-fields from having qualifiers in C++.
llvm-svn: 327781
Zhihao Yuan [Sat, 17 Mar 2018 21:01:27 +0000 (21:01 +0000)]
Fix codegen for structured binding binding in conditions
Summary:
The codegen for conditions assumes that a normal variable declaration is used in a condition, but this is not the case when a structured binding is used.
This fixes [PR36747](http://llvm.org/pr36747).
Thanks Nicolas Lesser for contributing the patch.
Reviewers: lichray, rsmith
Reviewed By: lichray
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D44534
llvm-svn: 327780
Martin Storsjo [Sat, 17 Mar 2018 20:08:48 +0000 (20:08 +0000)]
[AArch64] Skip an unnecessary getCopyToReg in DYNAMIC_STACKALLOC
Differential Revision: https://reviews.llvm.org/D44586
llvm-svn: 327779
Nirav Dave [Sat, 17 Mar 2018 19:24:54 +0000 (19:24 +0000)]
Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172""
as it times out building test-suite on PPC.
llvm-svn: 327778
Nirav Dave [Sat, 17 Mar 2018 17:42:10 +0000 (17:42 +0000)]
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
Reland ISel cycle checking improvements after simplifying and reducing
node id invariant traversal.
llvm-svn: 327777