platform/kernel/u-boot.git
4 years agorockchip: roc-rk3399-pc: Set LED only during POR and pwr_key=y
Jagan Teki [Tue, 21 Jul 2020 15:06:04 +0000 (20:36 +0530)]
rockchip: roc-rk3399-pc: Set LED only during POR and pwr_key=y

ROC-RK3399-PC has specific set of configurations for
on-board led setup.

Due to easiness for user to know the state of the board
roc-rk339-pc board code will setup the low power led
on/off, and waiting for user to press power key and then
glow full power led.

All this needs to happen only during power-on-reset not
for soft reset or WDT.

Also, it is not a proper usage to ask the user to press
the Power key if the board connected remotely, so add
the environment variable 'pwr_key' to check as well.

So, user need to press Power key only
- during POR
- pwr_key=y

Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: Separate the reset cause from display cpuinfo
Jagan Teki [Tue, 21 Jul 2020 15:06:03 +0000 (20:36 +0530)]
rockchip: Separate the reset cause from display cpuinfo

reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed. 

Other than cpuinfo, reset cause can also be using during
bootcount for checking the specific reset cause and glow
the led based on the reset cause.

So, let's separate the reset cause code from cpuinfo, and
add a check to build it for rk3399, rk3288 since these two
soc are supporting reset cause as of now.

Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: Don't clear the reset status reg
Jagan Teki [Tue, 21 Jul 2020 15:06:02 +0000 (20:36 +0530)]
rockchip: Don't clear the reset status reg

reset reason can be used several stages of U-Boot bootloader
like SPL, U-Boot proper based on the requirements.

Clearing the status register end of get_reset_cause will end
up showing the wrong reset cause when it read the second time.
For example, if board resets, SPL reads the reset status as
RST whereas U-Boot proper reads the status as POR.

However, based on the latest testing clearing reset status
won't be required for determine the last reset cause or
following resets.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: tpl: Remove board_early_init_f()
Kever Yang [Wed, 22 Jul 2020 12:26:30 +0000 (20:26 +0800)]
rockchip: tpl: Remove board_early_init_f()

There is no need for board_early_init_f() in TPL, anything like this
should goes to SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: roc-rk3399-pc: Add custom led_setup()
Jagan Teki [Tue, 21 Jul 2020 15:06:01 +0000 (20:36 +0530)]
rockchip: roc-rk3399-pc: Add custom led_setup()

roc-rk3399-pc has some specific requirements to support LEDS,
environment. board detection and etc prior to U-Boot proper.

So as of now SPL would be a better stage for these custom board
requirements to support unlike TPL. Adding few of these custom
requirements like LEDS in TPL would require extra code pulling
and also the size of TPL can grow.

So, this patch moves the leds code from TPL into SPL Board init
led_setup code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(split tpl.c change as separate patch)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rk3399: Add weak led_setup()
Jagan Teki [Tue, 21 Jul 2020 15:06:00 +0000 (20:36 +0530)]
rockchip: rk3399: Add weak led_setup()

Add weak led_setup() so that board which has an uncommon
led setup code that can make use of custom implementation.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rk3288: Add OF board setup
Jagan Teki [Tue, 21 Jul 2020 06:46:38 +0000 (12:16 +0530)]
rockchip: rk3288: Add OF board setup

The new rk3288 revision rk3288w has some changes with respect
to legacy rk3288 like hclk_vio in cru and usb host0 ohci.

Linux clock driver already handle this via rockchip,rk3288w-cru
compatible.

USB ohci host can enable via dts for rk3288w based boards.

So, add fdt board setup code to update cru compatible with
rk3288w-cru compatible if the SOC revision is RK3288W.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: Add rk3288 SoC detection helper
Jagan Teki [Tue, 21 Jul 2020 06:46:37 +0000 (12:16 +0530)]
rockchip: Add rk3288 SoC detection helper

Rockchip SoC's has a new revision chip for rk3288 SoCs.

RK3288 has a new revision chip called RK3288W which is similar
but different hclk_vio clock and fixed OHCI host.

Add common Rockchip SoC detection helper to support this rk3288w
detection.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoarm64: dts: rockchip: Add Radxa ROCK Pi 4C support
Jagan Teki [Mon, 20 Jul 2020 18:55:49 +0000 (00:25 +0530)]
arm64: dts: rockchip: Add Radxa ROCK Pi 4C support

Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled
GPIO pin change compared to 4B, 4C.

So, add or enable difference nodes/properties in 4C dts
by including common dtsi.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoarm64: dts: rockchip: Add ROCKPi 4A/4B support
Jagan Teki [Mon, 20 Jul 2020 18:55:48 +0000 (00:25 +0530)]
arm64: dts: rockchip: Add ROCKPi 4A/4B support

Rock PI 4 has 3 variants of hardware platforms called
RockPI 4A, 4B, and 4C.

- Rock PI 4A has no Wif/BT.
- Rock PI 4B has AP6256 Wifi/BT, PoE.
- Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enable
  GPIO pin change compared to 4B, 4C

So move common nodes, properties into dtsi file and include
on respective variant dts files.

Use 4B dts into default rock-pi-4 defconfig until we find any
solution for dynamic detection of these variants.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: firefly-rk3399: enable CONFIG_USB_DWC3
Kever Yang [Wed, 22 Jul 2020 11:46:19 +0000 (19:46 +0800)]
rockchip: firefly-rk3399: enable CONFIG_USB_DWC3

To fix below build error:
drivers/usb/host/built-in.o: In function `xhci_dwc3_remove':
drivers/usb/host/xhci-dwc3.c:174: undefined reference to `dwc3_shutdown_phy'
drivers/usb/host/built-in.o: In function `xhci_dwc3_probe':
drivers/usb/host/xhci-dwc3.c:130: undefined reference to `dwc3_setup_phy'

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rk3399: Add default env to support compressed kernel Image
Kever Yang [Sat, 18 Jul 2020 14:45:19 +0000 (22:45 +0800)]
rockchip: rk3399: Add default env to support compressed kernel Image

Add default kernel_comp_addr_r and kernel_comp_size to support boot
from compressed kernel Image, this space is temporarily used during
decompress according to README.distro.

Reported-by: Tian Yuanhao <tianyuanhao@aliyun.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: sdram: fix dram_init_banksize
Alex Bee [Tue, 14 Jul 2020 23:03:31 +0000 (01:03 +0200)]
rockchip: sdram: fix dram_init_banksize

Currently 2.5 GB is calculated as DRAM size for a 1 GB RK322x board
if CONFIG_SPL_OPTEE is set. This is troublesome when booting a
linux kernel since this size will be injected in FDT of the kernel.

gd->bd->bi_dram[0].start (which is basically CONFIG_SYS_SDRAM_BASE)
must not be taken into consideration for calculation of second bank
size, since this offset is already included in calculation of "top".

After applying this patch 992 MB (1024 MB - 32 MB reserved for
optee-os) is correctly calculated and has also been verified on
2 GB boards.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agopci: rockchip: Drop legacy PHY driver
Jagan Teki [Thu, 9 Jul 2020 18:11:03 +0000 (23:41 +0530)]
pci: rockchip: Drop legacy PHY driver

Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agopci: rockchip: Switch to generic-phy
Jagan Teki [Thu, 9 Jul 2020 18:11:02 +0000 (23:41 +0530)]
pci: rockchip: Switch to generic-phy

Now, we have a PCIe PHY driver as part of the Generic
PHY framework. Let's use it instead of legacy PHY driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agophy: Add Rockchip PCIe PHY driver
Jagan Teki [Thu, 9 Jul 2020 18:11:01 +0000 (23:41 +0530)]
phy: Add Rockchip PCIe PHY driver

Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: roc-rk3399-pc: Disable RAM_ROCKCHIP_DEBUG
Jagan Teki [Mon, 13 Jul 2020 20:06:35 +0000 (01:36 +0530)]
rockchip: roc-rk3399-pc: Disable RAM_ROCKCHIP_DEBUG

Disable ram rockchip debug driver for roc-rk3399-pc
boards since we have verified ram in many instances
with respective U-Boot versions.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not set
Kever Yang [Mon, 20 Jul 2020 10:34:12 +0000 (18:34 +0800)]
rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not set

The empty function define should not be in the header file, or else the
build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG
is disabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUG
Jagan Teki [Mon, 13 Jul 2020 20:06:34 +0000 (01:36 +0530)]
ram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUG

Right now all these debug statements are printing on the
console to make sure proper dram initialization happens.  

Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful
and work like before since the RAM_ROCKCHIP_DEBUG is by
default yet.

No functionality changes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3399: Drop debug stride in driver
Jagan Teki [Mon, 13 Jul 2020 20:06:33 +0000 (01:36 +0530)]
ram: rk3399: Drop debug stride in driver

stride debug is already present in sdram_common.c via
RAM_ROCKCHIP_DEBUG.

So, drop the redundant debug stride code in rk3399 driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rock64-rk3328_defconfig: Add SPI Flash support
Johannes Krottmayer [Wed, 8 Jul 2020 22:50:34 +0000 (00:50 +0200)]
rockchip: rock64-rk3328_defconfig: Add SPI Flash support

Add U-Boot SPI Flash support for the PINE64 Rock64 board

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoARM: dts: rk3328-rock64: Add SPI Flash support
Johannes Krottmayer [Wed, 8 Jul 2020 22:50:33 +0000 (00:50 +0200)]
ARM: dts: rk3328-rock64: Add SPI Flash support

Add U-Boot SPI Flash support for the PINE64 Rock64 board

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoARM: dts: rk3328: Add SPI support
Johannes Krottmayer [Wed, 8 Jul 2020 21:57:40 +0000 (23:57 +0200)]
ARM: dts: rk3328: Add SPI support

Add U-Boot SPI support for the RK3328

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(fix checkpatch error for code ident)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agodrivers: spi: rk_spi: Add support for RK3328
Johannes Krottmayer [Wed, 8 Jul 2020 21:57:39 +0000 (23:57 +0200)]
drivers: spi: rk_spi: Add support for RK3328

Add support for the RK3328 SPI controller

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agodrivers: clk: rockchip: clk_rk3328: Add SPI support
Johannes Krottmayer [Wed, 8 Jul 2020 21:57:38 +0000 (23:57 +0200)]
drivers: clk: rockchip: clk_rk3328: Add SPI support

Add SPI support for the RK3328 clock driver

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: roc-rk3399-pc: Update ENV offset, size
Jagan Teki [Tue, 7 Jul 2020 13:50:49 +0000 (19:20 +0530)]
rockchip: roc-rk3399-pc: Update ENV offset, size

Adjust the ENV offset, size to fit into all images
on 16MB flash.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: roc-rk3399-pc: Enable USB Gadget
Jagan Teki [Tue, 7 Jul 2020 13:50:48 +0000 (19:20 +0530)]
rockchip: roc-rk3399-pc: Enable USB Gadget

Enable DWC3 core, gadget for roc-rk3399-pc board.

This would help to use fastboot by default.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rock-pi-4: Enable HDMI output
Jagan Teki [Tue, 7 Jul 2020 13:50:47 +0000 (19:20 +0530)]
rockchip: rock-pi-4: Enable HDMI output

Enable config options to get HDMI output on RockPI-4 boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rock-pi-4: Enable USB Gadget
Jagan Teki [Tue, 7 Jul 2020 13:50:46 +0000 (19:20 +0530)]
rockchip: rock-pi-4: Enable USB Gadget

Enable USB gadget for rock-pi-4 boards.

This would help to use fastboot by default.

Note: Connect the Host USB cable (Port A or C) to rock-pi-4
Upper USB 3.0 port.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rock-pi-4: Enable PCI/NVME
Jagan Teki [Tue, 7 Jul 2020 13:50:45 +0000 (19:20 +0530)]
rockchip: rock-pi-4: Enable PCI/NVME

Enable PCI/NVME for M.2 Slot on RockPI-4 boards.

=> nvme info
Device 0: Vendor: 0x144d Rev: 2B2QEXM7 Prod: S4EUNG0MC10012Y
            Type: Hard Disk
            Capacity: 238475.1 MB = 232.8 GB (488397168 x 512)

Cc: Tom Cubie <tom@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rock-pi-4: Enable USB3 Host
Jagan Teki [Tue, 7 Jul 2020 13:50:44 +0000 (19:20 +0530)]
rockchip: rock-pi-4: Enable USB3 Host

Enable USB3.0 Host support for RockPI-4 boards.

Note that the Upper USB3.0 port is marked as otg and
lower USB3.0 port marked as host, so this below log
capture when USB3.0 mass storage plug in at lower
USB 3.0 port.

Log:
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3c0000: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@fe380000 for devices... 1 USB Device(s) found
scanning bus usb@fe3c0000 for devices... 1 USB Device(s) found
scanning bus dwc3 for devices... 1 USB Device(s) found
scanning bus dwc3 for devices... cannot reset port 1!?
2 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
     u-boot EHCI Host Controller

  1  Hub (480 Mb/s, 0mA)
     u-boot EHCI Host Controller

  1  Hub (5 Gb/s, 0mA)
     U-Boot XHCI Host Controller

  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Mass Storage (5 Gb/s, 224mA)
       SanDisk Dual Drive 040130e3ee554b7078843f4eb331646

Cc: Tom Cubie <tom@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rockpro64: Enable USB3.0 Host
Jagan Teki [Mon, 20 Jul 2020 09:23:09 +0000 (14:53 +0530)]
rockchip: rockpro64: Enable USB3.0 Host

Enable USB3.0 Host support for RockPro64 boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: board: add Hardkernel Odroid Go2 board
Heiko Stuebner [Wed, 1 Jul 2020 09:28:42 +0000 (11:28 +0200)]
rockchip: board: add Hardkernel Odroid Go2 board

Also known as Odroid Go Advance but named Go2 internally by the
vendor it seems.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: px30: sync Odroid Go Advance devicetree from Linux
Heiko Stuebner [Wed, 1 Jul 2020 09:28:41 +0000 (11:28 +0200)]
rockchip: px30: sync Odroid Go Advance devicetree from Linux

Get the devicetree from mainline Linux and include it for U-Boot uses.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: px30: sync the main rk3326 dtsi from mainline
Heiko Stuebner [Wed, 1 Jul 2020 09:28:40 +0000 (11:28 +0200)]
rockchip: px30: sync the main rk3326 dtsi from mainline

The rk3326 is just a trimmed down px30 from a software perspective,
so the mainline rk3326 dtsi also ist just a tiny addition.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMerge branch '2020-07-17-misc-fixes'
Tom Rini [Fri, 17 Jul 2020 20:08:54 +0000 (16:08 -0400)]
Merge branch '2020-07-17-misc-fixes'

A large number of assorted fixes, including but not limited to:
- Correct fixdep and CONFIG_IS_ENABLED(...)
- lz4 on big endian
- Assorted LMB hardening
- Remove bd_t typedef

4 years agoinclude: pci_ids: Add Cavium devices
Suneel Garapati [Fri, 17 Jul 2020 06:06:22 +0000 (08:06 +0200)]
include: pci_ids: Add Cavium devices

Add VendorID and DeviceID for supported devices on OcteonTX/TX2
platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 years agodoc: fit: Write hex address as hex instead of int
Michal Simek [Wed, 15 Jul 2020 13:10:17 +0000 (15:10 +0200)]
doc: fit: Write hex address as hex instead of int

When update_uboot.its is used directly there is syntax error for no reason.

Error report:
mkimage -f update_uboot.its boot
Error: update_uboot.its:18.12-13 syntax error
FATAL ERROR: Unable to parse input tree
mkimage: Can't read boot.tmp: Invalid argument

Fixes: 4bae90904b69 ("Automatic software update from TFTP server")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agomtd: mtdpart: use uint64_t instead of int for cur_off
Martin Kaistra [Mon, 13 Jul 2020 12:40:02 +0000 (14:40 +0200)]
mtd: mtdpart: use uint64_t instead of int for cur_off

The types of "offset" and "size" of "struct mtd_partition" are uint64_t,
while mtd_parse_partitions() uses int to work with these values. When
the offset reaches 2GB, it is interpreted as a negative value, which
leads to error messages like

mtd: partition "<partition name>" is out of reach -- disabled

eg. when using the "ubi part" command.

Fix this by using uint64_t for cur_off and cur_sz.

Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de>
Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoboard/km: update MAINTAINERS email
Holger Brunck [Thu, 9 Jul 2020 15:31:23 +0000 (17:31 +0200)]
board/km: update MAINTAINERS email

Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com>
CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
4 years agodoc: correct description of crash dumps
Heinrich Schuchardt [Thu, 9 Jul 2020 06:12:06 +0000 (08:12 +0200)]
doc: correct description of crash dumps

Correct the description of the ESR register.

Fix a typo.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agofixdep: fix CONFIG_IS_ENABLED etc. handling
Stephen Warren [Wed, 8 Jul 2020 21:45:56 +0000 (15:45 -0600)]
fixdep: fix CONFIG_IS_ENABLED etc. handling

When fixdep detects CONFIG_IS_ENABLED and other similar macros, it must
parse the macro parameter to determine which actual CONFIG_ option is
being referenced. This involves moving a pointer forward through the
entire CONFIG_ option "word". Currently, the code uses variable q to walk
through the word, but doesn't actually initialize it to point at the
parameter before doing so. Consequently, the walking process immediately
fails since it sees the macro invocatoins's ( rather than the expected
alpha-numeric characters in the macro parameter. Fix this by adding the
missing initialization.

Fixes: 67f2ee86ccbe ("kbuild: fixdep: Resync this with v4.17")
Fixes: 7012865e961c ("gpio: fix test.py for gpio label lookup")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agomkimage: Fix error message if write less data then expected
Mylène Josserand [Wed, 8 Jul 2020 09:52:50 +0000 (11:52 +0200)]
mkimage: Fix error message if write less data then expected

Add a new error message in case the size of data written
are shorter than the one expected.

Currently, it will lead to the following error message:

"mkimage: Write error on uImage: Success"

This is not explicit when the error is because the device
doesn't have enough space. Let's use a more understandable message:

"mkimage: Write only 4202432/4682240 bytes, probably no space left on the device"

Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
Reviewed-by: Walter Lozano <walter.lozano@collabora.com>
4 years agoremove include/config_defaults.h
Rasmus Villemoes [Tue, 7 Jul 2020 08:40:26 +0000 (10:40 +0200)]
remove include/config_defaults.h

Since commit 4b0bcfa7c4ec (Kconfig: Migrate CONFIG_BOOTM_* options),
the config_defaults.h file has been void of any actual content - and
these days, "sane defaults for everyone" is achieved by appropriate
default values in Kconfig. Remove it, and thus make every translation
unit process one less header file.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agodoc: multi-dtb-fit: Remove double underscores
Fabio Estevam [Sun, 5 Jul 2020 22:04:50 +0000 (19:04 -0300)]
doc: multi-dtb-fit: Remove double underscores

Remove the incorrect usage of double underscores for the
CONFIG_OF_LIST and CONFIG_SPL_OF_LIST symbols.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
4 years agofs: error handling in do_load()
Heinrich Schuchardt [Mon, 29 Jun 2020 18:08:49 +0000 (20:08 +0200)]
fs: error handling in do_load()

If a file cannot be loaded, show an error message.
Set the EFI boot device only after successfully loading a file.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoasm/u-boot.h: remove bd_t definitions
Masahiro Yamada [Fri, 26 Jun 2020 06:13:35 +0000 (15:13 +0900)]
asm/u-boot.h: remove bd_t definitions

All the users of bd_t were converted to struct bd_info.

Remove the definitions.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
4 years agotreewide: convert bd_t to struct bd_info manually
Masahiro Yamada [Fri, 26 Jun 2020 06:13:34 +0000 (15:13 +0900)]
treewide: convert bd_t to struct bd_info manually

Some code was not converted by coccinelle, somehow.

I manually fixed up the remaining, and comments, README docs.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
[trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and
        include/fdt_support.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agotreewide: convert bd_t to struct bd_info by coccinelle
Masahiro Yamada [Fri, 26 Jun 2020 06:13:33 +0000 (15:13 +0900)]
treewide: convert bd_t to struct bd_info by coccinelle

The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
4 years agoarm64: Remove CONFIG_SYS_FULL_VA macro
Michal Simek [Thu, 25 Jun 2020 07:26:57 +0000 (09:26 +0200)]
arm64: Remove CONFIG_SYS_FULL_VA macro

All configurations have been removed in 2016 by commit 7985cdf74b28
("arm64: Remove non-full-va map code").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoMakefile: Silence relocate-rela call
Jan Kiszka [Thu, 25 Jun 2020 06:39:45 +0000 (08:39 +0200)]
Makefile: Silence relocate-rela call

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
4 years agolib: zlib: Remove offset pointer optimization in inftrees.c
Chin Liang See [Wed, 24 Jun 2020 08:31:08 +0000 (16:31 +0800)]
lib: zlib: Remove offset pointer optimization in inftrees.c

This fixes the CVE-2016-9840. Commit imported from [1].

inftrees.c was subtracting an offset from a pointer to an array,
in order to provide a pointer that allowed indexing starting at
the offset. This is not compliant with the C standard, for which
the behavior of a pointer decremented before its allocated memory
is undefined. Per the recommendation of a security audit of the
zlib code by Trail of Bits and TrustInSoft, in support of the
Mozilla Foundation, this tiny optimization was removed, in order
to avoid the possibility of undefined behavior.

[1]: https://github.com/madler/zlib/commit/6a043145ca6e9c55184013841a67b2fef87e44c0

Signed-off-by: Mark Adler <madler@alumni.caltech.edu>
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoConvert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to Kconfig
Patrick Delaunay [Wed, 17 Jun 2020 16:19:18 +0000 (18:19 +0200)]
Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to Kconfig

This converts the following to Kconfig:
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_PSCI_0_2

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agospl: fix ext4fs_mount return code handling
Thomas Schaefer [Tue, 16 Jun 2020 20:03:52 +0000 (22:03 +0200)]
spl: fix ext4fs_mount return code handling

- Despite other ext4 filesystem functions, ext4fs_mount returns
  0 in case of error.
- This leads to u-boot crash in case that an SD card
  with valid partition table but without ext4 filesystem created
  in a partition is found on SD card.
- Fix this by returning a proper error code of '-1' from spl_load_image_ext
  function in case of ext4fs_mount error.

Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
[hthiery: slightly reword the commit message]
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agocmd: booti: convert the debug print about image move to printf
Tero Kristo [Fri, 12 Jun 2020 12:41:21 +0000 (15:41 +0300)]
cmd: booti: convert the debug print about image move to printf

Moving of the OS image may have some nasty side effects like corrupting
DTB. Convert the current debug print to printf so that the relocation of
the OS is always obvious to the user.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
4 years agocommon: bootm: add checks to verify if ramdisk / fdtimage overlaps OS image
Tero Kristo [Fri, 12 Jun 2020 12:41:20 +0000 (15:41 +0300)]
common: bootm: add checks to verify if ramdisk / fdtimage overlaps OS image

These cases are typically fatal and are difficult to debug for random
users. Add checks for detecting overlapping images and abort if overlap
is detected.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
4 years agoimage: fdt: bail out with error if no boot time FDT image found
Tero Kristo [Fri, 12 Jun 2020 12:41:19 +0000 (15:41 +0300)]
image: fdt: bail out with error if no boot time FDT image found

Currently the boot continues if the FDT image is clearly corrupted,
which just causes the loaded OS to hang. Abort boot properly if the FDT
is corrupted.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
4 years agoConvert CONFIG_MXC_UART to Kconfig
Tom Rini [Tue, 9 Jun 2020 14:46:46 +0000 (10:46 -0400)]
Convert CONFIG_MXC_UART to Kconfig

This converts the following to Kconfig:
   CONFIG_MXC_UART

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
4 years agolz4: fix decompressor on big-endian powerpc
Rasmus Villemoes [Sun, 7 Jun 2020 12:29:18 +0000 (14:29 +0200)]
lz4: fix decompressor on big-endian powerpc

Booting an lz4-compressed kernel image fails on our powerpc board with
-EPROTONOSUPPORT. Adding a bit of debug prints, we get

  magic: 0x184d2204
  flags: 0x64
  reserved0: 1
  has_content_checksum: 1
  has_content_size: 0
  has_block_checksum: 0
  independent_blocks: 1
  version: 0
  block_descriptor: 70
  reserved1: 7
  max_block_size: 0
  reserved2: 0

So the magic is ok, but the version check fails, also some reserved
bits are apparently set. But that's because the code interprets the
"flags" and "block_descriptor" bytes wrongly:

Using bit-fields to access individual bits of an "on the wire" format
is not portable, not even when restricted to the C flavour implemented
by gcc. Quoting the gcc manual:

   * 'The order of allocation of bit-fields within a unit (C90 6.5.2.1,
     C99 and C11 6.7.2.1).'

     Determined by ABI.

and indeed, the PPC Processor ABI supplement says

   * Bit-fields are allocated from right to left (least to most
     significant) on Little-Endian implementations and from left to
     right (most to least significant) on Big-Endian implementations.

The upstream code (github.com/lz4/lz4) uses explicit shifts and masks
for encoding/decoding:

    /* FLG Byte */
    *dstPtr++ = (BYTE)(((1 & _2BITS) << 6)    /* Version('01') */
        + ((cctxPtr->prefs.frameInfo.blockMode & _1BIT ) << 5)
        + ((cctxPtr->prefs.frameInfo.blockChecksumFlag & _1BIT ) << 4)
        + ((unsigned)(cctxPtr->prefs.frameInfo.contentSize > 0) << 3)
        + ((cctxPtr->prefs.frameInfo.contentChecksumFlag & _1BIT ) << 2)
        +  (cctxPtr->prefs.frameInfo.dictID > 0) );

    /* Flags */
    {   U32 const FLG = srcPtr[4];
        U32 const version = (FLG>>6) & _2BITS;
        blockChecksumFlag = (FLG>>4) & _1BIT;
        blockMode = (FLG>>5) & _1BIT;
        contentSizeFlag = (FLG>>3) & _1BIT;
        contentChecksumFlag = (FLG>>2) & _1BIT;
        dictIDFlag = FLG & _1BIT;
        /* validate */
        if (((FLG>>1)&_1BIT) != 0) return err0r(LZ4F_ERROR_reservedFlag_set); /* Reserved bit */
        if (version != 1) return err0r(LZ4F_ERROR_headerVersion_wrong);        /* Version Number, only supported value */
    }

Do the same here, and while at it, be more careful to use unaligned
accessors to what is most likely unaligned. Also update the comment to
make it clear that it only refers to the lz4.c file, not the following
code of lz4_wrapper.c.

This has been tested partly, of course, by seeing that my
lz4-compressed kernel now boots, partly by running the (de)compression
test-suite in the (x86_64) sandbox - i.e., it should still work just
fine on little-endian hosts.

Reviewed-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agodoc: Coccinelle: move to HTML doc
Heinrich Schuchardt [Fri, 5 Jun 2020 03:13:44 +0000 (05:13 +0200)]
doc: Coccinelle: move to HTML doc

Move doc/README.coccinelle to doc/develop/coccinelle.rst using the current
linux-next version of the text.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
Tom Rini [Fri, 17 Jul 2020 12:04:48 +0000 (08:04 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- New timer API to allow delays with a 32-bit microsecond timer
- Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core
- x86: Enable ACPI table generation by default
- x86: Enable the copy framebuffer on Coral
- x86: A few fixes to FSP2 with ApolloLake
- x86: Drop setup_pcat_compatibility()
- x86: Primary-to-Sideband Bus minor fixes

4 years agoMerge tag 'u-boot-imx-20200716' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Tom Rini [Fri, 17 Jul 2020 12:04:28 +0000 (08:04 -0400)]
Merge tag 'u-boot-imx-20200716' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.10
----------------

- i.MX DDR driver fix/update for i.MX8M
- i.MX pinctrl driver fix.
- Use arm_smccc_smc to remove imx sip function
- i.MX8M clk update
- support booting aarch32 kernel on aarch64 hardware
- fused part support for i.MX8MP
- imx6: pcm058 to DM

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785

4 years agoacpi: Enable ACPI table generation by default on x86
Simon Glass [Fri, 17 Jul 2020 03:22:39 +0000 (21:22 -0600)]
acpi: Enable ACPI table generation by default on x86

This should ideally be used by all x86 boards in U-Boot. Enable it by
default. If some boards don't use it, the cost is small.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Rename board_final_cleanup() to board_final_init()
Simon Glass [Fri, 17 Jul 2020 03:22:38 +0000 (21:22 -0600)]
x86: Rename board_final_cleanup() to board_final_init()

This function sounds like something that is called when U-Boot is about to
jump to Linux. In fact it is an init function.

Rename it to reduce confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: acpi: Correct the version of the MADT
Simon Glass [Fri, 17 Jul 2020 03:22:37 +0000 (21:22 -0600)]
x86: acpi: Correct the version of the MADT

Currently U-Boot implements version 2 but reports version 4. Correct it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: Drop setup_pcat_compatibility()
Simon Glass [Fri, 17 Jul 2020 03:22:36 +0000 (21:22 -0600)]
x86: Drop setup_pcat_compatibility()

This function does not exist anymore. Drop it from the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Update the comment about booting for FSP2
Simon Glass [Fri, 17 Jul 2020 03:22:35 +0000 (21:22 -0600)]
x86: Update the comment about booting for FSP2

The comment here applies only to FSP1, so update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: Store the coreboot table address in global_data
Simon Glass [Fri, 17 Jul 2020 03:22:34 +0000 (21:22 -0600)]
x86: Store the coreboot table address in global_data

At present this information is used to locate and parse the tables but is
not stored. Store it so that we can display it to the user, e.g. with the
'bdinfo' command.

Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(),
so it is always set when booting from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: apl: Adjust FSP-M code to avoid hard-coded address
Simon Glass [Fri, 17 Jul 2020 03:22:33 +0000 (21:22 -0600)]
x86: apl: Adjust FSP-M code to avoid hard-coded address

Update this code to calculate the address to use, rather than hard-coding
it. Obtain the requested stack size from the FSP.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Set the correct boot mode in the FSP-M code
Simon Glass [Fri, 17 Jul 2020 03:22:32 +0000 (21:22 -0600)]
x86: apl: Set the correct boot mode in the FSP-M code

If there is MRC information we should run FSP-M with a different
boot_mode flag since it is supposed to do a 'fast path' through the
memory init. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add debugging to table writing
Simon Glass [Fri, 17 Jul 2020 03:22:31 +0000 (21:22 -0600)]
x86: Add debugging to table writing

Writing tables is currently pretty opaque. Add a bit of debugging to the
process so we can see what tables are written and where they start/end in
memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: apl: Fix save/restore of ITSS priorities
Simon Glass [Fri, 17 Jul 2020 03:22:30 +0000 (21:22 -0600)]
x86: apl: Fix save/restore of ITSS priorities

The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.

Fix this by allocating space in the relocated memory for the ITSS data.
Save it there and access it from the driver after relocation.

This fixes interrupt handling on coral.

Also drop the log_msg_ret() in irq_first_device_type() since this function
can be called speculatively in places where we are not sure if there is
an interrupt controller of that type. The resulting log errors are
confusing when there is no error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: irq: Support flags for acpi_gpe
Simon Glass [Wed, 8 Jul 2020 03:32:34 +0000 (21:32 -0600)]
x86: irq: Support flags for acpi_gpe

This binding currently has a flags cell but it is not used. Make use of it
to create ACPI tables for interrupts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agopmc: Move common registers to the header file
Simon Glass [Wed, 8 Jul 2020 03:32:33 +0000 (21:32 -0600)]
pmc: Move common registers to the header file

These registers need to be accesses from ACPI code, so move them to the
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Hide the p2sb on exit from U-Boot
Simon Glass [Wed, 8 Jul 2020 03:32:32 +0000 (21:32 -0600)]
x86: apl: Hide the p2sb on exit from U-Boot

This confuses Linux's PCI probing so needs to be hidden when booting
Linux. Add a remove() method to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: apl: Support set_hide() in p2sb driver
Simon Glass [Wed, 8 Jul 2020 03:32:31 +0000 (21:32 -0600)]
x86: apl: Support set_hide() in p2sb driver

Add support for this new method in the driver and in the fsp-s setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agop2sb: Add a method to hide the bus
Simon Glass [Wed, 8 Jul 2020 03:32:30 +0000 (21:32 -0600)]
p2sb: Add a method to hide the bus

The P2SB bus needs to be hidden in some cases so that it does not get
auto-configured by Linux. Add a method for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agoi2c: designware_i2c: Support ACPI table generation
Simon Glass [Wed, 8 Jul 2020 03:32:29 +0000 (21:32 -0600)]
i2c: designware_i2c: Support ACPI table generation

Update the PCI driver to generate ACPI information so that Linux has the
full information about each I2C bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Correct one typo in dw_i2c_gen_speed_config() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoi2c: Add log_ret() on error
Simon Glass [Wed, 8 Jul 2020 03:32:28 +0000 (21:32 -0600)]
i2c: Add log_ret() on error

Add a few of these calls to make it easier to see where an error occurs,
if CONFIG_LOG_ERROR_RETURN is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Add a little more debugging
Simon Glass [Wed, 8 Jul 2020 03:32:27 +0000 (21:32 -0600)]
i2c: designware_i2c: Add a little more debugging

Add debugging for a few more values and also use log to show return values
when something goes wrong. This makes it easier to see the root cause.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agox86: gpio: Add support for obtaining ACPI info for a GPIO
Simon Glass [Wed, 8 Jul 2020 03:32:26 +0000 (21:32 -0600)]
x86: gpio: Add support for obtaining ACPI info for a GPIO

Implement the method that converts a GPIO into the form used by ACPI, so
that GPIOs can be added to ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Use memory-mapped access for VBT
Simon Glass [Wed, 8 Jul 2020 03:32:25 +0000 (21:32 -0600)]
x86: apl: Use memory-mapped access for VBT

Use the new binman memory-mapping function to access the VBT, to simplify
the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add error checking for csrt table generation
Simon Glass [Wed, 8 Jul 2020 03:32:24 +0000 (21:32 -0600)]
x86: Add error checking for csrt table generation

Generation of this table can fail, so update the function to return an
error code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: pinctrl: Drop the acpi_path member
Simon Glass [Wed, 8 Jul 2020 03:32:23 +0000 (21:32 -0600)]
x86: pinctrl: Drop the acpi_path member

This is in the device tree now, so drop the unnecessary field here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: pinctrl: Set up itss in the probe() method
Simon Glass [Wed, 8 Jul 2020 03:32:22 +0000 (21:32 -0600)]
x86: pinctrl: Set up itss in the probe() method

At present the itss is probed in the ofdata_to_platdata() method. This is
incorrect since itss is a child of p2sb which itself needs to probe the
pinctrl device. This means that p2sb is effectively not probed when the
itss is probed, so we get the wrong register address from p2sb.

Fix this by moving the itss probe to the correct place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: pinctrl: Add multi-ACPI control
Simon Glass [Wed, 8 Jul 2020 03:32:21 +0000 (21:32 -0600)]
x86: pinctrl: Add multi-ACPI control

Add a Kconfig to control whether pinctrl is represented as a single ACPI
device or as multiple devices. In the latter case (the default) we should
return the pin number relative to the pinctrl device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: pinctrl: Update comment for intel_pinctrl_get_pad()
Simon Glass [Wed, 8 Jul 2020 03:32:20 +0000 (21:32 -0600)]
x86: pinctrl: Update comment for intel_pinctrl_get_pad()

Add information about what is returned on error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: pinctrl: Add a way to get the pinctrl reg address
Simon Glass [Wed, 8 Jul 2020 03:32:19 +0000 (21:32 -0600)]
x86: pinctrl: Add a way to get the pinctrl reg address

At present we can query the offset of a pinctrl register within the p2sb.
For ACPI we need to get the actual address of the register. Add a function
to handle this and rename the old one to more accurately reflect its
purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agosound: Add an ACPI driver for Maxim MAX98357ac
Simon Glass [Wed, 8 Jul 2020 03:32:18 +0000 (21:32 -0600)]
sound: Add an ACPI driver for Maxim MAX98357ac

This chip is used on coral and we need to generate ACPI tables for sound
to make it work. Add a driver that does just this (i.e. at present does
not actually support playing sound).

Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: Use the correct acpi_irq_polarity enum number]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agosound: Add an ACPI driver for Dialog Semicondutor da7219
Simon Glass [Wed, 8 Jul 2020 03:32:17 +0000 (21:32 -0600)]
sound: Add an ACPI driver for Dialog Semicondutor da7219

This chip is used on coral and we need to generate ACPI tables for sound
to make it work. Add a driver that does just this (i.e. at present does
not actually support playing sound).

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agox86: Add support for building up an NHLT structure
Simon Glass [Wed, 8 Jul 2020 03:32:16 +0000 (21:32 -0600)]
x86: Add support for building up an NHLT structure

The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.

Add functions to allow adding to the structure that is eventually written
to the ACPI tables. Also add the device-tree bindings.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoacpi: Support writing named values
Simon Glass [Wed, 8 Jul 2020 03:32:15 +0000 (21:32 -0600)]
acpi: Support writing named values

Allow writing named integers and strings to the generated ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix the "new blank line at EOF" warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoacpi: Support generation of a device
Simon Glass [Wed, 8 Jul 2020 03:32:14 +0000 (21:32 -0600)]
acpi: Support generation of a device

Allow writing an ACPI device to the generated ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix build failures on Sandbox]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add bindings for NHLT
Simon Glass [Wed, 8 Jul 2020 03:32:13 +0000 (21:32 -0600)]
x86: Add bindings for NHLT

Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
(NHLT).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoacpi: mmc: Generate ACPI info for the PCI SD Card
Simon Glass [Wed, 8 Jul 2020 03:32:12 +0000 (21:32 -0600)]
acpi: mmc: Generate ACPI info for the PCI SD Card

Write required information into the SSDT to describe the SD card
card-detect pin. Since the required GPIO properties are not present in
the device-tree binding, set them manually for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoacpi: Support generation of a generic register
Simon Glass [Wed, 8 Jul 2020 03:32:11 +0000 (21:32 -0600)]
acpi: Support generation of a generic register

Allow writing out a generic register.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix build failures on Sandbox]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoacpi: Support generation of a scope
Simon Glass [Wed, 8 Jul 2020 03:32:10 +0000 (21:32 -0600)]
acpi: Support generation of a scope

Add a function to write a scope to the generated ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Fix build failures on Sandbox]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoacpi: Export functions to write sized values
Simon Glass [Wed, 8 Jul 2020 03:32:09 +0000 (21:32 -0600)]
acpi: Export functions to write sized values

At present only acpigen_write_integer() is exported for use by other code.
But in some cases it is useful to call the specific function depending on
the size of the value.

Export these functions and add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Fix the "new blank line at EOF" warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agodm: acpi: Add support for the NHLT table
Simon Glass [Wed, 8 Jul 2020 03:32:08 +0000 (21:32 -0600)]
dm: acpi: Add support for the NHLT table

The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.

Add core support for this, based on a structure which is built up through
calls to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agodm: core: Add a way of overriding the ACPI device path
Simon Glass [Wed, 8 Jul 2020 03:32:07 +0000 (21:32 -0600)]
dm: core: Add a way of overriding the ACPI device path

Some devices such as GPIO need to override the normal path that would be
generated by driver model. Add a device-tree property for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>