Rob Clark [Sun, 13 Jun 2021 20:37:16 +0000 (13:37 -0700)]
freedreno: Add debugging for blitter fallback recursion
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11371>
Rob Clark [Sun, 13 Jun 2021 15:21:52 +0000 (08:21 -0700)]
freedreno: Don't try staging blit for non-renderable formats
If a format is not supported as a render target, there is no point in
trying a staging blit, as it will end up in a CPU copy fallback.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11371>
Rob Clark [Sun, 13 Jun 2021 20:36:19 +0000 (13:36 -0700)]
freedreno: Drop obsolete comment
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11371>
Chia-I Wu [Tue, 15 Jun 2021 00:27:23 +0000 (17:27 -0700)]
venus: be verbose about which physical devices are skipped
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11369>
Chia-I Wu [Mon, 14 Jun 2021 23:39:54 +0000 (16:39 -0700)]
venus: fix compatibility with older host drivers
Unlike on Android, KHR_swapchain may be advertised even when the host
driver does not support EXT_image_drm_format_modifier and
EXT_queue_family_foreign. Do not request those extensions when they are
not supported.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11369>
Chia-I Wu [Tue, 15 Jun 2021 00:23:07 +0000 (17:23 -0700)]
venus: clean up vn_physical_device_get_native_extensions
Separate Android and non-Android paths. No real change.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11369>
Rhys Perry [Mon, 17 Aug 2020 19:22:23 +0000 (20:22 +0100)]
nir/cse: resize the instruction set
ministat (CSE only):
Difference at 95.0% confidence
-3357.54 +/- 32.5177
-25.267% +/- 0.24098%
(Student's t, pooled s = 33.909)
ministat (entire run):
Difference at 95.0% confidence
-3414.27 +/- 270.628
-2.76477% +/- 0.217647%
(Student's t, pooled s = 282.207)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6390>
Rhys Perry [Mon, 17 Aug 2020 18:56:16 +0000 (19:56 +0100)]
nir: use a single set during CSE
Use a single set and ensure dominance by checking after a equivalent
instruction is found.
Besides removing the need to copy a set, this also lets us resize the set
at the start of the pass in the next commit.
ministat (CSE only):
Difference at 95.0% confidence
-984.956 +/- 28.8559
-6.90075% +/- 0.190231%
(Student's t, pooled s = 26.9052)
ministat (entire run):
Difference at 95.0% confidence
-1246.1 +/- 257.253
-0.998972% +/- 0.205094%
(Student's t, pooled s = 239.863)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6390>
Jonathan Marek [Tue, 15 Jun 2021 16:42:12 +0000 (12:42 -0400)]
freedreno/registers: define REG_DSI_CPHY_MODE_CTRL
For use by the kernel driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11381>
Marcin Ślusarz [Mon, 14 Jun 2021 09:01:41 +0000 (11:01 +0200)]
iris: fix error message on I915_GEM_[GS]ET_TILING failure
The first problem was noticed by Coverity (CID 1485970).
Fixes:
ab49063f449 ("iris: Only use SET/GET_TILING when exporting/importing BOs")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11357>
Erik Faye-Lund [Mon, 14 Jun 2021 09:59:04 +0000 (11:59 +0200)]
zink: use correct type for u_bit_scan
Since we're going to iterate over each bit of this variable using
u_bit_scan, we should make sure we use an unsigned int for the variable.
While this works on GCC, it's not guaranteed to work, and produces a
warning on MSVC.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11358>
Felix DeGrood [Thu, 18 Mar 2021 16:44:33 +0000 (09:44 -0700)]
anv: Replace DC Flush with HDC Pipeline Flush
HDC Pipeline Flush is the correct method for flushing HDC
pipeline on Gfx12+ HW. Continue using DC Flush for earlier HW.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Felix DeGrood [Thu, 18 Mar 2021 02:46:41 +0000 (19:46 -0700)]
anv: Add ANV_PIPE_HDC_PIPELINE_FLUSH_BIT
Gfx12+ PIPE_CONTROL bit for flushing HDC cache and memory
transactions to L3 cache.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Felix DeGrood [Fri, 12 Mar 2021 23:36:49 +0000 (15:36 -0800)]
anv: Only flush Tile Cache on VK_ACCESS_HOST_R/W
Tile Cache flush flushes all Color/Depth values from L3 cache
to memory in Unified Cache mode. This is only required when
CPU access is required.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Felix DeGrood [Wed, 17 Mar 2021 04:02:35 +0000 (21:02 -0700)]
anv: remove unnecessary Tile Cache flushes
On Gfx12+, flushing tile cache ensures color/depth values are
globally visible, but that's expensive. Most operations only
need values to be GT-visible which can be achieved with depth
or rt flush. Remove a bunch of unnecessary Tile Cache flushes.
Fast clears and slow depth clears still require Tile Cache flush.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Felix DeGrood [Wed, 17 Mar 2021 04:00:59 +0000 (21:00 -0700)]
anv: Remove Tile Cache flush from SBA, Pipe Select
Tile Cache flushing not required for State Base Address or
Pipe Select instructions.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Felix DeGrood [Fri, 29 Jan 2021 22:40:11 +0000 (14:40 -0800)]
anv: Clear all pending stall after pipe flush
Was only clearing CS stalls after emitting pending pipe
controls. Need to clear all stalls.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Felix DeGrood [Thu, 11 Mar 2021 16:40:56 +0000 (08:40 -0800)]
anv: Add debug messages for DEBUG_PIPE_CONTROL
Enable with INTEL_DEBUG=pc.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Felix DeGrood [Wed, 24 Mar 2021 16:08:58 +0000 (09:08 -0700)]
anv: Cache VB/IB in L3$ for Gfx12
Gfx12 enables caching of Vertex and Index Buffers in L3.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Hoe Hao Cheng [Tue, 15 Jun 2021 10:55:54 +0000 (18:55 +0800)]
zink: standardize zero-init code style
quick grepping shows that the amount of {0} (there were 8) is higher
than { 0 } (only 5), so {0} it is!
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11376>
Hoe Hao Cheng [Tue, 15 Jun 2021 10:51:44 +0000 (18:51 +0800)]
zink: zero-init structs with ISO C
zero-initing with empty braces is a GNU extension, MSVC does not like
it.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11376>
Daniel Stone [Fri, 11 Jun 2021 19:04:38 +0000 (20:04 +0100)]
ci/lava: Generate YAML from Python, not Jinja
This makes it much easier to use the common init scripts ... which we
also do here.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 17:34:13 +0000 (18:34 +0100)]
ci/lava: Make kernel image type a normal argument
Just pass the actual parameter, rather than bare YAML.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 17:32:03 +0000 (18:32 +0100)]
ci/lava: Drop bitrotten fastboot support
We don't have any fastboot devices in LAVA, and even if we did, the old
overlay path no longer applies.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 16:14:21 +0000 (17:14 +0100)]
ci/lava: Use common stage-2 init
Now that our job-execution scripts look very similar for LAVA and
bare-metal, we can just tell LAVA to use the same stage-2 init we use
for bare-metal and delete a bunch of duplication.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 16:41:41 +0000 (17:41 +0100)]
ci/lava: Pass MinIO path on the command line
This brings us much closer with what bare-metal does, and also allows us
to upload job data to a local instance rather than the primary fd.o one.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 16:09:17 +0000 (17:09 +0100)]
ci/bare-metal: Set CPU and GPU governors to max, disable GPU runtime PM
Give us a bit more predictable performance by making sure we always run
at full tilt.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 15:53:54 +0000 (16:53 +0100)]
ci: Unify {BARE_METAL,LAVA}_TEST_SCRIPT environment
Should also probably never have been different.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 15:46:57 +0000 (16:46 +0100)]
ci: Unify {BM,LAVA}_START_XORG environment
Why were they ever different ... ?
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 15:44:55 +0000 (16:44 +0100)]
ci: Consistent pass/fail result output
One less point of differentiation.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 15:41:35 +0000 (16:41 +0100)]
ci/lava: Start using devcoredump captures
No reason not to.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 15:18:15 +0000 (16:18 +0100)]
ci/bare-metal: Move devcoredump capture to CI common
Reusing this for LAVA sounds like a good idea!
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 15:13:01 +0000 (16:13 +0100)]
ci/bare-metal: Split init script into two stages
Whilst we want to reuse the same init and job environment for LAVA and
bare-metal, LAVA needs to additionally inject wget and tar jobs, so we
can actually get our per-job environment, as the rootfs we run in is
just the container-generated base rootfs.
Split the init script into two stages, with the first stage doing very
base bringup of devices and networking, and the second stage setting the
job environment and running the jobs.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 14:56:19 +0000 (15:56 +0100)]
ci/bare-metal: Consistently set library paths
Everything needs them, so might as well set it up front.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 14:54:34 +0000 (15:54 +0100)]
ci: Be consistent about install path
Make both LAVA and bare-metal untar into $CI_PROJECT_DIR/install/, and
symlink /install/ to it during init.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 14:51:38 +0000 (15:51 +0100)]
ci: Move bare-metal init script to common directory
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 14:50:15 +0000 (15:50 +0100)]
ci/bare-metal: Reorder init so network comes first
Make sure that everything we need to ensure network access comes first,
so we can reuse this in LAVA which needs the network to pull the
per-pipeline build and the per-job environment overlays.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 14:45:44 +0000 (15:45 +0100)]
ci/bare-metal: Try harder to do NTP
Same as LAVA does.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 14:43:17 +0000 (15:43 +0100)]
ci/lava: Rename environment variable script
Make it line up with bare-metal.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 14:41:50 +0000 (15:41 +0100)]
ci/lava: Use HWCI_KERNEL_MODULES to load modules
One fewer difference to bare-metal.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Tomeu Vizoso [Tue, 15 Jun 2021 09:23:23 +0000 (11:23 +0200)]
ci/bare-metal: Add parens around shell command
Play safe and make sure we don't get bit by priority rules between the
|| and | operators.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Suggested-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Fri, 11 Jun 2021 14:40:08 +0000 (15:40 +0100)]
ci/bare-metal: Rename BM_KERNEL_MODULES to HWCI_KERNEL_MODULES
To try to make init more common.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Sun, 13 Jun 2021 12:55:36 +0000 (13:55 +0100)]
ci/lava: Explicitly start Xorg for Iris EGL tests
These tests relies on Xorg being started, so let's explicitly declare
that.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Sat, 12 Jun 2021 12:55:26 +0000 (13:55 +0100)]
ci/lava: Set PIGLIT_NO_WINDOW
This got lost in the move away from hardcoded environment variables, and
fixes the Iris EGL tests.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Sat, 12 Jun 2021 12:25:45 +0000 (13:25 +0100)]
ci/lava: Always upload Piglit replay images to MinIO
This should probably be set in the trace-job environments, but the
inheritance is a bit of a mess between all the systems at the moment,
and this matches previous hardcoded behaviour at least.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Daniel Stone [Sat, 12 Jun 2021 09:19:36 +0000 (10:19 +0100)]
ci/piglit: Fix path to uploaded images
Missed this bit when I was reworking environment variables.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reported-by: Emma Anholt <emma@anholt.net>
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329#note_956187
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Pierre-Eric Pelloux-Prayer [Thu, 6 May 2021 13:20:21 +0000 (15:20 +0200)]
radeonsi: use si_nir_is_output_const_if_tex_is_const
When a blending mode producing "color = src * dst" is used and we
can determine that dst is 1, then the draw call can dropped completely.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
Pierre-Eric Pelloux-Prayer [Wed, 5 May 2021 07:01:19 +0000 (09:01 +0200)]
radeonsi/nir: add si_nir_is_output_const_if_tex_is_const
Determine if a given shader write the same constant value to its output
if a specific input texture is replaced by constant load.
It's done by checking if the store_output intrinsics only depends on
constant and a texture. If it's true, the given texture is replaced by
a constant load in cloned shader and this clone is optimized.
Then the output is checked (= is it constant or not).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
Pierre-Eric Pelloux-Prayer [Wed, 19 May 2021 16:38:29 +0000 (18:38 +0200)]
radeonsi: use si_install_draw_wrapper for tmz handling
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
Pierre-Eric Pelloux-Prayer [Wed, 19 May 2021 15:11:57 +0000 (17:11 +0200)]
radeonsi: add si_install_draw_wrapper
This allows to implement custom draw_vbo code-path without
touching si_draw_vbo.
As an example, skipped all draw calls with an odd new_draws
could be done like this:
void mywrapper(...) {
if (new_draws % 2)
return;
return sctx->real_draw_vbo(...);
}
if (some_condition_is_met)
si_install_draw_wrapper(sctx, mywrapper);
Instead of having to add the "if ()" condition inside si_draw_vbo.
Note that a single wrapper may be installed so care must be taken
to not override an existing wrapper.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
Pierre-Eric Pelloux-Prayer [Fri, 7 May 2021 09:48:34 +0000 (11:48 +0200)]
radeonsi: add _once suffix to depth_cleared_level_mask
And add a new variable to disambiguate between "has been cleared once" and
"is cleared".
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
Marek Olšák [Sun, 13 Jun 2021 16:13:50 +0000 (12:13 -0400)]
gallium/u_threaded: merge draws faster by merging indexbuf unreferencing
Instead of N times decrementing the index buffer refcount by 1, decrement
it by N once.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11349>
Hyunjun Ko [Tue, 8 Jun 2021 06:49:45 +0000 (06:49 +0000)]
turnip: Copy command buffers to deferred submit request
To make sure the index of global bo table in drm_msm_gem_submit_cmd is
valid at actual submit time.
v1. Move the entry_count calculation into the submit request creation
function.
Fixes: #4877
Fixes:
3f229e34 ("turnip: Implement VK_KHR_timeline_semaphore.")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11260>
Dave Airlie [Mon, 14 Jun 2021 07:29:45 +0000 (17:29 +1000)]
crocus: fix scanout tiling so glamor/modesetting can work.
This fixes the scanout tiling to be like iris, with this X/glamor
can run.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11354>
Dave Airlie [Mon, 14 Jun 2021 02:37:41 +0000 (12:37 +1000)]
crocus: enable GL_EXT_memory_object feature on gen7
This is enabled by enabling gallium's memobj capability.
Ports
05cf1e7f36cb5337aea3467c730bac1b80494730 from iris
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
Dave Airlie [Mon, 14 Jun 2021 03:25:57 +0000 (13:25 +1000)]
crocus: plumb device/driver UUID generators
Ports
456fa9b8385b14d6f2d4bea16e89bf280c4d5b3f from iris.
Use the same generators as used in anv driver so both Vulkan and OpenGL
drivers can share the same external memory objects.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
Dave Airlie [Mon, 14 Jun 2021 02:34:45 +0000 (12:34 +1000)]
crocus: hook up resource creation from memory object
Port
772dc50d162f6ac99676ef5134607f0d0e6db21e from iris
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
Dave Airlie [Mon, 14 Jun 2021 02:27:49 +0000 (12:27 +1000)]
crocus: hook up memory object creation from handle
Port
cdb5a727644e9fd0195519f81ce34f79a99ae432 from iris
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
Dave Airlie [Mon, 14 Jun 2021 02:03:43 +0000 (12:03 +1000)]
crocus: Drop buffer support in resource_from_handle
Port
9d503b36ca24e1747e99a034e05700ad80c0682c from iris
The callers don't seem to pass targets of PIPE_BUFFER. Stop nesting an
if-else block by dropping support for this target.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
Dave Airlie [Sun, 13 Jun 2021 23:43:40 +0000 (09:43 +1000)]
crocus: introduce main resource configuration helper.
Along the lines of what iris does.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
Dave Airlie [Mon, 14 Jun 2021 01:51:37 +0000 (11:51 +1000)]
crocus: Make iris_bo_import_dmabuf take a modifier
Port
493298528a82e2ab7cf3ce6aed187fe19730e3d0 from iris
Replace the tiling parameter with a modifier parameter. I find it more
straightforward to have this function figure out the tiling from the
modifier than to have its caller do it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
Dave Airlie [Mon, 14 Jun 2021 01:41:37 +0000 (11:41 +1000)]
crocus: Don't call SET_TILING for dmabuf imports
This is a port of
c111e9099ceada50a2437e6e2e2a0f7cc6597448 from iris to
crocus.
Calling SET_TILING on a DMA buffer with the gen12 CCS modifier can fail
unnecessarily. The main surface in the BO is Y-tiled, but the CCS portion is
linear and can have a stride that's not a multiple of 128B. Because SET_TILING
is called on the CCS plane with I915_TILING_Y, the ioctl will sometimes reject
the stride.
SET_TILING was originally used in
b6d45e7f748e9ff7e198391f5ce5d1253101fedb to
fix an assertion failure in iris_resource_from_handle. Assigning the BO's
tiling_mode field is sufficient to avoid the failure.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
Andres Gomez [Tue, 1 Jun 2021 10:37:54 +0000 (13:37 +0300)]
ci: remove unzip from several containers that don't use it at all
Signed-off-by: Andres Gomez <agomez@igalia.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11110>
Marek Olšák [Sun, 6 Jun 2021 17:35:51 +0000 (13:35 -0400)]
gallium/u_threaded: use tc_drop_resource_reference in call_draw_single_drawid
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11335>
Marek Olšák [Thu, 20 May 2021 09:05:01 +0000 (05:05 -0400)]
gallium/u_threaded: clear valid buffer range only if it's not bound for write
We can't invalidate the range if a buffer is bound for write because we
would need to add the range that is bound, which we don't track.
This fixes buffer mappings incorrectly promoted to unsynchronized because
the valid range was cleared while the buffers were bound for write.
It also clears the valid range if the invalidation is allowed but skipped.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11335>
Marek Olšák [Sat, 12 Jun 2021 00:18:28 +0000 (20:18 -0400)]
gallium/u_threaded: don't update valid_buffer_range for read-only shader buffers
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11335>
Mike Blumenkrantz [Mon, 14 Jun 2021 19:20:58 +0000 (15:20 -0400)]
util/prim_restart: use more direct conversion for restart index
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11363>
Mike Blumenkrantz [Wed, 2 Jun 2021 19:43:43 +0000 (15:43 -0400)]
aux/tc: pass rebind count and rebind bitmask with replace_buffer_storage func
tc already calculates all the rebinding that needs to be done on a given
context, so (some of) this info can be passed on to drivers to enable
optimizations
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11245>
Michel Zou [Mon, 14 Jun 2021 08:14:32 +0000 (10:14 +0200)]
zink: Fix win32 build
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11338>
Michel Zou [Sun, 13 Jun 2021 17:36:53 +0000 (19:36 +0200)]
zink: Drop useless zink_dispatch_table
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11338>
Emma Anholt [Fri, 11 Jun 2021 21:40:06 +0000 (14:40 -0700)]
ci/piglit: Skip glx_arb_sync_control@timing.* on all systems.
The test involves timestamping to figure out how long a swap actually
takes, but if anything ends up rescheduling the process you can end up
spuriously failing. I could easily reproduce flakiness by just running a
loop accessing the filesystem in parallel with a loop running the test.
So, it's certainly not usable on a CI system with other piglit tests
running in parallel, and we don't want to run it if it's going to just
produce flake noise.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
Emma Anholt [Fri, 11 Jun 2021 21:21:06 +0000 (14:21 -0700)]
ci/piglit: Move the WGL skip to a common skips file.
This will also give us a central place to handle known CI issues for
piglit.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
Emma Anholt [Fri, 11 Jun 2021 21:14:54 +0000 (14:14 -0700)]
ci/deqp: Skip dEQP-VK.wsi.display.get_display_plane_capabilities
The flakiness of this test is due to CI running deqp in parallel, rather
than exposing any underlying driver issue. Just skip it in CI until we
come up with a reasonable way to handle tests to be run in isolation
during a deqp-runner run (likely as part of
https://gitlab.freedesktop.org/anholt/deqp-runner/-/issues/7).
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
Emma Anholt [Fri, 11 Jun 2021 21:11:22 +0000 (14:11 -0700)]
ci: Add a flakes IRC channel for llvmpipe/softpipe.
I'll watch this for deqp flake reports so we can stay on top of them (and
maybe expire those ancient softpipe annotations at some point).
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
Emma Anholt [Fri, 11 Jun 2021 21:10:14 +0000 (14:10 -0700)]
ci/softpipe: Move the flake to the flakes list.
These flake annotations in the skips list predated having flakes support.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
Emma Anholt [Fri, 11 Jun 2021 21:03:37 +0000 (14:03 -0700)]
ci/deqp: Skip flush_finish on all CI jobs.
They're too slow to run in CI even on non-tiled renderers, they don't
block conformance (unless you crash), and provide unreliable warning
results unless you isolate them from other activity on the system.
This means that the following jobs now skip these tests:
- deqp-iris-*
- deqp-llvmpipe (you know, the one mentioned in the comment!)
- deqp-virgl-gl
- deqp-zink-lvp
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
Emma Anholt [Fri, 11 Jun 2021 20:53:51 +0000 (13:53 -0700)]
ci/deqp: Drop stress/perf skips lists.
The mustpass doesn't have any tests matching these, so no need to
skip. These tests only show up if you run without using a mustpass list.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
Andres Gomez [Mon, 14 Jun 2021 13:20:07 +0000 (16:20 +0300)]
ci: bump x86_test-base tag
When adding crosvm to the x86_test-gl building deqp-runner was also
mistakenly introduced. deqp-runner is already included in the
x86_test-base image.
Additionally, when bumping the deqp-runner version, only the
x86_test-gl tag was updated.
Now, we remove the unnecessary build from x86_test-gl and bump the tag
for the x86_test-base image.
v2:
- Bump x86_test-gl, not x86_test-vk (Tomeu).
v3: add in fixes for duplicated lines in lvp xfails (Anholt)
Fixes:
dc9cd18f522 ("ci: Build Crosvm in our container")
Fixes:
53826932db5 ("ci: Update piglit and deqp/piglit-runner.")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11359>
Emma Anholt [Sat, 12 Jun 2021 00:07:31 +0000 (17:07 -0700)]
ci: Disable Xorg's screensaver entirely.
The screensaver kicks in at 10 minutes and obscures the screen,
independent of dpms. This causes piglit tests to get flaky (swaps start
taking a whole second, and swapbuffersmsc-divisor-zero times out at
exactly the wrong time) and slow if the run takes longer than 10 minutes.
Hopefully with this we'll see some piglit glx flakes go away forever, it
did seem to for this test locally.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11334>
Alexander Monakov [Fri, 11 Jun 2021 20:56:17 +0000 (23:56 +0300)]
freedreno/drm-shim: keep GEM buffers page-aligned
Trying to run turnip under drm-shim reveals that pretended device
offsets are not sufficiently aligned, failing this assert in tu_pipeline.c:
/* emit program binary & private memory layout
* binary_iova should be aligned to 1 instrlen unit (128 bytes)
*/
assert((binary_iova & 0x7f) == 0);
Round up BO size to 4096 in msm_ioctl_gem_new to avoid this (the kernel
aligns to page size).
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11331>
Alexander Monakov [Fri, 11 Jun 2021 20:29:57 +0000 (23:29 +0300)]
freedreno/drm-shim: pretend to offer DRM 1.6.0
turnip's DRM device interface requires version 1.6 (for SYNCOBJ).
To unblock use of turnip over drm-shim, raise shim's version to 1.6.
This allows to see shader disassembly, while submission fails with
DRM_SHIM: unhandled core DRM ioctl 0xC4 (0xc01064c4)
TU: error: DRM_IOCTL_SYNCOBJ_RESET failure: Invalid argument
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11331>
Rhys Perry [Wed, 9 Jun 2021 19:10:51 +0000 (20:10 +0100)]
aco/lower_phis: don't allocate unused temporary ids
The excessive number of temporary IDs caused #4872's live-out sets to be
extremely large and expensive to iterate.
With this change, #4872's shader is much faster to compile and uses much
less memory.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4872
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11300>
Rhys Perry [Thu, 10 Jun 2021 10:23:56 +0000 (11:23 +0100)]
aco/lower_phis: fix undef_operands initialization with >32 predecessors
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11300>
Samuel Pitoiset [Tue, 8 Jun 2021 14:18:20 +0000 (16:18 +0200)]
radv: fix dynamic rasterizer discard enable state
If a pipeline enables rasterizerDiscardEnable statically we have to
properly initialize the value, otherwise it won't be updated when a
new pipeline is bound.
Fixes few dEQP-VK.pipeline.extended_dynamic_state.*disable_raster.
Fixes:
dd19bf9d7dd ("radv: implement dynamic rasterizer discard enable")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11242>
Rhys Perry [Fri, 27 Nov 2020 16:37:07 +0000 (16:37 +0000)]
aco: move VMEM instructions below descriptor loads
This is to prevent sequences like:
a = descriptor_load()
vmem(a)
b = descriptor_load()
vmem(b)
and instead create:
a = descriptor_load()
b = descriptor_load()
vmem(a)
vmem(b)
fossil-db (GFX10.3):
Totals from 114521 (78.30% of 146267) affected shaders:
VGPRs: 4540352 -> 4540216 (-0.00%); split: -0.03%, +0.02%
CodeSize:
289864228 ->
289114652 (-0.26%); split: -0.29%, +0.03%
MaxWaves: 2940234 -> 2940338 (+0.00%); split: +0.00%, -0.00%
Instrs:
55112418 ->
54919910 (-0.35%); split: -0.38%, +0.03%
Latency:
956528393 ->
954682011 (-0.19%); split: -0.24%, +0.05%
InvThroughput:
229280830 ->
229238107 (-0.02%); split: -0.04%, +0.02%
VClause: 1141832 -> 1139002 (-0.25%); split: -0.63%, +0.38%
SClause: 2357840 -> 2225008 (-5.63%); split: -6.01%, +0.38%
Copies: 3316040 -> 3331519 (+0.47%); split: -0.31%, +0.77%
Branches: 1187212 -> 1186919 (-0.02%); split: -0.03%, +0.01%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6489>
Rhys Perry [Fri, 27 Nov 2020 17:26:46 +0000 (17:26 +0000)]
aco: don't move descriptor loads below buffer loads
fossil-db (GFX10.3):
Totals from 52870 (36.15% of 146267) affected shaders:
VGPRs: 2109936 -> 2110056 (+0.01%); split: -0.01%, +0.01%
CodeSize:
134898056 ->
134812748 (-0.06%); split: -0.08%, +0.02%
MaxWaves: 1347354 -> 1347346 (-0.00%)
Instrs:
25598063 ->
25575415 (-0.09%); split: -0.11%, +0.02%
Latency:
432491613 ->
432047723 (-0.10%); split: -0.12%, +0.02%
InvThroughput:
90940977 ->
90927545 (-0.01%); split: -0.03%, +0.01%
VClause: 570039 -> 570019 (-0.00%); split: -0.05%, +0.04%
SClause: 1145076 -> 1139040 (-0.53%); split: -0.60%, +0.07%
Copies: 1513949 -> 1513102 (-0.06%); split: -0.32%, +0.26%
Branches: 524279 -> 524275 (-0.00%); split: -0.03%, +0.03%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6489>
Rhys Perry [Mon, 14 Jun 2021 13:45:22 +0000 (14:45 +0100)]
aco/ra: use adjust_max_used_regs() in compact_relocate_vars()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6489>
Samuel Pitoiset [Wed, 9 Jun 2021 14:10:59 +0000 (16:10 +0200)]
radv/winsys: remove useless errno.h includes
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11269>
Samuel Pitoiset [Wed, 9 Jun 2021 14:09:32 +0000 (16:09 +0200)]
radv/winsys: adjust some error messages
Report the return code from libdrm instead of errno. While we are at it,
fix the function name in radv_amdgpu_wait_timeline_syncobj().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11269>
Bas Nieuwenhuizen [Mon, 2 Nov 2020 01:09:11 +0000 (02:09 +0100)]
gallium/va: Add support for PRIME_2 import.
That way we can actually import surfaces with modifiers & metadata
planes.
Tested with patches for ffmpeg to use this with kmsgrab & modifiers.
For AMD & multiplanar formats we always have 1 format plane = 1
memory plane, even with modifiers.
Intel (non Gallium) does have 1 format plane is 2 memory planes
for some modifiers with NV12. Currently with Gallium we don't really
have info about layer/plane ordering so this manually orders things
so that they align with Intel.
This shouldn't impact other drivers as without modifiers with metadata
planes this should give equivalent behavior to the old import path.
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10815>
Bas Nieuwenhuizen [Sun, 1 Nov 2020 23:16:29 +0000 (00:16 +0100)]
gallium/vl: Use format plane count for sampler view creation.
Extra memory planes don't need a sampler.
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10815>
Bas Nieuwenhuizen [Fri, 14 May 2021 12:08:12 +0000 (14:08 +0200)]
radv: Allow DCC images to be compressed with foreign queues.
Otherwise we would always decompress when transitioning to the
foreign queue.
Fixes:
8b9033ad0a0 ("radv: Support DCC modifiers fully.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10802>
Bas Nieuwenhuizen [Fri, 14 May 2021 12:04:11 +0000 (14:04 +0200)]
radv: Actually return correct value for read-only DCC compressedness.
Most stuff that depends on the value wouldn't be triggered anyway but
...
Fixes:
b5ecf0748a5 ("radv: Ensure we never decompress or FCE read-only textures.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10802>
Bas Nieuwenhuizen [Fri, 14 May 2021 11:57:11 +0000 (13:57 +0200)]
radv: Don't skip barriers that only change queues.
We depend on the queue mask for some decisions ...
CC: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10802>
Rhys Perry [Fri, 12 Feb 2021 10:49:03 +0000 (10:49 +0000)]
aco: adjust the condition for expanding vertex fetch data format
Instead of avoiding out-of-bounds access, avoid creating a load larger
than the original attribute. This should work just as well, since the only
situations expending a load helped was because we shrunk it first.
Also fixes a bug where a 3 component load (4 components with the first
component skipped) would be incorrectly expanded to 4 components because
the stride check would never be performed. Maybe we should avoid skipping
the first component in some situations, but I'm not sure if it's worth
the VGPR cost.
fossil-db (vega10):
Totals from 583 (0.39% of 149974) affected shaders:
CodeSize: 1496848 -> 1500868 (+0.27%); split: -0.03%, +0.30%
Instrs: 286155 -> 286575 (+0.15%); split: -0.07%, +0.22%
Latency: 2947101 -> 2946865 (-0.01%); split: -0.23%, +0.22%
InvThroughput: 797396 -> 797127 (-0.03%); split: -0.08%, +0.04%
fossil-db (polaris10):
Totals from 583 (0.39% of 151365) affected shaders:
SGPRs: 38880 -> 39216 (+0.86%)
VGPRs: 24440 -> 24356 (-0.34%)
CodeSize: 1506808 -> 1510876 (+0.27%); split: -0.01%, +0.28%
Instrs: 288735 -> 289167 (+0.15%); split: -0.06%, +0.21%
Latency: 2963263 -> 2961884 (-0.05%); split: -0.24%, +0.19%
InvThroughput: 802351 -> 801665 (-0.09%); split: -0.12%, +0.04%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9007>
Rhys Perry [Fri, 12 Feb 2021 10:48:58 +0000 (10:48 +0000)]
radv,aco: use all attributes in a binding to obtain an alignment for fetch
Instead of assuming scalar alignment for an attribute, we can use the
required alignment of other attributes in a binding to expect a higher
one.
This uses the alignment of all attributes in the pipeline, not just the
ones loaded. This can create slightly better code, but could break
pipelines which relied on unused (and unaligned) attributes no being
loaded. I don't think such pipelines are allowed by the spec.
fossil-db (Sienna Cichlid):
Totals from 44350 (30.32% of 146267) affected shaders:
VGPRs: 1694464 -> 1700616 (+0.36%); split: -0.08%, +0.44%
CodeSize:
60207184 ->
58093836 (-3.51%); split: -3.51%, +0.00%
MaxWaves: 1175998 -> 1174948 (-0.09%); split: +0.02%, -0.11%
Instrs:
11763444 ->
11458952 (-2.59%); split: -2.60%, +0.01%
Latency:
70679612 ->
67062215 (-5.12%); split: -5.27%, +0.15%
InvThroughput:
11482495 ->
11362911 (-1.04%); split: -1.20%, +0.16%
VClause: 359459 -> 343248 (-4.51%); split: -6.36%, +1.85%
SClause: 422404 -> 419229 (-0.75%); split: -1.17%, +0.42%
Copies: 754384 -> 764368 (+1.32%); split: -1.74%, +3.06%
Branches: 197472 -> 197474 (+0.00%); split: -0.03%, +0.03%
PreVGPRs: 1215348 -> 1215503 (+0.01%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9007>
Tomeu Vizoso [Mon, 14 Jun 2021 07:35:56 +0000 (09:35 +0200)]
Revert "ci: Disable the iris APL jobs"
This reverts commit
209c82977572dc73cc5c022be3949e1600fba05e.
They are stable now.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11355>
Iago Toral Quiroga [Thu, 10 Jun 2021 11:17:45 +0000 (13:17 +0200)]
v3dv: handle Vulkan 1.1 feature and property queries
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11316>
Hyunjun Ko [Mon, 7 Jun 2021 04:59:32 +0000 (04:59 +0000)]
turnip: add missing VKAPI_ATTR/CALL
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11099>
Dave Airlie [Wed, 2 Jun 2021 19:52:40 +0000 (05:52 +1000)]
ci: add crocus to the build tests
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11146>