mesa: add KHR_no_error support for glCompressedTex*SubImage3D()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add 3D support to compressed_tex_sub_image() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add KHR_no_error support for glCompressedTex*SubImage2D()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add 2D support to compressed_tex_sub_image() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add KHR_no_error support for CompressedTex*SubImage1D()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add compressed_tex_sub_image() helper

This reduces duplication between the dsa and non-dsa function
and will also be used in the following commit to add
KHR_no_error support.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: make _mesa_compressed_texture_sub_image() static

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add KHR_no_error support for NamedFramebufferTexture

V3: use frame_buffer_texture() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add KHR_no_error support for FramebufferTexture

V3: use the frame_buffer_texture() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add *FramebufferTexture() support to frame_buffer_texture helper

V2: call check_layered_texture_target() even for no_error

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add KHR_no_error support for NamedFramebufferTextureLayer

v3: use frame_buffer_texture_layer() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add KHR_no_error support for FramebufferTextureLayer

V3: use frame_buffer_texture_layer() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add no error support to frame_buffer_texture_layer() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add frame_buffer_texture_layer() helper

To be used to add KHR_no_error support while sharing code between
the DSA and non-DSA OpenGL function.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add KHR_no_error support for glUseProgram

V3: use always_inline attribute (Suggested by Nicolai)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: move use_program() inside _mesa_use_program()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

intel/isl/gen6: Fix combined depth stencil alignment

All combined depth stencil buffers (even those with just stencil)
require a 4x4 alignment on Sandy Bridge.  The only depth/stencil buffer
type that requires 4x2 is separate stencil.

Reviewed-by: Chad Versace <chadversary@chromium.org>

intel/isl: Refactor gen8_choose_image_alignment_el

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

intel/isl: Refactor gen6_choose_image_alignment_el

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

intel/isl: Refactor gen7_choose_image_alignment_el

The Ivy Bridge PRM provides a nice table that handles most of the
alignment cases in one place.  For standard color buffers we have a
little freedom of choice but for most depth, stencil and compressed it's
hard-coded.  Chad's original functions split halign and valign apart and
implemented them almost entirely based on restrictions and not the
table.  This makes things way more confusing than they need to be.  This
commit gets rid of the split and makes us implement the exact table
up-front.  If our surface isn't one of the ones in the table then we
have to make real choices.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4

The reasoning Chad gave in the comment for choosing a valign of 4 is
entirely bunk.  The fact that you have to multiply pitch by 2 is
completely unrelated to the halign/valign parameters used for texture
layout.  (Not completely unrelated.  W-tiling is just Y-tiling with a
bit of extra swizzling which turns 8x8 W-tiled chunks into 16x4 y-tiled
chunks so it makes everything easier if miplevels are always aligned to
8x8.)  The fact that RENDER_SURFACE_STATE::SurfaceVerticalAlignmet
doesn't have a VALIGN_8 option doesn't matter since this is gen7 and you
can't do stencil texturing anyway.

v2 (Jason Ekstrand):
 - Delete most of Chad's comment and add a more descriptive commit
   message.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>

freedreno/gmem: fix hw binning hangs with large render targets

On all 3 gens, we have 4 bits for width and height in the VSC pipe
config.  And overflow results in setting width and/or height to zero
which causes hangs.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: fix crash with atomics

Atomics can have a result value.  And sometimes it is even used.

Signed-off-by: Rob Clark <robdclark@gmail.com>

mesa/st: fix yuv EGLImage's

Don't reject YUV formats that the driver doesn't handle natively, since
mesa/st already knows how to lower this in shader.

Reported-by: Nicolas Dechesne <ndec@linaro.org>
Fixes: 83e9de2 ("st/mesa: EGLImageTarget* error handling")
Cc: 17.1 <mesa-stable@lists.freedesktop.org
Signed-off-by: Rob Clark <robdclark@gmail.com>
Tested-by: Nicolas Dechesne <ndec@linaro.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ttn: fix dest size for some texture instructions

Some, like lod, don't return 4 components.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

ttn: fix txd src sizes

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

ttn: fix txs dest size

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

freedreno/a5xx: remove unneeded assert

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: fallback to slow-clear for z32

We probably *could* do this with blit path, but I think it would involve
clobbering settings from batch->gmem (see emit_zs()).

Signed-off-by: Rob Clark <robdclark@gmail.com>

etnaviv: increment the resource seqno in resource_changed

Just increment the resource seqno instead of setting the texture
seqno to be lower by one than the resource seqno.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: clean up sampler view reference counting

Use the proper pipe_resource_reference function instead of
rolling our own.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: apply feature overrides in one central location

This way we can just test the feature bits and don't need to spread
the debug overrides to all locations touching a feature.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: allow R/B swapped surfaces to be cleared

Fixes: 7f62ffb68ad ("etnaviv: add support for rb swap")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: stop oversizing buffer resources

PIPE_BUFFER is a target enum, not a binding. This caused the driver to
up-align the height of buffer resources, leading to largely oversizing
those resources. This is especially bad, as the buffer resources used
by the upload manager are already 1MB in size. Height alignment meant
that those would result in 4 to 8MB big BOs.

Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

i965: Fix test_eu_validate.cpp

Broken by commit a7217e909ce6 ("i965: Pass pointer and end of assembly
to brw_validate_instructions").

Reported-by: Aaron Watry <awatry@gmail.com>

anv: Implement VK_KHR_get_surface_capabilities2

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

vulkan/wsi/wayland: Add support for VK_KHR_get_surface_capabilities2

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

vulkan/wsi/x11: Add support for VK_KHR_get_surface_capabilities2

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

vulkan/wsi: Add get_capabilities2 and get_formats2d interface pointers

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

vulkan/wsi: Use vk_outarray for surface_get_formats

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

vulkan: Update registry and headers to 1.0.49

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

radeonsi: extract TGSI memory/texture opcode handling into its own file

It's about time to get the growth of si_shader.c somewhat under control.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: make const_array externally accessible

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: make get_bounded_indirect_index externally accessible

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: make emit_waitcnt externally accessible

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: silence a Coverity warning

Coverity doesn't understand that we'll never pass non-NULL for vertex
shaders.

This is a bit lame, actually. A straightforward cross-procedural analysis
limited to this source file should be enough to prove that there's no
NULL-pointer dereference. Oh well.

CID: 1405999
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: rename tcs_tes_uses_prim_id for clarity

What we care about is whether PrimID is used while tessellation is
enabled; whether it's used in TCS/TES or further down the pipeline is
irrelevant.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix gl_PrimitiveIDIn in geometry shader when using tessellation

This builds on commit 0549ea15ec38 ("radeonsi: fix primitive ID in
fragment shader when using tessellation").

Fixes piglit
arb_tessellation_shader/execution/gs-primitiveid-instanced.shader_test

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/debug: handle index field in SET_*_REG correctly

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: simplify link_assign_uniform_storage() a bit

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: unify _mesa_uniform() for image uniforms

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: fix indentation in _mesa_uniform()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: fix indentation in _mesa_associate_uniform_storage()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: replace _mesa_problem() with unreachable() in pack.c

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: replace _mesa_problem() with unreachable() in mipmap.c

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: replace _mesa_problem() with unreachable() in _mesa_convert_colors()

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: replace _mesa_problem() with unreachable() in _mesa_light()

All drivers but the old nouveau dri driver return after this anyway.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: replace _mesa_problem() with assert() in hash table

There should be no way the OpenGL test suites don't hit the assert()
should we do something to cause this code path to be taken.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: don't crash in KHR_no_error uniform variants when location == -1

From Seciton 7.6 (UNIFORM VARIABLES) of the OpenGL 4.5 spec:

  "If the value of location is -1, the Uniform* commands will
  silently ignore the data passed in, and the current uniform values
  will not be changed.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

intel/aubinator_error_decode: Disassemble shader programs

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/aubinator_error_decode: Stop decoding after MI_BATCH_BUFFER_END

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/tools: Refactor gen_disasm_disassemble() to use annotations

Which will allow us to print validation errors found in shader assembly
in GPU hang error states.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/decoder: Fix indentation

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

genxml: Remove brackets from kernel start pointer names

Newer Gens' names don't have the brackets. Having common names will make
some later patches simpler.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

i965: Add a weak no-op nir_print_instr() symbol

intel_asm_annotation.c is part of libintel_compiler.la, which contains
code for disassembling and validating shaders that we want to call in
aubinator_error_decode.

dump_assembly() calls nir_print_instr() to print annotations, and
although dump_assembly() is not called by aubinator_error_decode (nor is
any function in intel_asm_annotation.c) it causes undefined references
to nir_print_instr().

To work around, provide a no-op weak symbol to resolve against.

i965: Allow brw_eu_validate to handle compact instructions

This will allow the validator to run on shader programs we find in the
GPU hang error state.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Pass pointer and end of assembly to brw_validate_instructions

This will allow us to more easily run brw_validate_instructions() on
shader programs we find in GPU hang error states.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Mark shader programs for capture in the error state.

When the GPU hangs, the kernel saves some state for us. Until now it has
not included the shader programs, which are very often the reason the
GPU hang occurred. With the programs saved in the error state, we should
be more capable of debugging hangs.

Thanks to Chris Wilson and Ben Widawsky who provided the kernel support
for this feature ("drm/i915: Copy user requested buffers into the error
state"), which will be in kernel v4.13.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

egl: fix android logger compilation

1ce5853 broken compilation since LOG_ERROR is not defined and also
macro expansion won't work as planned (expands to 'ANDROID_egl2alog[level]')

v2: append 'ANDROID' to egl2alog table and use LOG_PRI
    (suggested by Chih-Wei Huang)

Fixes: 1ce5853 ("egl: simplify the Android logger")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: perf: fix pointer to integer cast

v2: Just use cast to uintptr_t (Chris)

Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

intel: gen-decoder: fix xml parser leak

In the unlikely case the parsing of genxml files fails, we were
leaking an xml parser object.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

radeonsi: enable threaded_context

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/u_threaded: drop and ignore all non-async debug callbacks

This is necessary to comply with OpenGL.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add threaded context counter monitoring for HUD

"tc" will be initialized by the next commit.

v2: rename stuff according to v2 changes in u_threaded_context

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

radeonsi: implement replace_buffer_storage for the threaded context

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/radeon: subclass and handle threaded_query

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/radeon: subclass threaded_transfer

v2: use assert on rtransfer->b.staging

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/radeon: subclass threaded_resource

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/radeon: handle other map buffer flags from the threaded context

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/radeon: handle TC_TRANSFER_MAP_THREADED_UNSYNC

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/radeon: unwrap a context if we get a wrapped one

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/radeon: require both WRITE and FLUSH_EXPLICIT in buffer_flush_region

spotted randomly.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/util: add threaded_context as a pipe_context wrapper

v2: - rename num_calls -> num_call_slots (for tc_call)
    - rename num_calls -> num_total_call_slots (for tc_batch)
    - rename num_offloaded/direct_calls -> num_offloaded/direct_slots
    - declare slot[0] instead of slot[1]
    - remove no-op leftover code from tc_draw_vbo
    - use tc_set_resource_reference to fill threaded_transfer
    - fix map flags for sparse buffers
    - cosmetic changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium/u_upload: add u_upload_clone

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

gallium: add flag PIPE_CONTEXT_PREFER_THREADED

State trackers can set this to tell the driver when u_threaded_context is
desirable.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

radeonsi/gfx9: add support for Raven

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd/addrlib: import Raven support

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

renderonly: Initialize fields of struct winsys_handle.

vc4 was rejecting renderonly's import, because the offset field was
nonzero.

Fixes: 848b49b288f ("gallium: add renderonly library")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

Revert "freedreno: use bypass if only clears"

Causing issues with stk on a4xx.. still probably a good idea, but seems
some debugging is needed first.

This reverts commit 3ab072d3c8643c66d8e07e63df970b792728bac6.

freedreno: fix crash when flush() but no rendering

If we haven't created a batch, just bail in pipe->flush(), since there
is nothing to do.

Fixes crash in warsow, which creates a whole bunch of contexts used for
nothing but texture uploads.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: fix indexbuffer upload

My fault for not having time to test Marek's patches while they were on
list.

Fixes: 330d0607 ("gallium: remove pipe_index_buffer and set_index_buffer")
Signed-off-by: Rob Clark <robdclark@gmail.com>

radv: Save descriptor set even if vertex buffers are not saved.

Totally independent.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: 0e6d532d327 "radv/meta: add support for save/restore meta without vertex data."

freedreno/a5xx: hw binning support

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: use bypass if only clears

Some things trigger batches that only contain a clear (like glmark2
startup).  No point to use GMEM for this.

Signed-off-by: Rob Clark <robdclark@gmail.com>

nv50/ir: Report wrong prog types using proper var

Coverity caught the use of the uninitialised variable `type`.
However, it was `info->type`, which is initialised, which was meant to
be used.

CID: 1406000
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Fixes: b490ca9a387d ("nv50/ir: Fail if encountering unknown shader type")
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: fix KHR_no_error SSO support

Fixes: 00c5119a5e821 ("mesa: add KHR_no_error support for glUseProgramStages()")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

docs: update calendar, add news item and link release notes for 17.0.6

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add sha256 checksums for 17.0.6

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 6a680243fcef4509372941d5c4c50b82c3aaa8ed)

docs: add release notes for 17.0.6

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 08abf3a2a2ca8733fb75277d41f2196fe899f129)