Chenbing Zheng [Tue, 17 May 2022 08:42:42 +0000 (16:42 +0800)]
[InstCombine] precommit tests for foldSelectToCopysign
Samuel Thibault [Tue, 17 May 2022 08:44:07 +0000 (08:44 +0000)]
[llvm] Fix typo for libxml2 detection
This seems to be a copy-paste from the similar zlib detection code.
Patch By: sthibaul
Differential Revision: https://reviews.llvm.org/D117052
esmeyi [Tue, 17 May 2022 08:27:47 +0000 (04:27 -0400)]
[XCOFF] support writing sections, relocations and symbols for XCOFF64.
This is the second patch to enable the XCOFF64 object writer.
Reviewed By: jhenderson, shchenz
Differential Revision: https://reviews.llvm.org/D122287
Nikita Popov [Tue, 17 May 2022 08:18:38 +0000 (10:18 +0200)]
[LVI] Compute range for xor
We do have a non-trivial implementation for binaryXor() now.
Nikita Popov [Tue, 17 May 2022 08:17:34 +0000 (10:17 +0200)]
[CVP] Add test for xor (NFC)
Nikita Popov [Tue, 17 May 2022 08:02:50 +0000 (10:02 +0200)]
[ConstantRange] Implement binaryXor() using known bits
This allows us to compute known high bits. It's not optimal, but
better than nothing.
Fraser Cormack [Wed, 11 May 2022 13:08:41 +0000 (14:08 +0100)]
[RISCV] Add a test w/ RVV stack objects misaligning non-RVV ones
This patch adds a simple test which demonstrates a miscompilation of
16-byte-aligned scalar (non-RVV) objects when combined with RVV stack
objects.
The RISCV stack is assumed to be aligned to 16 bytes, and this is
guaranteed/assumed to be true when setting up the stack. However, when
the stack contains RVV objects, we decrement the stack pointer by some
multiple of vlenb, which is only guaranteed to be aligned to 8 bytes.
This means that non-RVV objects specifically requiring 16-byte alignment
fall through the cracks and are misaligned. Objects requiring larger
alignment trigger stack realignment and thus should be okay.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D125382
Fraser Cormack [Mon, 16 May 2022 15:38:52 +0000 (16:38 +0100)]
[StackColoring] Don't merge slots with differing StackIDs
The documentation for this specifically mentions that this should not
happen. We could think about adding target hooks to permit it (and how
to merge IDs) in the future if that is desirable.
This specific test case was merging a scalable-vector slot into a
non-scalable one and dropping the notion of scalability, meaning we
failed to allocate enough stack space for the object.
Reviewed By: arsenm, MaskRay, sdesmalen
Differential Revision: https://reviews.llvm.org/D125699
Nikita Popov [Mon, 16 May 2022 15:20:19 +0000 (17:20 +0200)]
[KnownBits] Add operator==
Checking whether two KnownBits are the same is somewhat common,
mainly in test code.
I don't think there is a lot of room for confusion with "determine
what the KnownBits for an icmp eq would be", as that has a
different result type (this is what the eq() method implements,
which returns Optional<bool>).
Differential Revision: https://reviews.llvm.org/D125692
Peixin-Qiao [Tue, 17 May 2022 07:11:46 +0000 (15:11 +0800)]
[flang] Add one semantic check for elemental call arguments
As Fortran 2018 15.8.1(3), in a reference to an elemental procedure, if
any argument is an array, each actual argument that corresponds to an
INTENT (OUT) or INTENT (INOUT) dummy argument shall be an array. Add
this semantic check.
Reviewed By: klausler
Differential Revision: https://reviews.llvm.org/D125685
Peixin-Qiao [Tue, 17 May 2022 07:07:52 +0000 (15:07 +0800)]
[flang][OpenMP] Support lowering to MLIR for ordered clause
This supports the lowering parse-tree to MLIR for ordered clause in
worksharing-loop directive. Also add the test case for operation
conversion.
Part of this patch is from the fir-dev branch of
https://github.com/flang-compiler/f18-llvm-project.
Co-authored-by: Sourabh Singh Tomar <SourabhSingh.Tomar@amd.com>
Reviewed By: kiranchandramohan, NimishMishra
Differential Revision: https://reviews.llvm.org/D125456
luxufan [Tue, 17 May 2022 06:06:42 +0000 (14:06 +0800)]
[RISCV] Support getHostCpuName for sifive-u74
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D123978
jacquesguan [Mon, 16 May 2022 09:19:17 +0000 (09:19 +0000)]
[mlir][LLVMIR] Add support for translating insertelement/extractelement.
Add support for translating llvm::InsertElement and llvm::ExtractElement.
Differential Revision: https://reviews.llvm.org/D125674
Chuanqi Xu [Thu, 12 May 2022 10:00:45 +0000 (18:00 +0800)]
[Frontend] [Coroutines] Emit error when we found incompatible allocation
function in promise_type
According to https://cplusplus.github.io/CWG/issues/2585.html, this
fixes https://github.com/llvm/llvm-project/issues/54881
Simply, the clang tried to found (do lookup and overload resolution. Is
there any better word to use than found?) allocation function in
promise_type and global scope. However, this is not consistent with the
standard. The standard behavior would be that the compiler shouldn't
lookup in global scope in case we lookup the allocation function name in
promise_type. In other words, the program is ill-formed if there is
incompatible allocation function in promise type.
Reviewed By: erichkeane
Differential Revision: https://reviews.llvm.org/D125517
Mitch Phillips [Tue, 17 May 2022 02:07:22 +0000 (19:07 -0700)]
Revert "[dwarf] Emit a DIGlobalVariable for constant strings."
This reverts commit
4680982b36a84770a1600fc438be8ec090671724.
Broke a fuchsia windows bot. More details in the review:
https://reviews.llvm.org/D123534
Vy Nguyen [Tue, 17 May 2022 00:53:27 +0000 (20:53 -0400)]
[nfc][lld-macho] Follow up fixes to
bd9e46815d73e4236c207bad8b5c54e7188154d7
Need -DAG in the first expect statement too
wren romano [Mon, 16 May 2022 23:45:50 +0000 (16:45 -0700)]
[mlir][sparse] Moved _mlir_ciface_newSparseTensor closer to its macros
This is a followup to D125431, to keep from confusing the machinery that generates diffs (since combining these two changes into one would obfuscate the changes actually made in the previous differential).
Depends On D125431
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D125432
Thomas Lively [Tue, 17 May 2022 00:51:45 +0000 (17:51 -0700)]
[WebAssembly] Update relaxed SIMD opcodes and names
to reflect the latest state of the proposal:
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md#binary-format.
Moves code around to match the instruction order from the proposal, but the only
functional changes are to the names and opcodes.
Reviewed By: aheejin
Differential Revision: https://reviews.llvm.org/D125726
Vy Nguyen [Tue, 17 May 2022 00:46:15 +0000 (20:46 -0400)]
[nfc][lld-macho] Fixed test from https://reviews.llvm.org/D125732
Details:
The test was incorrectly expecting the error messages for the export symbols to have a particular order.
It shouldn't because the export symbol list is processed concurrently.
Vy Nguyen [Tue, 17 May 2022 00:36:49 +0000 (20:36 -0400)]
[lld-macho] Temporarily disable test on windows
The metadata seems to be demangled differently
Philip Reames [Mon, 16 May 2022 23:43:13 +0000 (16:43 -0700)]
[RISCV] Use classic dataflow for VSETVLI insertion
Our current implementation of the InsertVSETVLI dataflow allows phase 3 to arrive at a different block end state than the data flow in phase 1/2 computed. This arises because a block which contains instructions (e.g. load or stores) which don't consume all the incoming bits of the VL/VTYPE can be compatible with multiple incoming states. The algorithm effectively changes the SEW on such instructions, and propagates the prior state forward. As phase 3 uses the block input state for this propagation, but phase 1/2 doesn't, this can result in different block end states.
If we don't correct for it, this discrepancy can result in miscompiles. This was the source of multiple recent bugs. However, by now we have fixes for all known correctness issues.
The basic strategy we use is to insert a compensation vsetvli to bring the block state leaving the block back into consistency with the one computed. This is correct, but results in extra vsetvlis being placed at the end of blocks.
This change adjusts the phase 1/2 algorithm to propagate the incoming block state through the block, allowing the compatibility rules to modify the end state. The algorithm may need to run slightly more iterations, but the end result is consistent with what phase 3 does.
The benefit of doing this is two fold.
First, we reverse some of the code quality introductions introduced in the functional fixes.
Second, we simplify the invariants, and allow the strict assertions to be enabled. Several humans, myself included, have found it quite surprising that invariant didn't hold already, and arguably that confusion is the cause of several of our recent miscompiles in this code.
The downside to this patch is that the dataflow may require additional iterations to stabilize. In the worse case, we go from O(Edges) to O(E + UniquePaths) as the incoming state (and thus the outgoing one) can now change once for each path from the entry block.
Differential Revision: https://reviews.llvm.org/D125232
Philip Reames [Mon, 16 May 2022 23:40:35 +0000 (16:40 -0700)]
[RISCV] Fix missing vsetvli in transparent block case
We've got a lurking problem with our data flow implementation where different phases disagree, resulting in possible miscompiles. D119518 introduced a workaround, but failed to consider blocks which only contain load/stores compatible with their incoming state.
When I went to rebase and simplify D125232, it turned out that not all of the correctness issues had been fixed yet after all. This is the correctness fix accidentally embedded in the original more complicated version.
Note that the test changes here are mostly regressions. It's worth noting that the simplified version of D125232 exactly reverses all the non-functional diffs in the test caused here. D125232 should be the immediate following commit.
Differential Revision: https://reviews.llvm.org/D125703
Grace Jennings [Mon, 16 May 2022 23:50:49 +0000 (16:50 -0700)]
[test-suite][cmake] sort unit test targets
This patch sorts unit test targets into directories corresponding to the
test source file directories to improve target navigation.
Reviewed By: smeenai
Differential Revision: https://reviews.llvm.org/D124810
Mitch Phillips [Mon, 16 May 2022 23:03:47 +0000 (16:03 -0700)]
[dwarf] Emit a DIGlobalVariable for constant strings.
An upcoming patch will extend llvm-symbolizer to provide the source line
information for global variables. The goal is to move AddressSanitizer
off of internal debug info for symbolization onto the DWARF standard
(and doing a clean-up in the process). Currently, ASan reports the line
information for constant strings if a memory safety bug happens around
them. We want to keep this behaviour, so we need to emit debuginfo for
these variables as well.
Reviewed By: dblaikie, rnk, aprantl
Differential Revision: https://reviews.llvm.org/D123534
Vy Nguyen [Mon, 16 May 2022 23:19:32 +0000 (19:19 -0400)]
[lld-macho] Demangle symbol names in export-symbol error messages when -demangle is specified.
PR/55512
Reviewed By: keith
Differential Revision: https://reviews.llvm.org/D125732
River Riddle [Mon, 16 May 2022 23:45:51 +0000 (16:45 -0700)]
[mlir][NFC] Fix the tags for various doc code blocks
River Riddle [Mon, 16 May 2022 23:37:31 +0000 (16:37 -0700)]
[mlir][PDLL] Tweak the grammar to highlight partial code better
This commit enables proper highlighting when inner statements are
outside of a constraint/pattern/etc. This shouldn't really happen in
actual code, but can happen in documentation (which uses the same
syntax grammar).
wren romano [Wed, 11 May 2022 23:32:54 +0000 (16:32 -0700)]
[mlir][sparse] Restyling macros in the runtime library
In addition to reducing code repetition, this also helps ensure that the various API functions follow the naming convention of mlir::sparse_tensor::primaryTypeFunctionSuffix (e.g., due to typos in the repetitious code).
Depends On D125428
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D125431
Philip Reames [Mon, 16 May 2022 23:27:39 +0000 (16:27 -0700)]
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)
The existing redundant copy elimination required a virtual register source, but the same logic works for any physreg where we don't have to worry about clobbers. On RISCV, this helps eliminate redundant CSR reads from VLENB.
Differential Revision: https://reviews.llvm.org/D125564
Ben Dunbobbin [Mon, 16 May 2022 23:11:18 +0000 (00:11 +0100)]
[llvm-ar][NFC] Address post-commit comments on D125439.
Remove errant whitespace.
AIX uses big archive format so check for both !<arch> and <bigaf>.
Only the "gnu" format has thin archives; specify --format=gnu for
thin archive test-cases.
River Riddle [Mon, 16 May 2022 23:23:01 +0000 (16:23 -0700)]
[mlir][NFC] Fix a few langref typos
Keith Smiley [Thu, 12 May 2022 17:28:57 +0000 (10:28 -0700)]
[llvm-objcopy][test] Add cmp after copy
All of the other tests here either check that the copy fails, or that
the resulting binary is the same, it seems like this check was omitted
for the universal object case.
Differential Revision: https://reviews.llvm.org/D125478
River Riddle [Mon, 9 May 2022 17:36:48 +0000 (10:36 -0700)]
[mlir][Tablegen-LSP] Add support for a basic TableGen language server
This follows the same general structure of the MLIR and PDLL language
servers. This commits adds the basic functionality for setting up the server,
and initially only supports providing diagnostics. Followon commits will
build out more comprehensive behavior.
Realistically this should eventually live in llvm/, but building in MLIR is an easier
initial step given that:
* All of the necessary LSP functionality is already here
* It allows for proving out useful language features (e.g. compilation databases)
without affecting wider scale tablegen users
* MLIR has a vscode extension that can immediately take advantage of it
Differential Revision: https://reviews.llvm.org/D125440
Ken Matsui [Mon, 16 May 2022 22:36:54 +0000 (15:36 -0700)]
[clang] Avoid suggesting typoed directives in `.S` files
This patch is itended to avoid suggesting typoed directives in `.S`
files to support the cases of `#` directives treated as comments or
various pseudo-ops. The feature is implemented in
https://reviews.llvm.org/D124726.
Fixes: https://reviews.llvm.org/D124726#3516346.
Reviewed By: nickdesaulniers
Differential Revision: https://reviews.llvm.org/D125727
wren romano [Wed, 11 May 2022 23:10:22 +0000 (16:10 -0700)]
[mlir][sparse] Adding "final" keyword wherever appropriate
This enables the compiler to perform devirtualization. And benchmarks
indicate devirtualization can sometimes give considerable speedup.
Depends On D122061
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D125428
wren romano [Wed, 11 May 2022 23:05:13 +0000 (16:05 -0700)]
[mlir][sparse] Enhancing sparse=>sparse conversion.
Fixes: https://github.com/llvm/llvm-project/issues/51652
Depends On D122060
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D122061
River Riddle [Sun, 15 May 2022 23:40:18 +0000 (16:40 -0700)]
[mlir] Restrict dialect doc gen to a single dialect
In the overwhelmingly majority of cases only one dialect is generated at a time
anyways, and this restriction more easily catches user error when multiple
dialects might be generated. We hit this semi-recently with the PDL dialect,
and circt+other downstream users are also actively hitting this as well.
Differential Revision: https://reviews.llvm.org/D125651
Jason Molenda [Mon, 16 May 2022 22:27:21 +0000 (15:27 -0700)]
[NFC] Don't bother with unstripped binary w/ dSYM, don't DebugSymbols twice
This patch addresses two perf issues when we find a dSYM on macOS
after calling into the DebugSymbols framework. First, when we have
a local (probably stripped) binaary, we find the dSYM and we may
be told about the location of the symbol rich binary (probably
unstripped) which may be on a remote filesystem. We don't need the
unstripped binary, use the local binary we already have.
Second, after we've found the path to the dSYM, save that in the Module
so we don't call into DebugSymbols a second time later on to
rediscover it. If the user has a DBGShellCommands set, we need to
exec that process twice, serially, which can add up.
Differential Revision: https://reviews.llvm.org/D125616
rdar://
84576917
Joseph Huber [Mon, 16 May 2022 16:26:32 +0000 (12:26 -0400)]
[OpenMP] Don't build the offloading driver without a source input
The Clang driver additional stages to build a complete offloading
program for applications using CUDA or OpenMP offloading. This normally
requires either a source file input or a valid object file to be
handled. This would cause problems when trying to compile an assembly or
LLVM IR file through clang with flags that would enable offloading. This
patch simply adds a check to prevent the offloading toolchain from being
used if we don't have a valid source file.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D125705
Joseph Huber [Mon, 16 May 2022 15:49:51 +0000 (11:49 -0400)]
[Libomptarget] Don't build the device runtime without a new Clang
The OpenMP device offloading library is a bitcode library and thus only
expect to build and linked with the same version of clang that was used
to create it. This somewhat copmlicates the building process as we
require the Clang that was just built to be used to create the library.
This is either done with a two-step build, where OpenMP is built with
the Clang that was just installed, or through the
`-DLLLVM_ENABLE_RUNTIMES=openmp` option. This has always been the case,
but recent changes have caused this to make it difficult to build the
rest of OpenMP. This patchs adds a check to not build the OpenMP device
runtime if the current compiler is not Clang with the same version as
the LLVM installation. This should allow users to build OpenMP as a
project using any compiler without it erroring out due to the bitcode
library, but if users require it they will need to use the above methods
to compile it.
Reviewed By: jdoerfert, tianshilei1992, ye-luo
Differential Revision: https://reviews.llvm.org/D125698
Alex Zinenko [Fri, 13 May 2022 16:03:08 +0000 (18:03 +0200)]
[mlir] allow for re-registering extension ops
Op registration mechanism does not allow for ops with the same name to be
re-registered. This is okay to avoid name conflicts and debug
double-registration, but may be problematic for dialect extensions that may get
registered several times (unlike dialects that are deduplicated in the
registry). When registering ops through the Transform dialect extension
mechanism, check first if the ops are already registered and only complain in
the case of repeated registration with the same name but different TypeID.
Differential Revision: https://reviews.llvm.org/D125554
Jonas Devlieghere [Mon, 16 May 2022 21:51:27 +0000 (14:51 -0700)]
[lldb] Prevent underflow in crashlog.py
Avoid a OverflowError (an underflow really) when the pc is zero. This
can happen for "unknown frames" where the crashlog generator reports a
zero pc. We could omit them altogether, but if they're part of the
crashlog it seems fair to display them in lldb as well.
rdar://
92686666
Differential revision: https://reviews.llvm.org/D125716
Sanjay Patel [Mon, 16 May 2022 21:47:02 +0000 (17:47 -0400)]
Revert "[InstCombine] invert canonicalization for cast of signbit test"
This reverts commit
3794cc0e996481e10307b67c8436aa44e0d65d22.
This change is suspected of causing bots to hang at stage 2
compiles, so reverting to confirm and investigate.
Martin Storsjö [Sat, 14 May 2022 22:59:14 +0000 (01:59 +0300)]
[MC] [Win64EH] Check for matches between epilogs and the prolog on ARM64
This allows sharing opcodes between prolog and epilog even when there
is more than one epilog.
I didn't make any handcrafted special MC level testcases for this (yet
at least), but it does seem to have the expected effect on two existing
CodeGen level testcases.
Differential Revision: https://reviews.llvm.org/D125619
Martin Storsjö [Fri, 13 May 2022 07:42:56 +0000 (10:42 +0300)]
[MC] [Win64EH] Try writing an ARM64 "packed epilog" even if the epilog doesn't share opcodes with the prolog
The "packed epilog" form only implies that the epilog is located
exactly at the end of the function (so the location of the epilog
is implicit from the epilog opcodes), but it doesn't have to share
opcodes with the prolog - as long as the total number of opcode
bytes and the offset to the epilog fit within the bitfields.
This avoids writing a 4 byte epilog scope in many cases. (I haven't
measured how much this shrinks actual xdata sections in practice
though.)
Differential Revision: https://reviews.llvm.org/D125536
Martin Storsjö [Mon, 16 May 2022 07:51:36 +0000 (10:51 +0300)]
[ARM] Rename the isARMAreaXRegister parameter isIOS to SplitFramePushPop. NFC.
In
f8b0a7af52f8c4ec6b4ddcfe3a6fa75098c9507c in 2016, this parameter
was generalized on the caller side (previously passing
STI.isTargetMachO(), now passing STI.splitFramePushPop()). Rename
the parameter on the receiver side to match the generalization.
Differential Revision: https://reviews.llvm.org/D125681
Eli Friedman [Mon, 16 May 2022 21:40:57 +0000 (14:40 -0700)]
[compiler-rt builtins] Assert that atomic.c can be compiled correctly.
The spinlock requires that lock-free operations are available;
otherwise, the implementation just calls itself. As discussed in
D120026.
Differential Revision: https://reviews.llvm.org/D123080
Paul Walker [Sat, 14 May 2022 11:49:07 +0000 (12:49 +0100)]
[AArch64] Use ADDV for boolean xor reductions.
NEON does not have native support for xor reductions. However, when
reducing predicate vectors the operation is synonymous with an add
reduction that is supported.
Differential Revision: https://reviews.llvm.org/D125605
Ellis Hoag [Mon, 16 May 2022 17:36:20 +0000 (10:36 -0700)]
[InstrProf] Fix promoter when using counter relocations
When using counter relocations, two instructions are emitted to compute
the address of the counter variable.
```
%BiasAdd = add i64 ptrtoint <__profc_>, <__llvm_profile_counter_bias>
%Addr = inttoptr i64 %BiasAdd to i64*
```
When promoting a counter, these instructions might not be available in
the block, so we need to copy these instructions.
This fixes https://github.com/llvm/llvm-project/issues/55125
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D125710
Matthias Springer [Mon, 16 May 2022 21:09:08 +0000 (23:09 +0200)]
[mlir][bufferize] Better propagation of errors
Return immediately when an op bufferization patterns fails.
Differential Revision: https://reviews.llvm.org/D125087
Mogball [Mon, 16 May 2022 20:28:17 +0000 (20:28 +0000)]
[mlir][ods] Fix verification of attribute + colon type ambiguity
An attribute without a type builder followed by a colon in an assembly format is potentially ambiguous because the parser will read ahead to parse the colon-type and pass this as the type argument to the attribute's constructor.
However, the previous verifier that checks for this ambiguity erroneously produces an error in the case of
```
let assemblyFormat = "( `(` $attr `)` )? `:`";
```
This patch fixes the bug by implementing a checker that correctly handles all edge cases, including very strange assembly formats like:
```
let assemblyFormat = "( `(` $attr ) : (`>`)? attr-dict (`>` $a^) : (`<`)? `:`";
```
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D125445
River Riddle [Thu, 12 May 2022 20:36:05 +0000 (13:36 -0700)]
[mlir] Remove the `type` keyword from type alias definitions
This was carry over from LLVM IR where the alias definition can
be ambiguous, but MLIR type aliases have no such problems.
Having the `type` keyword is superfluous and doesn't add anything.
This commit drops it, which also nicely aligns with the syntax for
attribute aliases (which doesn't have a keyword).
Differential Revision: https://reviews.llvm.org/D125501
Mogball [Mon, 16 May 2022 20:45:24 +0000 (20:45 +0000)]
[mlir][transforms] Add a topological sort utility and pass
This patch adds a topological sort utility and pass. A topological sort reorders
the operations in a block without SSA dominance such that, as much as possible,
users of values come after their producers.
The utility function sorts topologically the operation range in a given block
with an optional user-provided callback that can be used to virtually break cycles.
The toposort pass itself recursively sorts graph regions under the target op.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D125063
zhijian [Mon, 16 May 2022 20:29:16 +0000 (16:29 -0400)]
[AIX] llvm-link support big archive.
Summary:
Use object::Archive::create so that the returned archive object has a dynamic type of either Archive or BigArchive.
Reviewers: James Henderson,Fangrui Song
Differential Revision: https://reviews.llvm.org/D124940
Mogball [Mon, 16 May 2022 20:21:39 +0000 (20:21 +0000)]
[mlir][ods] Ignore AttributeSelfTypeParameter in assembly formats
The attribute self type parameter is currently treated like any other attribute parameter in the assembly format. The self type parameter should be handled by the operation parser and printer and play no role in the generated parsers and printers of attributes.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D125724
Aart Bik [Sat, 14 May 2022 00:54:32 +0000 (17:54 -0700)]
[mlir][sparse] introduce complex type to sparse tensor support
This is the first implementation of complex (f64 and f32) support
in the sparse compiler, with complex add/mul as first operations.
Note that various features are still TBD, such as other ops, and
reading in complex values from file. Also, note that the
std::complex<float> had a bit of an ABI issue when passed as
single argument. It is still TBD if better solutions are possible.
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D125596
Yang Keao [Mon, 16 May 2022 19:12:50 +0000 (14:12 -0500)]
[DomPrinter] Migrate -dot-dom to the new pass manager.
In D123677, @YangKeao provided an implementation of `DOTGraphTraits{Viewer,Printer}` in the new pass manager. This commit migrates the `DomPrinter` and `DomViewer` to the new pass manager.
Reviewed By: Meinersbur
Differential Revision: https://reviews.llvm.org/D124904
Paul Walker [Fri, 8 Apr 2022 11:59:21 +0000 (12:59 +0100)]
[SelectionDAG] Remove duplicate "is scaled" information from gather/scatter SDNodes.
During early gather/scatter enablement two different approaches
were taken to represent scaled indices:
* A Scale operand whereby byte_offsets = Index * Scale
* An IndexType whereby byte_offsets = Index * sizeof(MemVT.ElementType)
Having multiple representations is bad as shown by this patch which
fixes instances where the two are out of sync. The dedicated scale
operand is more flexible and pervasive so this patch removes the
UNSCALED values from IndexType. This means all indices are scaled
but the scale can be one, hence unscaled. SDNodes now use the scale
operand to answer the "isScaledIndex" question.
I toyed with the idea of keeping the UNSCALED enums and helper
functions but because they will have no uses and force SDNodes to
validate the set of supported values I figured it's best to remove
them. We can re-add them if there's a real need. For similar
reasons I've kept the IndexType enum when a bool could be used as I
think being explicitly looks better.
Depends On D123347
Differential Revision: https://reviews.llvm.org/D123381
Louis Dionne [Fri, 13 May 2022 20:13:54 +0000 (16:13 -0400)]
[libc++] Remove overly conservative error in <stdatomic.h>
As mentionned in D97044, it is fine if users include <atomic> and then
include <stdatomic.h> -- we don't need to error out for that case.
Differential Revision: https://reviews.llvm.org/D125579
Louis Dionne [Mon, 16 May 2022 14:04:33 +0000 (10:04 -0400)]
[libc++] Remove the legacy LIBCXX_LIBCPPABI_VERSION option
I think this notion of libc++abi's version was relevant a long time ago
on Apple platforms when we were using a Xcode project to build the library.
As part of moving Apple's build to CMake, D59489 made it possible to
specify the "ABI version" of libc++abi in use. However, it's not possible
to build libc++abi with that old ABI anymore and we don't need the ability
to link against that version from libc++ anymore.
Hence, we can clean this up and stop falsely pretending that libc++abi
has more than one ABI version.
Differential Revision: https://reviews.llvm.org/D125687
John Paul Adrian Glaubitz [Mon, 16 May 2022 17:56:19 +0000 (10:56 -0700)]
[sanitizer] Don't use newfstatat for Linux on SPARC
Linux on SPARC uses fstatat64 instead.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D125572
Utkarsh Saxena [Mon, 16 May 2022 09:40:49 +0000 (11:40 +0200)]
Optimise findRefs for XRefs and docHighlights
Reduces time spent in findRef by 66%.
Differential Revision: https://reviews.llvm.org/D125675
Robert Suderman [Mon, 16 May 2022 18:08:49 +0000 (11:08 -0700)]
[mlir][tosa] Use math.ctlz intrinsic for tosa.clz
We were custom counting per bit for the clz instruction. Math dialect
now has an intrinsic to do this in one instruction. Migrated to this
instruction and fixed a minor bug math-to-llvm for the intrinsic.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D125592
zhijian [Mon, 16 May 2022 18:29:37 +0000 (14:29 -0400)]
[AIX] fixed llvm-ar can not read empty big archive correctly.
Summary:
llvm-ar can not read empty big archive correctly. it output error as
error: unable to load 'empty.a': truncated or malformed archive (characters in size field in archive member header are not all decimal numbers: '<bigaf>'
Reviewers: James Henderson
Differential Revision: https://reviews.llvm.org/D124017
Stanislav Mekhanoshin [Wed, 11 May 2022 20:04:17 +0000 (13:04 -0700)]
[AMDGPU] Revert wide LDS DMA support.
This reverts
ffbee7acdcaaf, see also bug 37653 which it was fixing.
The bug claims this is an undocumented feature which actually works.
In the reality it is documented as not working for a good reason.
It likely does something, but it is useless anyway. These instructions
write into the LDS. The LDS address is:
M0 + inst_offset + (TIDinWave * 4).
For a store wider than a DWORD neighboring lanes will overwrite each
other.
Differential Revision: https://reviews.llvm.org/D125409
Utkarsh Saxena [Mon, 16 May 2022 12:06:22 +0000 (14:06 +0200)]
Add documentHighlight in clangd check for performance measurements.
Differential Revision: https://reviews.llvm.org/D125682
Alex Bradbury [Mon, 16 May 2022 17:47:25 +0000 (18:47 +0100)]
[WebAssembly][TableGen][NFCI] Use getValueAsBit rather than converting TableGen 'bit' to string
The logic around IsCanonical previously used getAsString and compared to
"1". Just using getValueAsBit is simpler.
Jakub Kuderski [Mon, 16 May 2022 17:43:35 +0000 (13:43 -0400)]
[mlir:toy][NFC] Remove unnecessary trailing return type
In this instance, the trailing return type does not improve readability
as it repeats what is returned in the same line.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D125697
Fangrui Song [Mon, 16 May 2022 17:42:43 +0000 (10:42 -0700)]
[Driver] Change "zlib not installed" diagnostic to "zlib not enabled"
The former is a bit misleading and a user may try installing zlib which
will not help.
Fangrui Song [Mon, 16 May 2022 17:34:01 +0000 (10:34 -0700)]
[docs] Re-generate ClangCommandLineReference.rst
Rahman Lavaee [Fri, 13 May 2022 17:32:13 +0000 (10:32 -0700)]
[llvm-objdump] Let --symbolize-operands symbolize basic block addresses based on the SHT_LLVM_BB_ADDR_MAP section.
`--symbolize-operands` already symbolizes branch targets based on the disassembly. When the object file is created with `-fbasic-block-sections=labels` (ELF-only) it will include a SHT_LLVM_BB_ADDR_MAP section which maps basic blocks to their addresses. In such case `llvm-objdump` can annotate the disassembly based on labels inferred on this section.
In contrast to the current labels, SHT_LLVM_BB_ADDR_MAP-based labels are created for every machine basic block including empty blocks and those which are not branched into (fallthrough blocks).
The old logic is still executed even when the SHT_LLVM_BB_ADDR_MAP section is present to handle functions which have not been received an entry in this section.
Reviewed By: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D124560
Adrian Prantl [Mon, 16 May 2022 17:05:38 +0000 (10:05 -0700)]
Remove stale file from modulemap
David Green [Mon, 16 May 2022 17:00:30 +0000 (18:00 +0100)]
[AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32
There have been some patterns in the AArch64 backend to optimize code of
the form:
ldrsh w8, [x0]
scvtf s0, w8
to:
ldr h0, [x0]
sshll v0.4s, v0.4h, #0
scvtf s0, s0
The idea is to remove the GRP->FPR move, but in reality is making code
larger and slower (or the same) on all the cpus I tried.
This patch adds the UseAlternateSExtLoadCVTF32 predicate similar to
nearby related pattern.
Differential Revision: https://reviews.llvm.org/D125470
Sanjay Patel [Mon, 16 May 2022 16:29:47 +0000 (12:29 -0400)]
[InstCombine] invert canonicalization for cast of signbit test
The existing transform was wrong in 3 ways:
1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).
This fixes #54692 (modeled by the PhaseOrdering tests).
This is a minimal step to fix the bug, but we should likely invert
the sibling transform for the "is negative" pattern too.
The backend should be able to invert this back to a shift if that
leads to better codegen.
Sanjay Patel [Mon, 16 May 2022 16:26:48 +0000 (12:26 -0400)]
[InstCombine] add tests for zext-of-signbit test; NFC
Craig Topper [Mon, 16 May 2022 16:28:09 +0000 (09:28 -0700)]
[AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC
This bug is in generic DAG combine and easily reproducible on many
targets.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D125640
Craig Topper [Mon, 16 May 2022 16:27:43 +0000 (09:27 -0700)]
[TargetLowering] Expand the last stage of i16 popcnt using shift+add+and instead of mul+shift.
If we use multiply it would be with 0x0101 which is 1 more than a power
of 2. On some targets we would expand this to shl+add. By avoiding the
multiply earlier, we can generate better code.
Note, PowerPC doesn't do the shl+add expansion of multiply so one of
the tests increased in instruction count.
Limiting to scalars because it almost always increased the number of
instructions in vector tests.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D125638
Craig Topper [Sun, 15 May 2022 18:45:42 +0000 (11:45 -0700)]
[DAGCombiner] Fix incorrect indentation. NFC
Philip Reames [Mon, 16 May 2022 16:15:26 +0000 (09:15 -0700)]
[RISCV] Add further trace output to InsertVSETLVI
Hongtao Yu [Fri, 13 May 2022 05:08:18 +0000 (22:08 -0700)]
[llvm-profgen] Update callsite body samples by summing up all call target samples.
Current profile generation caculcates callsite body samples and call target samples separately. The former is done based on LBR range samples while the latter is done based on branch samples. Note that there's a subtle difference. LBR ranges is formed from two consecutive branch samples. Therefore the last entry in a LBR record will not be counted towards body samples while there's still a chance for it to be counted towards call targets if it is a function call. I'm making sense of the call body samples by updating it to the aggregation of call targets.
Reviewed By: wenlei
Differential Revision: https://reviews.llvm.org/D122609
Matthias Springer [Mon, 16 May 2022 15:02:00 +0000 (17:02 +0200)]
[mlir][bufferize] Better user control of layout maps
This changes replaces the `fully-dynamic-layout-maps` options (which was badly named) with two new options:
* `unknown-type-conversion` controls the layout maps on buffer types for which no layout map can be inferred.
* `function-boundary-type-conversion` controls the layout maps on buffer types inside of function signatures.
Differential Revision: https://reviews.llvm.org/D125615
Ellis Hoag [Mon, 16 May 2022 14:13:07 +0000 (07:13 -0700)]
[InstrProf][NFC] Save profile bias to function map
Add a map from functions to load instructions that compute the profile bias. Previously we assumed that if the first instruction in the function was a load instruction, then it must be computing the bias. This was likely to work out because functions usually start with the `llvm.instrprof.increment` instruction, but optimizations could change this. For example, inlining into a non-profiled function.
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D114319
Sanjay Patel [Mon, 16 May 2022 15:11:51 +0000 (11:11 -0400)]
[IR] create and use helper functions that test the signbit; NFCI
Philip Reames [Mon, 16 May 2022 14:48:57 +0000 (07:48 -0700)]
[LiveIntervals] Add range accessors for value numbers [nfc]
Simon Pilgrim [Mon, 16 May 2022 15:19:03 +0000 (16:19 +0100)]
[polly] Remove 'using namespace llvm/polly' from ScopGraphPrinter.h header.
As mentioned on D123678 this appears to be causing namespace resolution issues on some versions of gcc.
David Green [Mon, 16 May 2022 14:50:39 +0000 (15:50 +0100)]
[AArch64] Update check lines in arm64-scvt.ll. NFC
Sanjay Patel [Mon, 16 May 2022 14:21:55 +0000 (10:21 -0400)]
[PhaseOrdering] add tests for cmp + boolean/bitwise logic; NFC
The tests (see C++ source in #54692) have multiple potential
optimizations/canonicalizations, but we should be consistent
since they are logically identical.
Sanjay Patel [Mon, 16 May 2022 13:59:31 +0000 (09:59 -0400)]
[InstCombine] fix test name; NFC
The bug number was typo'd when it was added for D86243.
Alexey Bataev [Mon, 16 May 2022 13:43:00 +0000 (06:43 -0700)]
[SLP]Check if the root of the buildvector has one use only.
The root of the buildvector can have only one use, otherwise it can be
treated only as a final element of the previous buildvector sequence.
Nikita Popov [Fri, 13 May 2022 14:35:43 +0000 (16:35 +0200)]
[ValueTracking] Handle and/or on RHS of isImpliedCondition()
isImpliedCondition() currently handles and/or on the LHS, but not
on the RHS, resulting in asymmetric behavior. This patch adds two
new implication rules:
* LHS ==> (RHS1 || RHS2) if LHS ==> RHS1 or LHS ==> RHS2
* LHS ==> !(RHS1 && RHS2) if LHS ==> !RHS1 or LHS ==> !RHS2
Differential Revision: https://reviews.llvm.org/D125551
Florian Hahn [Mon, 16 May 2022 14:27:22 +0000 (15:27 +0100)]
[LAA,LV] Add initial support for pointer-diff memory checks.
This patch adds initial support for a pointer diff based runtime check
scheme for vectorization. This scheme requires fewer computations and
checks than the existing full overlap checking, if it is applicable.
The main idea is to only check if source and sink of a dependency are
far enough apart so the accesses won't overlap in the vector loop. To do
so, it is sufficient to compute the difference and compare it to the
`VF * UF * AccessSize`. It is sufficient to check
`(Sink - Src) <u VF * UF * AccessSize` to rule out a backwards
dependence in the vector loop with the given VF and UF. If Src >=u Sink,
there is not dependence preventing vectorization, hence the overflow
should not matter and using the ULT should be sufficient.
Note that the initial version is restricted in multiple ways:
1. Pointers must only either be read or written, by a single
instruction (this allows re-constructing source/sink for
dependences with the available information)
2. Source and sink pointers must be add-recs, with matching steps
3. The step must be a constant.
3. abs(step) == AccessSize.
Most of those restrictions can be relaxed in the future.
See https://github.com/llvm/llvm-project/issues/53590.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D119078
Joe Nash [Fri, 13 May 2022 16:55:16 +0000 (12:55 -0400)]
[AMDGPU] Mark sendmsg hasSideEffects. NFC
Address the FIXME by marking the sendmsg instructions with
hasSideEffects.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D125569
Jay Foad [Fri, 18 Feb 2022 17:24:50 +0000 (17:24 +0000)]
[AMDGPU] Shrink MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10
On GFX10 VOP3 instructions can have a literal operand, so the conversion
from VOP3 MAD/FMA to VOP2 MADAK/MADMK/FMAAK/FMAMK will not happen in
SIFoldOperands. The only benefit of the VOP2 form is code size, so do it
in SIShrinkInstructions instead.
Differential Revision: https://reviews.llvm.org/D125567
Nikita Popov [Mon, 16 May 2022 14:04:11 +0000 (16:04 +0200)]
[ConstantRange] Add toKnownBits() method
Add toKnownBits() method to mirror fromKnownBits(). We know the
top bits that are constant between min and max.
The return value for an empty range is chosen to be conservative.
Joe Nash [Tue, 19 Apr 2022 19:38:35 +0000 (15:38 -0400)]
[AMDGPU] gfx11 BUF Instructions
Includes MachineCode layer support and tests, and MIR tests not requiring
CodeGen pass changes.
Includes a small change in SMInstructions.td to correct encoded bits.
Contributors:
Petar Avramovic <Petar.Avramovic@amd.com>
Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>
Depends on D125316
Patch 6/N for upstreaming of AMDGPU gfx11 architecture.
Reviewed By: dp, Petar.Avramovic
Differential Revision: https://reviews.llvm.org/D125319
Stephen Long [Mon, 16 May 2022 13:59:40 +0000 (06:59 -0700)]
[MSVC] Add support for pragma alloc_text
`#pragma alloc_text` is a MSVC pragma that names the code section where functions should be placed. It only
applies to functions with C linkage.
https://docs.microsoft.com/en-us/cpp/preprocessor/alloc-text?view=msvc-170
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D125011
Mehdi Amini [Mon, 16 May 2022 09:50:18 +0000 (09:50 +0000)]
Apply clang-tidy fixes for llvm-qualified-auto in LinalgInterfaces.cpp (NFC)
Mehdi Amini [Mon, 16 May 2022 09:49:11 +0000 (09:49 +0000)]
Apply clang-tidy fixes for performance-move-const-arg in SerializeToHsaco.cpp (NFC)
Nathan James [Mon, 16 May 2022 13:42:43 +0000 (14:42 +0100)]
[clang-tidy][NFC] Reimplement SimplifyBooleanExpr with RecursiveASTVisitors
Reimplement the matching logic using Visitors instead of matchers.
Benchmarks from running the check over SemaCodeComplete.cpp
Before 0.20s, After 0.04s
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D125026
Liqin.Weng [Mon, 16 May 2022 13:30:58 +0000 (13:30 +0000)]
[CodeGen] Use ArrayRef in TargetLowering functions
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D123656