zink: split off CreateShaderModule into util function

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14976>

zink: store the tcs_vertices_out spirv word to the spirv_shader struct

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14976>

zink: store the tcs_vertices_out spirv word

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14976>

zink: make spirv_builder_emit_exec_mode_literal() return the word for the param

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14976>

zink: make spirv_buffer_emit_word() return the word that was written

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14976>

zink: break out spirv shader dumping into separate function

debugging++

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14976>

zink: ci updates

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14974>

zink: always set VkPipelineMultisampleStateCreateInfo::pSampleMask

by initializing this on context creation, we can ensure that the correct
value is always here

cc: mesa-stable

fixes:
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_only
dEQP-GLES31.functional.texture.multisample.samples_2.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_2.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_2.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_2.sample_mask_only
dEQP-GLES31.functional.texture.multisample.samples_3.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_3.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_3.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_3.sample_mask_only
dEQP-GLES31.functional.texture.multisample.samples_4.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_4.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_4.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_4.sample_mask_only

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14974>

gallivm: add coroutine attribute that llvm requires.

Running llvm in debug mode asserts on this being missing.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14963>

microsoft/compiler: Fill interpolation for sysval inputs to non-vertex shader

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5483
Reviewed-by: Michael Tang <tangm@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14984>

d3d12: Only force point sampling for emulated shadow samplers

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14981>

anv: make the pointer valid before we assign stuff into it

Fixes: 665ffd4bf9c ("anv: Update VK_KHR_fragment_shading_rate for newer HW")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14982>

anv: Enable requiredSubgroupSize for Task/Mesh

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14979>

anv: Increase maxBoundDescriptorSets to 32

We recently had a request to support a larger maxBoundDescriptorSets,
specifically 32, and there doesn't appear to be a reason we need to
restrict this to 8.  According to vulkan.gpuinfo.org reports, most
Vulkan drivers appear to support 32.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14952>

driconf: Add Heaven entries for Windows .exe

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14965>

d3d12: Don't add a second dual-source output for Heaven

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14965>

d3d12: Default newly-created resources to not-resident

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14959>

d3d12: Implement residency management algorithm

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14959>

d3d12: Add a budget/usage callback to the screen

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14959>

d3d12: Add residency info to d3d12_bo

This is all currently immutable, but will be used to manage the
residency of the underlying D3D objects in a future commit.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14959>

d3d12: Add sampler's textures to batch bo tracking

This will be important for residency in a future change, but also
is necessary for synchronize() to work correctly for TBOs.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14959>

d3d12: Move ID3D12Fence from context to screen

There's already a single command queue for the screen, meaning that
all commands are being serialized implicitly into that queue. There's
no need to have separate fences for parallel contexts when those
fences would all share the same underlying timeline.

This adds an explicit lock to expand the scope of the implicit screen
command queue ordering to include fence signals.

Each context still gets its own submit sequence, which is used for 1
purpose right now: A uniqueness check in the state manager to see
if states are coming from separate command lists, to apply promotion
and decay logic.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14959>

d3d12: Forward wait condition from query -> result buffer

The no-wait condition was wrong before. If the query was used in the
current batch (query->fence_value == context->fence_value), we'd
continue on with the operation instead of returning false. Then the
buffer map would see that the bo is referenced in the current batch,
and would flush and wait, even though we were asked not to wait.

This fixes the condition by simply using the (correct) buffer map
logic.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14959>

d3d12: When mapping a resource used in the current batch without blocking, at least flush

Also, resource_is_busy needs to opportunistically retire batches, so apps can
spin on non-blocking resource maps and eventually succeed.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14959>

nir: Produce correct results for atan with NaN

Properly handling NaN adversely affects several hundred shaders in
shader-db (lots of Skia and a few others from various synthetic
benchmarks) and fossil-db (mostly Talos and some Doom 2016).  Only apply
the NaN handling work-around when the shader demands it.

v2: Add comment explaining the 1.0*y_over_x.  Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 2098ae16c8b ("nir/builder: Move nir_atan and nir_atan2 from SPIR-V translator")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

nir: Properly handle various exceptional values in frexp

frexp_sig of ±0, ±Inf, or NaN should just return the input unmodified.

frexp_exp of ±Inf or NaN is undefined, and frexp_exp of ±0 should return
the input unmodified.  This seems to already work.

No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 23d30f4099f ("spirv,nir: lower frexp_exp/frexp_sig inside a new NIR pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

spirv: Produce correct result for GLSLstd450Tanh with NaN

No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 9f9432d56c0 ("Revert "spirv: Use a simpler and more correct implementaiton of tanh()"")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

spirv: Produce correct result for GLSLstd450Modf with Inf

GLSLstd450ModfStruct too.

No shader-db or fossil-db changes on any Intel platform.

v2: Fix handling 16-bit (and presumably 64-bit) values.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: f92a35d831c ("vtn: Fix Modf.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

spriv: Produce correct result for GLSLstd450Step with NaN

NOTE: This commit needs "nir: All set-on-comparison opcodes can take all
float types" or regressions will occur in other Vulkan SPIR-V tests.

No shader-db changes on any Intel platform.

NOTE: This commit depends on "nir: All set-on-comparison opcodes can
take all float types".

v2: Fix handling 16-bit (and presumably 64-bit) values.

About 280 shaders in Talos are hurt by a few instructions, and a couple
shaders in Doom 2016 are hurt by a few instructions.

Tiger Lake
Instructions in all programs: 159893290 -> 159895026 (+0.0%)
SENDs in all programs: 6936431 -> 6936431 (+0.0%)
Loops in all programs: 38385 -> 38385 (+0.0%)
Cycles in all programs: 7019260087 -> 7019254134 (-0.0%)
Spills in all programs: 101389 -> 101389 (+0.0%)
Fills in all programs: 131532 -> 131532 (+0.0%)

Ice Lake
Instructions in all programs: 143624235 -> 143625691 (+0.0%)
SENDs in all programs: 6980289 -> 6980289 (+0.0%)
Loops in all programs: 38383 -> 38383 (+0.0%)
Cycles in all programs: 8440083238 -> 8440090702 (+0.0%)
Spills in all programs: 102246 -> 102246 (+0.0%)
Fills in all programs: 131908 -> 131908 (+0.0%)

Skylake
Instructions in all programs: 134185495 -> 134186618 (+0.0%)
SENDs in all programs: 6938790 -> 6938790 (+0.0%)
Loops in all programs: 38356 -> 38356 (+0.0%)
Cycles in all programs: 8222366923 -> 8222365826 (-0.0%)
Spills in all programs: 98821 -> 98821 (+0.0%)
Fills in all programs: 125218 -> 125218 (+0.0%)

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 1feeee9cf47 ("nir/spirv: Add initial support for GLSL 4.50 builtins")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

intel/fs: Don't optimize out 1.0*x and -1.0*x

This (sort of) matches the behavior of nir_opt_algebraic.  This ensures
that subnormal values are properly flushed to zero.

With the aid of "nir/search: Float sources of texture instructions are
float users" and "nir/search: Transitively apply is_only_used_as_float",
there would have been no shader-db regressions on Intel platforms.
However, those caused a significant increase in compile time.  Since the
instruction regressions were so small, I just dropped those commits
rather than improve them.

All Haswell and newer platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 20125042 -> 20125094 (<.01%)
instructions in affected programs: 7184 -> 7236 (0.72%)
helped: 0
HURT: 32
HURT stats (abs)   min: 1 max: 4 x̄: 1.62 x̃: 2
HURT stats (rel)   min: 0.11% max: 1.49% x̄: 0.85% x̃: 0.78%
95% mean confidence interval for instructions value: 1.39 1.86
95% mean confidence interval for instructions %-change: 0.74% 0.96%
Instructions are HURT.

total cycles in shared programs: 862745586 -> 862746551 (<.01%)
cycles in affected programs: 109872 -> 110837 (0.88%)
helped: 12
HURT: 23
helped stats (abs) min: 2 max: 774 x̄: 90.83 x̃: 19
helped stats (rel) min: 0.07% max: 25.23% x̄: 3.06% x̃: 0.40%
HURT stats (abs)   min: 2 max: 1106 x̄: 89.35 x̃: 12
HURT stats (rel)   min: 0.08% max: 45.40% x̄: 3.01% x̃: 0.47%
95% mean confidence interval for cycles value: -60.09 115.23
95% mean confidence interval for cycles %-change: -2.21% 4.07%
Inconclusive result (value mean confidence interval includes 0).

All of the shaders hurt are in either UE4 shooter-game or shooter_demo.

Tiger Lake
Instructions in all programs: 159893213 -> 159893290 (+0.0%)
SENDs in all programs: 6936431 -> 6936431 (+0.0%)
Loops in all programs: 38385 -> 38385 (+0.0%)
Cycles in all programs: 7019259514 -> 7019260087 (+0.0%)
Spills in all programs: 101389 -> 101389 (+0.0%)
Fills in all programs: 131532 -> 131532 (+0.0%)

Ice Lake
Instructions in all programs: 143624164 -> 143624235 (+0.0%)
SENDs in all programs: 6980289 -> 6980289 (+0.0%)
Loops in all programs: 38383 -> 38383 (+0.0%)
Cycles in all programs: 8440082767 -> 8440083238 (+0.0%)
Spills in all programs: 102246 -> 102246 (+0.0%)
Fills in all programs: 131908 -> 131908 (+0.0%)

Skylake
Instructions in all programs: 134185424 -> 134185495 (+0.0%)
SENDs in all programs: 6938790 -> 6938790 (+0.0%)
Loops in all programs: 38356 -> 38356 (+0.0%)
Cycles in all programs: 8222366529 -> 8222366923 (+0.0%)
Spills in all programs: 98821 -> 98821 (+0.0%)
Fills in all programs: 125218 -> 125218 (+0.0%)

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: f5dd6dfe012 ("anv: enable VK_KHR_shader_float_controls and SPV_KHR_float_controls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

nir: All set-on-comparison opcodes can take all float types

Extend 4195a9450bde so that the next poor fool doesn't come along and
say, "sge does the right thing for 16-bit sources, but slt gives a NIR
validation failure. What the deuce?"

NOTE: This commit is necessary to prevent regressions in GLSLstd450Step
tests of 16-bit sources at "spriv: Produce correct result for
GLSLstd450Step with NaN".

Fixes: 4195a9450bd ("nir: sge operation is defined for floating-point types")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

nir/search: Constify instr parameter to nir_search_expression::cond

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

nir: Constify def parameter to nir_ssa_def_bits_used

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>

nir: Use proper macro to set bits of variable correctly

When slots is 64 only the first bit was being set, instead of setting
all 64 bits of the variable, so for that case the function
get_variable_io_mask() always returned 0.

This behaviour caused variables that are being used both on producer and
consumer to be considered unused and thus being removed on
nir_remove_unused_io_vars().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14955>

Revert "ci: Disable Windows for now"

This reverts commit be385ab5bcba60e30c8c980ae595e1e69a888393.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14975>

nir/lower_mediump: Treat u2u16 like i2i16.

There is a comment in nir_fold_16bit_sampler_conversions saying that these
are the same, but the code only checks for i2i16.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14893>

zink: anv (icl) ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14973>

freedreno/pps: Expose same counters as blob

Expose most of the counters exposed by blob. By faking the value of
counters returned from kgsl I found the exact underlying counters and
constant coefficients being used.

Note, coefficients for counters that depend on time are NOT verified.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14323>

radv/ci: update CI lists for CTS 1.3.1.0

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14946>

radv: remove exports without color attachment or writemask

This lets us make use of NIR's more advanced DCE.
This includes removing of CF constructs, PS inputs and VS outputs.

Totals from 1959 (1.45% of 134913) affected shaders: (GFX10.3)
VGPRs: 73464 -> 71944 (-2.07%); split: -3.79%, +1.72%
SpillSGPRs: 6 -> 0 (-inf%)
CodeSize: 4860324 -> 4675248 (-3.81%); split: -4.92%, +1.11%
LDS: 2619904 -> 2781696 (+6.18%); split: -0.37%, +6.55%
MaxWaves: 50614 -> 50852 (+0.47%); split: +1.63%, -1.16%
Instrs: 924233 -> 887836 (-3.94%); split: -5.01%, +1.07%
Latency: 5635532 -> 5418083 (-3.86%); split: -4.53%, +0.67%
InvThroughput: 1107764 -> 1077542 (-2.73%); split: -3.44%, +0.71%
VClause: 17361 -> 16163 (-6.90%); split: -8.38%, +1.47%
SClause: 31886 -> 29323 (-8.04%); split: -8.52%, +0.48%
Copies: 53529 -> 52127 (-2.62%); split: -5.30%, +2.68%
Branches: 22993 -> 22802 (-0.83%); split: -3.44%, +2.61%
PreSGPRs: 53123 -> 51395 (-3.25%); split: -3.60%, +0.35%
PreVGPRs: 59699 -> 57424 (-3.81%); split: -5.13%, +1.32%

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14771>

ci: Disable Windows for now

Docker on Windows is broken for some reason, so just disable it for now.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14970>

anv: update limit for maxVertexInputBindingStride

Before:
maxVertexInputBindingStride                     = 2048 (gen7+)

After:
maxVertexInputBindingStride                     = 2048 (gen7/gen8)
maxVertexInputBindingStride                     = 4095 (gen9+)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14958>

venus: fix two VN_TRACE_SCOPE's in the same scope

Make sure __LINE__ is expanded.

Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14960>

iris: Drop the iris_resource aux usage bit fields

A big reason we had these fields was to help create a set of surface
states for a resource. That's largely being handled through other means
now.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Compute aux.possible_usages from aux.usage

We're going to remove res->aux.possible_usages. This will simplify the
commit in which we do so.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Use iris_sample_with_depth_aux more often

We're going to remove res->aux.sampler_usages. This will simplify the
commit in which we do so.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

intel/isl: Add format assertions for surfaces using CCS

This caught some invalid CCS surface states created by iris.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Avoid making some invalid CCS surface states

Although a resource may support CCS with its original format, a texture
view of that resource may have a format that doesn't support
compression. Don't create CCS surface states for such texture views.

This change affects iris' behavior when running piglit's
arb_texture_view-rendering-formats_gles3 test on SKL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Inline some surface_state.cpu references

Now that we're using fill_surface_states, these aren't needed anymore.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Add and use fill_surface_states

This helper simplifies some repeated logic.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Add and use use_surface_state

This helper simplifies some repeated logic.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Add and use iris_surface_state::aux_usages

An iris_surface_state can have a different set of possible aux usages
than its iris_resource.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Drop res param from surf_state_offset_for_aux

This has been unused since commit 117a0368b0cc.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Drop format param from fast_clear_color

It's unused.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Don't fast clear with the view format

Fast clear with the resource format instead. This is safe to do because
can_fast_clear_color ensures that the clear color generates the same
pixel with either the view format or the resource format.

On SKL, this prevents us from using an invalid surface state. This platform
doesn't support CCS_E with sRGB formats, but prior to this patch we allowed
fast-clearing with this combination. Piglit's fcc-write-after-clear test
can trigger this.

Fixes: 230952c2101 ("iris: Don't support sRGB + Y_TILED_CCS on gen9")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

aux/draw: fix llvm tcs lane vec generation

the idx param for LLVMBuildInsertElement is zero-indexed based on the
value of 'vector_length' (always 4), and the vector length is (obviously)
sized to 'vector_length', so this should be the member of the vec that is being
inserted, not the invocation index

cc: mesa-stable

fixes (zink, but only on my one machine):
KHR-GL46.tessellation_shader.single.max_patch_vertices
KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
dEQP-GLES31.functional.tessellation.shader_input_output.barrier
dEQP-GLES31.functional.tessellation.shader_input_output.patch_vertices_5_in_10_out
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_point_mode_geometry_output_triangles
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_point_mode_geometry_output_lines
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_point_mode_geometry_output_lines

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14949>

radv: Add submit locking with trace bo.

Otherwise cmdbuffers from different queues can override the trace id
from each other, making for a very confusing hang report.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14868>

gallivm/nir: Call nir_lower_bool_to_int32 after nir_opt_algebraic_late

All of the opcodes in nir_opt_algebraic_late are the unsized (1-bit)
versions.  If the lowering to int32 happens first, many of the
optimizations and lowerings won't happen.

Of particular importance is the lowering of fisfinite.  If a shader
happens to contain fisfinite of an fp16 value, it will assert later
during compliation.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: 78b4e417d44 ("gallivm: handle fisfinite/fisnormal")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14942>

ci/freedreno: Try to detect a wedged MMU that's happened recently.

Possibly since the VK-GL-CTS 1.3.1.0 uprev.  It doesn't seem to recover,
like it says.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14945>

ci/lvp: Add a flake that's shown up a couple of times since VKCTS 1.3.1.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14945>

ci/r300: Drop xfails that were fixed with the VK-GL-CTS 1.3.1.0 uprev.

Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

nir: Delete the per-instr SSA liveness impl.

It was introduced for nir-to-tgsi, and I found that it was the wrong
approach.  There's a reason nobody else does RA this way.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

nir_to_tgsi: Replace the NIR SSA liveness with TGSI reg-level liveness.

Allocating NIR registers ends up being required for drivers like r600 and
nv30, which don't do their own allocation (except in some cases on r600
where sb is used).

Rather than add a NIR register liveness impl
(https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14158), switch
from NIR-based liveness to just doing the same channel-based liveness
logic that the NIR registers needed at the TGSI level.  The actual
liveness code here basically comes straight out of
brw_vec4_live_variables.cpp.

Since we do the liveness in TGSI now, it also means we don't need to be
careful about not reading SSA values from later TGSI instructions (which
may be useful for doing some greedy instruction selection in generating
TGSI instructions).

i915g:
total instructions in shared programs: 400719 -> 380730 (-4.99%)
instructions in affected programs: 284760 -> 264771 (-7.02%)
total tex_indirect in shared programs: 12289 -> 12290 (<.01%)
tex_indirect in affected programs: 4 -> 5 (25.00%)
total temps in shared programs: 32172 -> 22086 (-31.35%)
temps in affected programs: 30647 -> 20561 (-32.91%)
LOST:   0
GAINED: 148

r300:
total instructions in shared programs: 1472463 -> 1459286 (-0.89%)
instructions in affected programs: 507009 -> 493832 (-2.60%)
total temps in shared programs: 212143 -> 201678 (-4.93%)
temps in affected programs: 78007 -> 67542 (-13.42%)

softpipe:
total temps in shared programs: 517071 -> 294387 (-43.07%)
temps in affected programs: 509324 -> 286640 (-43.72%)

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

nir_to_tgsi: Track our TGSI insns in blocks before emitting tokens.

To do register allocation well, we want to have a point before
ureg_insn_emit() to look at the liveness of the values and allocate them
to TGSI temporaries.  In order to do that, we have to switch from
ureg_OPCODE() emitting TGSI tokens directly to a new ntt_OPCODE() that
stores the ureg args in a block structure.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

tgsi: Refactor out a tgsi_util_get_src_usage_mask().

The function operated on a tgsi_full_instruction, but for code generation
in NIR-to-TGSI I want to reuse this logic using pieces of tgsi_ureg
structs.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

i915g: Report the temps usage

This is another important metric for this driver, and we don't do our own
RA so ours is just what TGSI uses.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

docs: update calendar and link releases notes for 21.3.6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14956>

docs: add release notes for 21.3.6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14956>

docs: update calendar for 22.0.0-rc2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14953>

turnip: Depth/stencil formats should not expose any bufferFeatures

From the Vulkan 1.3.205 spec, section 19.3 "43.3. Required Format Support":

   Mandatory format support: depth/stencil with VkImageType
   VK_IMAGE_TYPE_2D
   [...]
   bufferFeatures must not support any features for these formats

See https://gitlab.khronos.org/vulkan/vulkan/-/merge_requests/4849

Fixes CTS tests: dEQP-VK.api.buffer.invalid_buffer_features.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14927>

radv: only emit the per-vertex VRS state if the pipeline forced it

If the primitive shading rate is not written by the last VGT stage
(like if no FS), it's useless to emit the VRS state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14907>

radv: do not force per-vertex VRS if there is no pixel shader

This has no effect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14907>

radv: rewrite RADV_FORCE_VRS directly in NIR

This introduces a small NIR pass that exports
VARYING_SLOT_PRIMITIVE_SHADING_RATE if RADV_FORCE_VRS is used,
instead of doing this in both backend compilers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14907>

v3dv/ci: Update failure list

Add more failing tests to the expected failures.

These are obtained after executing the full Vulkan CTS.

v2:
 - Add comments in the tests (Alejandro)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14948>

zink: ci updates

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14852>

zink: add Sample decorations to fragment shader inputs with sample shading

PIPE_CAP_FORCE_PERSAMPLE_INTERP is broken for the no-attachment case, so
this is the only option

fixes (lavapipe):
KHR-GL46.sample_shading.render*
dEQP-GLES31.functional.sample_shading.min_sample_shading*

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14852>

iris/ci: Enable Whiskey Lake boards by default

The boards should be stable now.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14822>

radeonsi: workaround Specviewperf13 Catia hang on GFX9

The root cause is unknown but PAL always update IA_MULTI_VGT_PARAM
whenever primitive type change.

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Singed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14944>

intel/fs: Assert that old pull-const code is not used if devinfo->has_lsc

Jason changed this to use LSC in:

f5876dfdb9b ("intel/fs: Lower uniform pull constant load message to LSC dataport")

Cc: 22.0 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14384>

iris: invalidate L3 read only cache when VF cache is invalidated

When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.

Ref: bspec 46314
Fixes: ed8f2c4cbee ("iris: Cache VB/IB in L3$ for Gen12")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>

anv: invalidate L3 read only cache when VF cache is invalidated

When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.

Ref: bspec 46314
Fixes: 6c345ddbe40 ("anv: Cache VB/IB in L3$ for Gfx12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5941
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>

intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>

anv: Refactor descriptor copy

Refactor descriptor copies to use the existing helper functions instead
of rolling our own. In order to facilitate this, we need to store the
appropriate buffer views for the relevant descriptors internally and
reuse them in the helpers.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14909>

radv: allow RADV_FORCE_VRS with pipeline VRS declared as dynamic

This is for vkd3d which needs to always declare the VRS dynamic state
because it's fully dynamic in DX12. Ignoring the VRS dynamic state
when it's a no-op seems the best way to handle this, although it's
definitely not perfect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14910>

iris: Disable PIPE_CAP_PREFER_BACK_BUFFER_REUSE

This cap bit only affects DRI_PRIME setups.  Since iris now uses the
blitter to perform dGPU -> iGPU copies asynchronously, it's better to
always use at least two backbuffers so the 3D engine can start rendering
the next frame during the copy.

See commit d17e75285732878bc3ee8307541c1b4f09cbee7c where this change
was made for radeonsi.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

iris: Use the hardware blitter for DRI PRIME blits

In a hybrid graphics setup, Mesa allocates two buffers for the window
surface.  The first is what the discrete card renders to; it lives in
VRAM and is usually tiled and possibly compressed.  The second is a
shadow copy that lives in system memory (readable by the integrated
card with the displays); it's usually linear and uncompressed.

Mesa's window system code schedules blits to update the shadow copy
when needed, typically at the end of a frame.  These can be fairly
costly when running a full-screen application at high resolutions.

We'd like to use the blitter for these copies, as it lets us perform
the copy asynchronously, letting the 3D engine race ahead and start
rendering the next frame.  If we used the 3D engine, the next frame
could not start rendering until the PRIME blit finishes, giving us
less time to draw the frame.  Fortunately, Tigerlake introduced new
blitter commands which can operate at full memory bandwidth.

DRI PRIME blits happen via the Gallium blit() hook.  We can detect that
case by looking for the PIPE_BIND_PRIME_BLIT_DST flag on the destination
resource.  This patch detects that case and calls iris_copy_region() on
IRIS_BATCH_BLITTER to handle it.  We know a priori that the blitter can
handle this operation (it's not a scaled blit, the formats match and
should not be 96bpp, there's no combined depth stencil, or other weird
edge cases).  blorp_copy() will also assert that edge cases don't occur.

Together with the next patch, this improves performance on DG1 Hybrid
scenarios by about 5-6%.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

iris: Allow IRIS_BATCH_BLITTER in iris_copy_region()

This updates iris_copy_region() to support using the blitter batch.
(Future patches will actually do so; for now, we keep using render.)

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

broadcom/simulator: enable multisync in the simulator

Use drmSyncobjSignal to signal out_syncobjs when a GPU job submission
ends in the simulator. With this, we can enable multisync support in the
simulator and keep the multisync approach to process fence by submitting
a serialized no-op job that adds the fence to the array of out syncobjs,
i.e.  syncobjs to be signaled in the kernel when a job completes (job
post deps).

Signed-off-by: Melissa Wen <mwen@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14768>

translate: improve sse2 32-bit unsigned -> float conversion

The existing logic would drop the low bit. Instead, let's drop the high
bit, do the conversion, and then add the fixed constant back in if the
value had the high bit set originally.

Fixes KHR-GL45.direct_state_access.vertex_arrays_attribute_format on
drivers that use this module to handle the format conversion.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

rtasm: add pcmpgtd operation

This will be used shortly by the translate code. Available in SSE2.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

rtasm: fix printf specifier for ptrdiff_t

In practice it's a small number, but new gcc versions complain.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

zink: ci updates

hooray

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

zink: do not copy colors through floats

Copying per compoents might flush NaN values, leading to changes in the
values, so it'd be safer to copy as unsigned integers here. But in one
of the cases here we can do even better, and just copy the whole damn
union instead.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

zink: Re-interpret formats when using vkCmdClearColorImage()

vkCmdClearColorImage() doesn't take a view format so it always uses the
underlying format of the image.  If there's texture views going on, we
need to manually mangle the colors into the image format.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

st/mesa: only enable ARB_enhanced_layouts if there are xfb buffers

It really doesn't make sense without any xfb support. One could limp
along, but our validation does not work as-is. Doesn't seem important to
support this use-case.

This disables GL_ARB_enhanced_layouts on crocus with gen4/5.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

glsl: only validate xfb_buffer values when we have enhanced layouts

XFB might not be supported, and the shader wouldn't be setting this
flag. But validation would still fail, since the number of xfb buffers
would be 0. So only validate if an xfb_buffer is set in the qualifiers.

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5415
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

glsl: simplify conditions for setting various allowed flags

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

nir_to_tgsi: Add a flag for lowering fabs, and use it in r300/i915.

Saves instructions if the same fabs value is used multiple times.

i915g:
total instructions in shared programs: 397005 -> 396525 (-0.12%)
instructions in affected programs: 11061 -> 10581 (-4.34%)
LOST:   0
GAINED: 22

r300 (not r500):
total instructions in shared programs: 180286 -> 179767 (-0.29%)
instructions in affected programs: 27102 -> 26583 (-1.91%)
total temps in shared programs: 29692 -> 29638 (-0.18%)
temps in affected programs: 356 -> 302 (-15.17%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

nir: Split the flag for lowering of fabs and fneg to source modifiers.

i915 and r300 have fneg source modifier but not fabs, and doing it in NIR
can save us some backend pain.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

r300: Throw a compile error instead of an assert in r300 swizzle rewrites.

I hit this on shader-db, but I really just want to get stats for unrelated
changes.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>