Alyssa Rosenzweig [Fri, 25 Nov 2022 01:40:48 +0000 (20:40 -0500)]
agx: Implement 8-bit sign extensions
Long term, I think having i2i16 and i2i32 available with 8-bit sources should
make lowering the rest of 8-bit away a bit easier. Short term, this avoids
special casing 8-bit in the VBO lowering code.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
Alyssa Rosenzweig [Fri, 25 Nov 2022 01:40:47 +0000 (20:40 -0500)]
agx: Allow some 8-bit sources
8-bit sources are useful for int8->float32 conversions, which we can do in a
single hardware instruction.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
Alyssa Rosenzweig [Fri, 25 Nov 2022 01:40:46 +0000 (20:40 -0500)]
agx: Implement formatted loads
These will be generated by the UBO and VBO lowerings. (and eventually by other
lowerings too?)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
Alyssa Rosenzweig [Fri, 25 Nov 2022 01:40:43 +0000 (20:40 -0500)]
agx: Add shift to device_load
We'll use this as an optimization soon. This acts in addition to the format's
shift.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
Alyssa Rosenzweig [Wed, 30 Nov 2022 17:55:35 +0000 (12:55 -0500)]
asahi: Use NIR_PASS_V for agx_nir_lower_tilebuffer
This ensures that printing shaders before and after the NIR pass still works
with the standard NIR debug options.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
Alyssa Rosenzweig [Fri, 25 Nov 2022 01:40:42 +0000 (20:40 -0500)]
nir: Add intrinsics for lowering UBOs/VBOs on AGX
We'll use formatted loads and some system values to lower UBOs and VBOs to
global memory in NIR, using the AGX-specific format support and addressing
arithmetic to optimize the emitted code.
Add the intrinsics and teach nir_opt_preamble how to move them so we don't
regress UBO pushing.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
Lionel Landwerlin [Thu, 1 Dec 2022 21:06:30 +0000 (23:06 +0200)]
intel/nir/rt: switch to workgroup_id_zero_base
RT don't use a base workgroup id so no reason of using workgroup_id.
Additionally the lowering introduced in
b4dd3df227 requires something
provides base_workgroup_id which we don't have for RT as it's not
needed.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b4dd3df227 ("intel/nir: Set has_base_workgroup_id for lower_compute_system_values")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7812
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20115>
Qiang Yu [Sun, 9 Oct 2022 02:30:24 +0000 (10:30 +0800)]
radeonsi: cleanup si_llvm_build_vs_exports gfx11 code
It's now completely handled in ac_nir_lower_ngg.c
export_vertex_params_gfx11.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Sun, 3 Jul 2022 09:32:33 +0000 (17:32 +0800)]
ac/llvm: remove unused llvm cull
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Thu, 16 Jun 2022 10:25:56 +0000 (18:25 +0800)]
radeonsi: remove unused ngg llvm code
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Sun, 12 Jun 2022 13:02:26 +0000 (21:02 +0800)]
radeonsi: replace llvm ngg gs with nir lowering
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Sun, 12 Jun 2022 12:36:39 +0000 (20:36 +0800)]
radeonsi: replace llvm ngg vs/tes with nir lowering
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Sat, 23 Jul 2022 10:30:45 +0000 (18:30 +0800)]
radeonsi: fix NGG VS primitive ID load
When NGG VS need to export primitive ID, it will load it in GS
threads, so need to use gs_prim_id arg. Current nir to llvm
translator check vs_prim_id present to use vs_prim_id first.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Fri, 22 Jul 2022 12:01:26 +0000 (20:01 +0800)]
radeonsi: implement two lds base load intrinsics
LDS will be accessed starting from esgs_ring which has offset 0.
So ngg_scratch and ngg_emit base address is just the offset from
the esgs_ring base.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Sat, 11 Jun 2022 07:29:50 +0000 (15:29 +0800)]
radeonsi: implement export_vertex abi
Used by ngg lower.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Mon, 26 Sep 2022 06:36:55 +0000 (14:36 +0800)]
radeonsi: implement nir_intrinsic_load_provoking_vtx_in_prim_amd
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
Qiang Yu [Wed, 8 Jun 2022 03:09:35 +0000 (11:09 +0800)]
radeonsi: use nir_lower_gs_intrinsics
Replace some llvm code.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
David Heidelberg [Thu, 1 Dec 2022 22:16:14 +0000 (23:16 +0100)]
ci/zink: add missing spec@!opengl 1.1@masked-clear flake
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20119>
Giancarlo Devich [Thu, 1 Dec 2022 19:57:04 +0000 (11:57 -0800)]
wgl: Fix build break when LLVMPIPE and SOFTPIPE are both off
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20114>
David Heidelberg [Fri, 18 Nov 2022 22:54:31 +0000 (23:54 +0100)]
ci/cross: switch from the debcrossgen to the meson env2mfile
Modern Debian recommends to use `meson env2mfile` rather than `debcrossgen`:
```
WARNING: this tool is deprecated, use "meson env2mfile" instead.
```
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7740
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19863>
David Heidelberg [Thu, 24 Nov 2022 22:44:47 +0000 (23:44 +0100)]
ci/arm_build: follow x86 and install newer Meson
This allows us utilize meson env2mfile.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19863>
David Heidelberg [Fri, 18 Nov 2022 23:10:34 +0000 (00:10 +0100)]
ci/meson: bump to 0.63.3
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19863>
David Heidelberg [Fri, 18 Nov 2022 23:07:59 +0000 (00:07 +0100)]
ci/x86: Remove meson from apt when we later install it with pip
But install Ninja, which is needed.
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19863>
David Heidelberg [Sat, 26 Nov 2022 20:29:38 +0000 (21:29 +0100)]
ci: CI should handle also arrays in meson cross-file
The new meson env2mfile generates everything in the arrays.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19863>
Eric Engestrom [Thu, 24 Nov 2022 10:27:57 +0000 (10:27 +0000)]
meson: sort drivers alphabetically in any-of checks
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19977>
Eric Engestrom [Wed, 26 Oct 2022 10:26:15 +0000 (11:26 +0100)]
meson: make long any-of checks easier to read and to update
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19977>
Eric Engestrom [Mon, 18 Apr 2022 16:27:15 +0000 (17:27 +0100)]
meson: replace deprecated meson.get_cross_property(...) with meson.get_external_property(...)
According to the deprecation note:
> It's a pure subset of meson.get_external_property, and works strangely
> in host == build configurations, since it would be more accurately
> described as get_host_property.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19904>
Rhys Perry [Mon, 28 Nov 2022 19:18:32 +0000 (19:18 +0000)]
aco: improve do_pack_2x16() with zero constants
We can skip the v_or_b32 or use an instruction smaller than
v_alignbyte_b32.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19933>
Rhys Perry [Wed, 16 Nov 2022 17:42:20 +0000 (17:42 +0000)]
aco: use v_minmax/v_maxmin opcodes
fossil-db (gfx1100):
Totals from 29868 (22.12% of 135032) affected shaders:
MaxWaves: 741336 -> 741344 (+0.00%)
Instrs:
34624902 ->
34539766 (-0.25%); split: -0.25%, +0.00%
CodeSize:
187196804 ->
187192100 (-0.00%); split: -0.01%, +0.01%
VGPRs:
1816860 ->
1816788 (-0.00%); split: -0.01%, +0.01%
Latency:
502597202 ->
502245627 (-0.07%); split: -0.08%, +0.01%
InvThroughput:
84813176 ->
84586122 (-0.27%); split: -0.28%, +0.01%
VClause: 633826 -> 633749 (-0.01%); split: -0.02%, +0.01%
SClause:
1317738 ->
1317047 (-0.05%); split: -0.06%, +0.01%
Copies:
2130610 ->
2130954 (+0.02%); split: -0.03%, +0.05%
Branches: 766093 -> 765969 (-0.02%); split: -0.02%, +0.00%
PreSGPRs:
1630250 ->
1630034 (-0.01%); split: -0.02%, +0.00%
PreVGPRs:
1590777 ->
1590664 (-0.01%); split: -0.01%, +0.00%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19933>
Rhys Perry [Wed, 16 Nov 2022 18:10:38 +0000 (18:10 +0000)]
aco: change order in combine_minmax()
Prepare for future optimizations.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19933>
Rhys Perry [Wed, 16 Nov 2022 17:08:09 +0000 (17:08 +0000)]
aco/gfx11: use v_cvt_i32_i16/v_cvt_u32_u16
fossil-db (gfx1100):
Totals from 52753 (39.07% of 135032) affected shaders:
CodeSize:
153603860 ->
153163384 (-0.29%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19933>
Danylo Piliaiev [Thu, 1 Dec 2022 13:14:23 +0000 (14:14 +0100)]
ir3: Reduce the maximum allowed imm offset for shared var load/store
STL/LDL have 13 bits to store imm offset. However the most significant
bit in the offset is a sign bit, so the positive offset is limited by
12 bits.
nir_opt_offsets only has the upper limit and doesn't deal with
negative offsets, so shared_max should be changed to `(1 << 12) - 1`.
The issue was found in "Monster Hunter: World".
Fixes: 0b2da9d795610df15346a594384c39a096be338f
("ir3: Limit the maximum imm offset in nir_opt_offset for shared vars")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20100>
Connor Abbott [Thu, 1 Dec 2022 13:45:02 +0000 (14:45 +0100)]
tu: Don't prefetch descriptors for inline uniforms
This could result in hangs if the entire descriptor set was inline
uniforms. Fixes
dEQP-VK.binding_model.descriptorset_random.sets4.dynindexed.ubolimitlow.nosbo.nosampledimg.outimgonly.iublimitlow.nouab.comp.noia.0
after
0a0a04bd made us prefetch descriptors again and uncovered this.
Fixes: 37cde2c6 ("tu: Rewrite inline uniform implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20101>
Jasber Chen [Wed, 23 Nov 2022 02:14:31 +0000 (10:14 +0800)]
frontends/va: partially updating RefPicList depends on slice type
problem casused by one frame with multiple slices and different slices type.
Invalid referenced values came from slice P/I would overwrite previous update.
Signed-off-by: Jasber Chen <yipeng.chen@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19943>
Chia-I Wu [Wed, 30 Nov 2022 21:32:55 +0000 (13:32 -0800)]
Revert "freedreno/a6xx: Remove unneeded MSAA clear fallback"
This reverts commit
ded82cf4bdd9a74eded2a9a95ab14e2c0d907c0a and fixes
$ deqp-gles31 --deqp-gl-config-name=rgba8888d24s8ms4 \
-n dEQP-GLES31.functional.primitive_bounding_box.depth.*
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20085>
Samuel Pitoiset [Wed, 30 Nov 2022 09:12:38 +0000 (10:12 +0100)]
radv,driconf: fix static driconf by parsing 00-radv-defaults.conf
Otherwise when xmlconfig is disabled, drirc workarounds aren't applied
with RADV.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7785
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20077>
Samuel Pitoiset [Wed, 30 Nov 2022 09:36:40 +0000 (10:36 +0100)]
driconf: add support for multiple input files in the static script
RADV has its own drirc file and this is required to fix the static
driconf path.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20077>
Jordan Justen [Tue, 26 Jan 2021 07:01:52 +0000 (23:01 -0800)]
intel/dev: Add (disabled) device info for MTL
Reworks:
* Jordan: INTEL_PLATFORM_MTL_M/INTEL_PLATFORM_MTL_P
* Lionel: .has_coarse_pixel_primitive_and_cb
* Jordan: .has_mesh_shading & .has_ray_tracing
* Paulo: .has_64bit_float
* José: .has_integer_dword_mul (BSpec: 47431)
* Jordan: Comment pci device ids for now similar to DG2:
*
70a4e646852 ("intel: Add *disabled* device ids for DG2")
*
ad565f6b70d ("intel/dev: Enable first set of DG2 PCI IDs")
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19658>
Matt Coster [Fri, 28 Oct 2022 16:09:56 +0000 (17:09 +0100)]
pvr: debug: Print hexdump at the end of all sub buffers
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
Matt Coster [Fri, 28 Oct 2022 16:07:09 +0000 (17:07 +0100)]
pvr: debug: Add option to zero-alloc all buffer objects
This is designed for use by the control stream dump debug option, but
can also be used any time deterministic buffer state is desired.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
Matt Coster [Thu, 1 Sep 2022 10:26:32 +0000 (11:26 +0100)]
pvr: debug: Print hexdump for referenced buffers with unknown encoding
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
Matt Coster [Thu, 1 Sep 2022 10:21:52 +0000 (11:21 +0100)]
pvr: debug: Add offset address field type for dumps
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
Matt Coster [Thu, 1 Sep 2022 10:10:31 +0000 (11:10 +0100)]
pvr: debug: Include hexdump after each block in control stream dump
This makes it easier to quickly identify the raw words associated with
decoded values.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
Matt Coster [Thu, 1 Sep 2022 09:08:11 +0000 (10:08 +0100)]
pvr: debug: Enhancements to hex dumps
Contains the following enhancements & fixes:
- Increase (decrease?) the granularity to single bytes rather than
using an arbitrary word size,
- Remove some spurious semicolons at the end of macros, and
- Do not collapse sections of zero bytes that consist of only a single
line.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
Karmjit Mahil [Mon, 21 Nov 2022 15:51:52 +0000 (15:51 +0000)]
pvr: Remove a todo in vkCmdEndRenderPass2().
The first end_sub_cmd() is to make sure that we end the last sub_cmd.
The end_sub_cmd() in pvr_resolve_unemitted_resolve_attachments() makes
sure that we end any transfer sub_cmds created in there.
Suggested-by: Frank Binns <frank.binns@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19957>
Karmjit Mahil [Mon, 21 Nov 2022 15:38:07 +0000 (15:38 +0000)]
pvr: Replace sub_cmd flags with bools within each sub_cmd type.
This commit remove:
- PVR_SUB_COMMAND_FLAG_TRANSFER_SERIALIZE_WITH_FRAG.
- PVR_SUB_COMMAND_FLAG_OCCLUSION_QUERY.
The first flag was specific to transfer sub commands and the last
one, for graphics ones. Now we just have a bool in the transfer
sub_cmd, and one in the graphics sub_cmd.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19957>
Karmjit Mahil [Wed, 16 Nov 2022 17:00:38 +0000 (17:00 +0000)]
pvr: Handle PVR_SUB_COMMAND_FLAG_OCCLUSION_QUERY.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19957>
Karmjit Mahil [Wed, 16 Nov 2022 16:38:18 +0000 (16:38 +0000)]
pvr: Handle PVR_SUB_COMMAND_FLAG_TRANSFER_SERIALIZE_WITH_FRAG.
The flag was previously named PVR_SUB_COMMAND_FLAG_WAIT_ON_PREVIOUS_FRAG.
Since the next fragment job is also made to wait for the transfer
job to complete, the previous name might have been a bit misleading.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19957>
Iago Toral Quiroga [Thu, 1 Dec 2022 10:02:12 +0000 (11:02 +0100)]
v3dv: fix job serialization for single sync path
The idea in the single sync path is that we serialize any job that
needs to wait, however, our ANY queue syncobj only tracks the last job
submitted to any hardware queue, so in practice when we wait on this
we are only serializing against the queue to which we have submitted
the last job, which is not correct.
Fix that by accumulating the last job sync into the ANY queue synbcobj
to ensure that waiting on this syncobj effectively waits on all
hardware queues.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
Iago Toral Quiroga [Thu, 1 Dec 2022 09:59:17 +0000 (10:59 +0100)]
v3dv: make single-sync paths more explicit
Instead of having functions that return early in multi-sync mode
let's only call them when we are in single-sync mode. I think this
makes the code more explicit.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
Boris Brezillon [Tue, 20 Apr 2021 09:03:29 +0000 (11:03 +0200)]
panfrost: Add NATIVE_FENCE_FD cap
Add support for NATIVE_FENCE_FD so panfrost can advertise support for
EGL_ANDROID_native_fence_sync.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19774>
Boris Brezillon [Wed, 30 Nov 2022 09:00:02 +0000 (10:00 +0100)]
panfrost: Move fence code to pan_fence.{c,h}
Before adding support for NATIVE_FENCE_FD, let's move the fencing logic
to a dedicated file to avoid spreading the code in different places.
Suggested-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19774>
Boris Brezillon [Wed, 16 Nov 2022 09:48:34 +0000 (10:48 +0100)]
panfrost: Destroy panfrost_context::syncobj in the ctx desctruction path
Destroy panfrost_context::syncobj in the ctx desctruction path so we
don't leak a sync object.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19774>
Qiang Yu [Tue, 29 Nov 2022 03:15:17 +0000 (11:15 +0800)]
ac/nir/ngg: rename nogs 16bit output mask and var
To represent 16bit outputs more clearly.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19697>
Qiang Yu [Sat, 12 Nov 2022 03:58:03 +0000 (11:58 +0800)]
ac/nir/ngg: gs support 16bit outputs
radeonsi uses 16bit varying slots.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19697>
Qiang Yu [Sun, 13 Nov 2022 08:36:26 +0000 (16:36 +0800)]
ac/nir/ngg: gs skip check bit size before nir_u2u
nir_u2u do for us.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19697>
Qiang Yu [Sun, 13 Nov 2022 08:30:39 +0000 (16:30 +0800)]
ac/nir/ngg: gs store output use src_type index for type info
More precise type info, can be used for 16bit output streamout
to convert 16bit int/uint/float to 32bit one later.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19697>
Qiang Yu [Sat, 12 Nov 2022 13:24:08 +0000 (21:24 +0800)]
ac/nir/ngg: gs use u_foreach_bit64 to loop all output slots
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19697>
Qiang Yu [Fri, 11 Nov 2022 10:46:40 +0000 (18:46 +0800)]
ac/nir/ngg: reduce nogs 16bit output gather space
Max slot number for 16bit output is 16, so no need to use
64 array size for them.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19697>
Jason Ekstrand [Thu, 15 Sep 2022 23:31:06 +0000 (18:31 -0500)]
util/dynarray: Add an append_array helper
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19685>
Marcin Ślusarz [Mon, 24 Oct 2022 12:59:41 +0000 (14:59 +0200)]
intel/compiler: user payload starts after TUE header & its padding
All data written by the user are offset by TUE header size.
Without this patch we copy the correct amount of user data, but both
"from" and "to" offsets are wrong.
Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
Marcin Ślusarz [Mon, 24 Oct 2022 12:55:38 +0000 (14:55 +0200)]
nir/lower_task_shader: allow offsetting of the start of payload
We need this, because on Intel task payload starts with private header,
followed by user-accessible data.
Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
Marcin Ślusarz [Fri, 21 Oct 2022 13:49:52 +0000 (15:49 +0200)]
intel/compiler: adjust [store|load]_task_payload.base too
Base also needs to be converted from bytes to words.
Fixes: c36ae42e4cc ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
David Heidelberg [Thu, 1 Dec 2022 10:38:56 +0000 (11:38 +0100)]
ci/zink: add lavapipe flakes
Listed from: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7613
Bug: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7781
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20093>
Erik Faye-Lund [Tue, 27 Sep 2022 07:57:10 +0000 (09:57 +0200)]
zink: do not complain about missing line-stipple support
We can lower this now, so let's not complain about it...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Tue, 27 Sep 2022 11:23:04 +0000 (13:23 +0200)]
zink: lower line stipple
This lowers line-stippling to a combination of geometry and fragment
shaders:
- The geometry shader computes the length of each line-segment, and
outputs a varying that produces the stipple position.
- The fragment shader looks up the stipple position in the
stipple-pattern once per sample, and updates the sample mask
accordingly.
In case there's no geometry shader in place, we create a new
pass-through shader.
We should probably not declare the the push-constants in the pipeline
layout unless they're actually needed. But we already do this
unconditionally for the vertex shader and tesselation push-constants, so
let's do it unconditionally for these as well for now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Thu, 3 Nov 2022 11:45:47 +0000 (12:45 +0100)]
zink: allow to generate any vertex shader stage
There's times when it's going to be useful to generate geometry shaders
as well, so let's generalize the infrastructure for generated shader
stages a bit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Thu, 17 Nov 2022 11:15:54 +0000 (12:15 +0100)]
zink: process non-optimal-key passes first
Right now, it's only the vertex-shader that needs special handling for
non-optimal keys. That makes it possible to use fallthrough to always
end up in the last-vertex-stage conditional.
But we're about to add special handling for the geometry stage as well,
so let's prepare by splitting the switch-statement in two; one that only
happens for non-optimal keys, and does all the needed processing there,
and one that deals with the rest.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Tue, 27 Sep 2022 07:43:11 +0000 (09:43 +0200)]
zink: give gs its own shader-key
Line-stipple lowering is going to need some geometry-shader specific
lowering, so lets give the GS its own shader-key struct.
The GS variant only needs a non-optimal variant, so let's assert that to
be sure.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Wed, 26 Oct 2022 13:38:03 +0000 (15:38 +0200)]
zink: emit vars with nir_var_shader_temp mode
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Tue, 27 Sep 2022 07:35:54 +0000 (09:35 +0200)]
zink: add line-stippling lowering passes
There's two notable limitations here:
- This will viewport-map to viewport #0 only. This is because we need
the viewport-scale factors, which we'll be uploading using
push-constants. And we don't want to waste too many of those...
- It's missing a "global" stipple-counter. It doesn't seem like there's
a portable way of implementing this, so this is going to require a VK
extension that can be implemented in a hardware-specific way in the
long run. For now, let's just ignore the global stipple counter.
These two limitations don't seem viable to overcome for now, so but this
is better than nothing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Tue, 27 Sep 2022 10:53:03 +0000 (12:53 +0200)]
zink: setup driver-workaround for missing linestipple
This is not ideal, but at least it should work. In the long run, we
might want to store a bit per mode we're missing, so we can do this
conditionally. But that's quite a bit more complicated, so let's go with
this for now.
The line-stippling logic needs non-optimal shader-keys. So let's drop
some perf on the floor here.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
David Heidelberg [Wed, 30 Nov 2022 09:55:08 +0000 (10:55 +0100)]
ci/alpine: disable the job, still occasionally flakes
See: https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
32689466
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20076>
Emma Anholt [Mon, 28 Nov 2022 19:27:09 +0000 (11:27 -0800)]
glx: Require __DRI_SWRAST >= 4 for doing swrast.
The only implementer in tree is v4.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:25:01 +0000 (11:25 -0800)]
egl: Refactor common error handling for context creation.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:24:15 +0000 (11:24 -0800)]
egl: Bump minimum version of __DRI_SWRAST to 4.
The only implementer in tree is v4. This simplifies some bits now that we
always have CreateContextAttribs.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:22:23 +0000 (11:22 -0800)]
glx: Require __DRI_DRI2 v2 for doing X11 DRI2.
The only implementer in tree is v4.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:20:57 +0000 (11:20 -0800)]
egl: Require __DRI_DRI2 v4 if we're to do DRI2.
The only in-tree implementers are v4.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:19:07 +0000 (11:19 -0800)]
egl: Bump __DRI_CONFIG_OPTIONS min version to 2.
The only implementer in tree is v2.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:12:44 +0000 (11:12 -0800)]
egl: Bump minimum version of __DRI_IMAGE to 6 and drop version checks.
All __DRI_IMAGEs in tree are v6+ (lowest being drisw) and implement
createImageFromTexture.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:08:56 +0000 (11:08 -0800)]
egl: Bump required version of optional __DRI2_FENCE to 2.
The only implementer of it in tree is v2, so no need for checks.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:34:58 +0000 (11:34 -0800)]
gbm: Bump required __DRI_IMAGE version to 6.
That's the minimum implemented in tree (gallium swrast). Drops a few more
version checks.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Wed, 23 Nov 2022 00:58:08 +0000 (16:58 -0800)]
gbm: Drop support for __DRI_DRI2 < 4 and __DRI_SWRAST < 4.
We're always loading a gallium driver built from this tree, so it's always
v4.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Sat, 26 Nov 2022 05:44:18 +0000 (21:44 -0800)]
dri: Add notes on what part of the loader interface are used by Xorg.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Connor Abbott [Tue, 29 Nov 2022 14:56:39 +0000 (15:56 +0100)]
freedreno/fdl: Set sRGB bit for storage images
This probably wasn't noticed earlier because tests using sRGB storage
images didn't exist, and we didn't know whether this works, but this
fixes dEQP-VK.image.store.without_format.2d.*_srgb which also proves
that the bit works.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20060>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:57:25 +0000 (19:57 -0500)]
agx: Clamp point sizes
Fixes vs-point_size-zero.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:46:15 +0000 (19:46 -0500)]
agx: Handle 32-bit gl_FragCoord.zw
The coefficient register is 16-bit so our builder will make the iter 16-bit too
(maybe not the best design...), force fp32 to match the NIR intrinsic.
Fixes glsl-fs-fragcoord-zw-ortho
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:37:25 +0000 (19:37 -0500)]
agx: Handle large varying indices
Fixes glsl-max-varyings.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Fri, 25 Nov 2022 22:06:40 +0000 (17:06 -0500)]
asahi: Support one-sided polygon modes
We can implement glPolygonMode(GL_FRONT_AND_BACK, ...) natively. What we can't
implement natively are two-sided polygon modes. For that Apple has a nontrivial
lowering which I don't feel the need to implement unless someone actually hits a
workload other than Piglit that uses it.
Vulkan requires only one-sided polygon modes (so this is sufficient there), and
GLES doesn't have polygon modes at all. If an app hits the unimplemented case,
throw a warning like Zink does.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 03:19:12 +0000 (22:19 -0500)]
asahi: Handle NULL sampler views
Fixes fp-fragment-position (crash->pass).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 03:08:23 +0000 (22:08 -0500)]
asahi: Unset GL_CLAMP
Use the Zink lowering for the legacy mode, it's not too many instructions on AGX
anyway. Fixes texwrap tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:27:20 +0000 (19:27 -0500)]
asahi: Set frag coord caps correctly
Fixes ./glsl-arb-fragment-coord-conventions, c.f.
12facf23b1f ("panfrost: Don't set CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER").
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:10:54 +0000 (19:10 -0500)]
asahi: Set PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
Fixes arb-provoking-vertex-render.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Fri, 25 Nov 2022 23:53:17 +0000 (18:53 -0500)]
asahi: Set PIPE_CAP_SUPPORTED_PRIM_MODES
To lower GL_POLYGONS which we don't do natively. Fixes a pile of crashes in
Piglit.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Jason Ekstrand [Tue, 29 Nov 2022 20:08:50 +0000 (14:08 -0600)]
hasvk: Drop anv_nir_add_base_work_group_id()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 20:08:22 +0000 (14:08 -0600)]
anv: Drop anv_nir_add_base_work_group_id()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 20:05:19 +0000 (14:05 -0600)]
intel/nir: Set has_base_workgroup_id for lower_compute_system_values
This option didn't exist half a decade ago when I first implemented base
workgroup support in ANV. It's cleaner to just have split system values
like all the other zero_base+base things do.
We currently only do this for COMPUTE and not KERNEL because it lets us
avoid changing intel_clc for now. We can add KERNEL later if needed.
We also don't do this lowering for task/mesh.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 20:04:50 +0000 (14:04 -0600)]
hasvk: Implement lower_base_workgroup_id
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 20:03:54 +0000 (14:03 -0600)]
anv: Implement lower_base_workgroup_id
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 19:58:29 +0000 (13:58 -0600)]
crocus: Lower load_base_workgroup_id to zero
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
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