Chris Wilson [Wed, 6 May 2015 10:19:44 +0000 (11:19 +0100)]
i965: Pass the map-mode along to intel_mipmap_tree_map_raw()
Since we can distinguish when mapping between READ and WRITE, we can
pass along the map mode to avoid stalls and flushes where possible.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Thu, 18 May 2017 19:02:39 +0000 (12:02 -0700)]
i965: Add a cache_coherent field to brw_bo
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 11 May 2017 18:53:27 +0000 (11:53 -0700)]
i965: Remove unused 'use_resource_streamer' field
Missing in the resource streamer removal of commit
951f56cd43bc.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Fri, 5 May 2017 18:20:05 +0000 (11:20 -0700)]
i965: Remove brw_bo's virtual member
Just return the map from brw_map_bo_*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 3 May 2017 21:19:11 +0000 (14:19 -0700)]
i965: Remove unused brw_bo_map__* functions
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alex Smith [Mon, 5 Jun 2017 14:49:05 +0000 (15:49 +0100)]
anv: Set better descriptor set limits
Based on discussions with Jason, Ivy Bridge and Bay Trail only actually
support 16 samplers, while newer hardware can support more than the
current limit of 64. Therefore set the lower limit where needed, and
bump up to 128 for everything else. There is also a limit on the total
number of other resources of around 250.
This allows Dawn of War III to render correctly on ANV.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alex Smith [Tue, 6 Jun 2017 09:42:41 +0000 (10:42 +0100)]
anv: Set driver version to Mesa version
As already done by RADV.
v2: Move version calculation function to src/vulkan/util to share with
RADV.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alex Smith [Tue, 6 Jun 2017 15:09:07 +0000 (16:09 +0100)]
radv/vulkan: Move radv_get_driver_version to src/vulkan/util
This means it can be reused for other Vulkan drivers. Also fix up a
typo, need to search for '.' in the version string rather than ','.
v2: Remove unneeded temporary version variable (Emil, Eric)
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alex Smith [Tue, 6 Jun 2017 11:31:05 +0000 (12:31 +0100)]
util/vulkan: Move Vulkan utilities to src/vulkan/util
We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.
v2: Android build system changes (from Tapani Pälli)
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Tue, 30 May 2017 19:06:48 +0000 (20:06 +0100)]
intel: gen-decoder: rework how we handle groups
The current way of handling groups doesn't seem to be able to handle
MI_LOAD_REGISTER_* with more than one register. This change reworks
the way we handle groups by building a traversal list on loading the
GENXML files.
Let's say you have
Instruction {
Field0
Field1
Field2
Group0 (count=2) {
Field0-0
Field0-1
}
Group1 (count=4) {
Field1-0
Field1-1
}
}
We build of linked on load that goes :
Instruction -> Group0 -> Group1
All of those are gen_group structures, making the traversal trivial.
We just need to iterate groups for the right number of timers (count
field in genxml).
The more fancy case is when you have only a single group of unknown
size (count=0). In that case we keep on reading that group for as long
as we're within the DWordLength of that instruction.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Marek Olšák [Tue, 23 May 2017 19:52:11 +0000 (21:52 +0200)]
radeonsi: fix a GPU hang with tessellation on 2-CU configs
Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced
to 2 CUs.
Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:49 +0000 (14:31 +0200)]
mesa: make use of NewWindowRectangles driver flags
Now, st_update_window_rectangles() won't be called when the
scissor is going to be updated.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:48 +0000 (14:31 +0200)]
mesa: add new gl_driver_flags::NewWindowRectangles
This new driver flag will replace _NEW_SCISSOR which is
emitted when setting new window rectangles but it actually
triggers useless changes in the state tracker (like scissor
and rasterizer).
EXT_window_rectangles is currently only supported by Nouveau.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:47 +0000 (14:31 +0200)]
mesa: remove call to Driver.Scissor() in _mesa_WindowRectanglesEXT()
This is actually useless because this driver call is only used
by the classic DRI drivers which don't support that extension
and probably won't never support it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:49 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when min sample shading changes
We usually check that given parameters are different before
updating the state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:48 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when sample mask changes
We usually check that given parameters are different before
updating the state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:47 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when coverage parameters change
We usually check that given parameters are different before
updating the state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Sat, 3 Jun 2017 19:26:29 +0000 (12:26 -0700)]
i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.
We moved to INTEL_SCALAR_* when we added more than a single stage, but
never went back and converted the VS to work that way. Be consistent.
Also update the documentation to actually mention these debug variables.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Mon, 15 May 2017 01:27:10 +0000 (11:27 +1000)]
radv: expose integrated device type for APUs.
This just sets the vulkan device type depending on whether
this is an APU or GPU.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Bas Nieuwenhuizen [Sun, 21 May 2017 21:40:54 +0000 (23:40 +0200)]
ac/surface: Fix HTILE for radv.
We always compute HTILE size using addrlib, even when not TC compatible.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlied <airlied@redhat.com>
Dave Airlie [Tue, 6 Jun 2017 00:39:16 +0000 (10:39 +1000)]
radv: fix write event eop on vega.
Typo here, fixes command submission hangs on vega
Dave Airlie [Mon, 5 Jun 2017 23:06:57 +0000 (09:06 +1000)]
radv: enable GFX9 on radv
I'm open to reverting this closer to release if bad things
happen, but it might be easier to debugging to leave it for now.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:06:41 +0000 (09:06 +1000)]
radv: turn off geom/tess for gfx9.
We don't support these yet, and it'll take a bit of work to do so.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:06:21 +0000 (09:06 +1000)]
radv: misc GFX9 changes.
These are just some register changes ported from radeonsi for gfx9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:05:47 +0000 (09:05 +1000)]
radv: add some GFX9 specific events.
These are ported from radeonsi, don't know all the rules for
when they should be inserted.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:05:12 +0000 (09:05 +1000)]
radv: add IA_MULTI_VGT_PARAM support for GFX9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:03:55 +0000 (09:03 +1000)]
radv: add rb+ support for GFX9
This adds some rb+ support, as on GFX9 we have to disable
it as per radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:01:48 +0000 (09:01 +1000)]
radv: add GFX9 cache flushing support.
GFX9 needs to write event EOP to a fence buffer, allocate some
space for this, and just write an ever increasing number to it,
this isn't exactly what radeonsi does, but it seems to work.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:54:38 +0000 (08:54 +1000)]
radv: add texture descriptor/fmask/cmask support for GFX9
This adds gfx9 support for the texture descriptor along
with the fmask/cmask allocation routines.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:50:14 +0000 (08:50 +1000)]
radv: add GFX9 to initialisation cmd buffer.
This just adds support for initialising some GFX9 registers,
and handles the different init for the VGT reuse reg.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:48:25 +0000 (08:48 +1000)]
radv: don't setup raster_config on gfx9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:47:22 +0000 (08:47 +1000)]
radv: add gfx9 cp dma support.
This adds support to the CP dma code for GFX9, ported from
radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:39:44 +0000 (08:39 +1000)]
radv: add gfx9 depth/stencil surface support.
This is ported from radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:38:36 +0000 (08:38 +1000)]
radv: add GFX9 support for color surfaces.
This is ported from radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:33:53 +0000 (08:33 +1000)]
radv: add some misc gfx9 pieces.
This just adds the strings and includes the gfx9 register defs
in some files that we need them in.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:36:24 +0000 (08:36 +1000)]
radv: set offchip hs param like radeonsi.
radeonsi never uses 512 here anymore.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:58:54 +0000 (08:58 +1000)]
radv: fix typo in comment.
Dave Airlie [Mon, 5 Jun 2017 22:43:38 +0000 (08:43 +1000)]
radv: add a comment from radeonsi before cp dma function.
This is just copied over.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:27:35 +0000 (08:27 +1000)]
radv: remove doubled up prototype.
Must have snuck in during a rebase.
Dave Airlie [Wed, 24 May 2017 01:37:06 +0000 (11:37 +1000)]
radv: split metadata struct into legacy/gfx9 parts.
This is just ported from radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 01:09:30 +0000 (02:09 +0100)]
radv: refactor some texture descriptor state.
This just splits out some non-gfx9 bits in advance to avoid
regressions.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 01:05:59 +0000 (02:05 +0100)]
radv: refactor color surface init before gfx9.
This just moves the code around in preparation for gfx9 support.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 01:01:10 +0000 (02:01 +0100)]
radv: refactor depth/stencil state setup
In advance of GFX9 to reduce chances for regression, refactor
this code out so adding the GFX9 changes will be more obvious.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 02:07:26 +0000 (12:07 +1000)]
radv: use radv_foreach_stage in a couple of places.
This just collapses a few per-stage things into a loop,
shouldn't affect anything.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Emil Velikov [Wed, 31 May 2017 20:08:45 +0000 (15:08 -0500)]
radeon: remove out of date LLVM_REVISION.txt
The file was introduced to track which LLVM revision was required, yet
that has quickly gone out of shape.
It has seen no updates since 2013.
Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Aaron Watry <awatry@gmail.com>
Juan A. Suarez Romero [Mon, 5 Jun 2017 21:21:35 +0000 (21:21 +0000)]
docs: update calendar, add news item and link release notes for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Mon, 5 Jun 2017 21:15:43 +0000 (21:15 +0000)]
docs: add sha256 checksums for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
4908b1e909ba4cfd5391f61ea551d21cccb52e2f)
Juan A. Suarez Romero [Mon, 5 Jun 2017 20:27:24 +0000 (20:27 +0000)]
docs: add release notes for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
97f6404e50212fb65fe047e467f5497bcba5b8ac)
Brian Paul [Mon, 5 Jun 2017 20:13:14 +0000 (14:13 -0600)]
gallium/u_threaded: fixes for MSVC
Replace some static assertions with runtime assertions. The static
asserts don't work/fail on MSVC, despite the offsets being multiples
of 16 (checked with softpipe).
Use correct parameter types for a few gallium context functions.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Mon, 5 Jun 2017 03:34:05 +0000 (13:34 +1000)]
r600: refactor out some compressed resource state code.
This just takes this out to a separate function as it will
get more complex with images.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 03:25:29 +0000 (13:25 +1000)]
r600: document some of the missing shader constants.
These are used for fragment shader thread calculations.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 03:24:12 +0000 (13:24 +1000)]
r600: add register info for atomic counters.
The atomic counters on evergreen are implemented via append/consume
UAV counters. This just adds the register info for them. The EOS
packets are used to get the atomic totals extracted post shader
execution for storing into a buffer.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 03:22:07 +0000 (13:22 +1000)]
r600: add missing RAT registers and operations.
This just documents in the headers the RAT operation list,
and the RAT encoding for exports.
The immediate registers are used to point to buffers for the
RAT return values (_RTN instructions).
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 19:38:34 +0000 (05:38 +1000)]
r600/sb: fix typo in field definitions
Pointed out by glennk.
Marek Olšák [Tue, 30 May 2017 00:04:29 +0000 (02:04 +0200)]
tgsi/scan: fix scanning fragment shaders with PrimID and Position/Face
Not relevant to radeonsi, because Position/Face are system values
with radeonsi, while this codepath is for drivers where Position and
Face are ordinary inputs.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jason Ekstrand [Fri, 26 May 2017 17:57:33 +0000 (10:57 -0700)]
i965: Finalize miptrees before prepare_texture
In order to do resolves for texture views with different formats, we
need intel_texture_object::_Format to be valid. Calling
intel_finalize_mipmap_tree can safely be done multiple times in a row
and should be a fairly cheap operation.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Marek Olšák [Tue, 30 May 2017 23:46:40 +0000 (01:46 +0200)]
gallium/u_threaded: remove 16 bytes from tc_batch
All other sentinels occupy what is otherwise unused space.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Tue, 30 May 2017 23:32:01 +0000 (01:32 +0200)]
gallium/u_threaded: align batches and call slots to 16 bytes
not sure if this helps
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Wed, 31 May 2017 11:07:04 +0000 (13:07 +0200)]
st/mesa: don't load cached TGSI shaders on demand
This fixes a performance issue with the shader cache that delayed Gallium
shader create calls until draw calls.
I'd like this in stable, but it's not a showstopper.
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Chih-Wei Huang [Sun, 4 Jun 2017 04:53:01 +0000 (12:53 +0800)]
Android: use bionic pthread_barrier_* if possible
The pthread_barrier_* functions were introduced to bionic
since Nougat.
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Dave Airlie [Mon, 5 Jun 2017 03:19:18 +0000 (13:19 +1000)]
r600: fix incorrect and missing bit field in register headers.
The compression field was incorrect, and we were missing the
depth before shader field.
Nicolai Hähnle [Thu, 11 May 2017 23:46:46 +0000 (01:46 +0200)]
radv: use ac_compute_surface
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 14 May 2017 23:43:25 +0000 (09:43 +1000)]
radv: prepare fmask surface creation
The old code copied over all the surface info from the image
surface, we only want some bits of it, and to modify the flags.
This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.*
and others in the subsequent switch to ac_compute_surface.
v2:
- also disable opt4Space in radv_amdgpu_surface, so that we can
apply this patch separately *before* switching to ac_compute_surface
and hopefully avoid intermittent regressions (Nicolai)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 11 May 2017 23:38:49 +0000 (01:38 +0200)]
radv: use amdgpu_addr_create
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Thu, 11 May 2017 23:38:30 +0000 (01:38 +0200)]
radv: stop using radv_amdgpu_winsys::family
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Thu, 11 May 2017 23:11:27 +0000 (01:11 +0200)]
radv: use ac_gpu_info
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Thu, 11 May 2017 22:56:06 +0000 (00:56 +0200)]
radv: remove radeon_info::name
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 21:01:00 +0000 (23:01 +0200)]
radv: use ac_surface data structures
This is mostly mechanical changes of renaming types and introducing
"legacy" everywhere.
It doesn't use the ac_surface computation functions yet.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:41:36 +0000 (22:41 +0200)]
radv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}
To match radeonsi / ac_surface.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:33:13 +0000 (22:33 +0200)]
radv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREE
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:25:15 +0000 (22:25 +0200)]
radv: remove radeon_surf_level::nblk_z
We're not using thick tiling modes, so we can just derive the value
ourselves.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:20:37 +0000 (22:20 +0200)]
radv: remove radeon_surf_level::dcc_enabled
Like radeonsi; replace with radeon_surf::num_dcc_levels.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:14:39 +0000 (22:14 +0200)]
radv: remove radeon_surf_level::pitch_bytes
Like radeonsi. This saves memory, and the information can easily be
recomputed on the fly where necessary.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:05:52 +0000 (22:05 +0200)]
radv: add surface helper variable in radv_GetImageSubresourceLayout
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Tue, 16 May 2017 15:05:02 +0000 (17:05 +0200)]
radv: fewer than 8 RBs are possible
This fixes the subsequent assertion on Bonaire.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Tue, 16 May 2017 14:38:27 +0000 (16:38 +0200)]
ac/surface/gfx6: explicitly support S8 surfaces
This is needed by radv for dEQP-VK.renderpass.simple.stencil
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 00:20:48 +0000 (01:20 +0100)]
ac/nir: set workgroup size attribute to correct value.
This ports:
55445ff1891724c78e6573d2f8c721e14c0449fc from radeonsi
radeonsi: tell LLVM not to remove s_barrier instructions
LLVM 5.0 removes s_barrier instructions if the max-work-group-size
attribute is not set. What a surprise.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 00:20:10 +0000 (01:20 +0100)]
ac: add new helper function to add a integer target dependent function attr.
This is needed to add the max workgroup size attribute.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 3 Nov 2016 04:16:43 +0000 (04:16 +0000)]
radv: add external memory support.
This adds support for exporting 2D images, to an
opaque fd.
This implements the:
VK_KHX_external_memory_capabilities
VK_KHX_external_memory
VK_KHX_external_memory_fd
extensions.
These are used by SteamVR, we should work with anv
to decide if we should ship these under an env
var or something.
v2 (Bas): - Don't expose the semaphore ext without implementing it.
- Only export the capabilities ext as instance ext.
- Implement radv_GetPhysicalDeviceExternalBufferPropertiesKHX.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Bas Nieuwenhuizen [Tue, 23 May 2017 07:22:09 +0000 (09:22 +0200)]
radv: Add VkPhysicalDeviceIDProperties support.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 22 May 2017 21:50:13 +0000 (23:50 +0200)]
radv: Add support for external queue family.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 14 Mar 2017 23:40:17 +0000 (23:40 +0000)]
radv/formats: reverse how the image format properties KHR2 is handled
This just aligns with how anv does it.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Fri, 2 Jun 2017 22:01:36 +0000 (00:01 +0200)]
radv: Dirty all descriptors sets when changing the pipeline.
Sets could have been ignored during previous descriptor set flush
due to the shader not using them and therefore no SGPR being assigned.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes:
ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
Bas Nieuwenhuizen [Fri, 2 Jun 2017 21:51:50 +0000 (23:51 +0200)]
radv: Set both compute and graphics SGPRS on descriptor set flush.
We clear the descriptors_dirty array afterwards, so the SGPRs for
the other pipeline don't get updated on the flush for that other
draw/dispatch, so we have to make sure we do it immediately.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes:
ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
Chris Wilson [Thu, 6 Oct 2016 20:07:18 +0000 (21:07 +0100)]
i965: Order write of query availablity with earlier writes
Currently we signal the availabilty of the query result using an
unordered pipe-control write. As it is unordered, it may be executed
before the write of the query result itself - and so an observer may
read the query result too early. Fix this by requesting that the write
of the availablity flag is ordered after earlier pipe control writes.
Testcase: piglit/arb_query_buffer_object-qbo/*async*
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Lyude [Wed, 24 May 2017 19:42:41 +0000 (15:42 -0400)]
nvc0: Add support for ARB_post_depth_coverage
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lyude [Wed, 24 May 2017 19:42:40 +0000 (15:42 -0400)]
st/mesa: Add support for ARB_post_depth_coverage
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lyude [Wed, 24 May 2017 19:42:39 +0000 (15:42 -0400)]
gallium: Add a cap to check if the driver supports ARB_post_depth_coverage
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lyude [Wed, 24 May 2017 19:42:38 +0000 (15:42 -0400)]
gallium: Add TGSI shader token for ARB_post_depth_coverage
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lyude [Sat, 3 Jun 2017 00:45:36 +0000 (20:45 -0400)]
nvc0: disable BGRA8 images on Fermi
BGRA8 image stores on Fermi don't work, which results in breaking
PBO downloads, such that they always return 0x0. Discovered this
through a glamor bug, and confirmed it does indeed break a good number
of piglit tests such as spec/arb_pixel_buffer_object/pbo-read-argb8888
Fixes:
8e7893eb53213 ("nvc0: add support for BGRA8 images")
Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Anuj Phogat [Thu, 1 Jun 2017 23:36:39 +0000 (16:36 -0700)]
i965: Simplify l3 way size computations
By making use of l3_banks field in gen_device_info struct
l3_way_size for gen7+ = 2 * l3_banks.
V2: Keep the get_l3_way_size() function.
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Anuj Phogat [Thu, 1 Jun 2017 16:28:04 +0000 (09:28 -0700)]
i965: Add and initialize l3_banks field for gen7+
This new field helps simplify l3 way size computations
in next patch.
V2: Initialize the l3_banks to 0 in macros.
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Chad Versace [Sat, 27 May 2017 01:48:28 +0000 (18:48 -0700)]
i965: Replace 0 with ISL_FORMAT_UNSUPPORTED in format table (v2)
When given an *unsupported* mesa_format,
brw_isl_format_for_mesa_format() returned 0, a *valid* isl_format,
ISL_FORMAT_R32G32B32A32_FLOAT. The problem is that
brw_isl_format_for_mesa_format's inner table used 0 instead of
ISL_FORMAT_UNSUPPORTED to indicate unsupported mesa formats.
Some callers of brw_isl_format_for_mesa_format() were aware of this
weirdness, and worked around it. This patch removes those workarounds.
v2: Ensure that all array elements are initialized to
ISL_FORMAT_UNSUPPORTED, even when new formats are added to enum
mesa_format, by using an designated range initializer.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Gurchetan Singh [Tue, 23 May 2017 00:34:32 +0000 (17:34 -0700)]
st/dri: Use fence extension in drisw.c
This is desirable for synchronization in virtual machines.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Gurchetan Singh [Tue, 23 May 2017 00:33:22 +0000 (17:33 -0700)]
st/dri: move fence implemention into separate file
Since the fence implementation is not dri2.c specific, put
it in a separate file. This way SW implementations can use this
extension too.
v2: Don't depend on dri2.c for extensions (Emil)
v3: Make this patch only move extension into a separate file (Chad).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 1 Jun 2017 20:19:15 +0000 (14:19 -0600)]
mesa: document range of SampleCoverageValue, MinSampleShadingValue
Trivial.
Brian Paul [Mon, 22 May 2017 17:46:27 +0000 (11:46 -0600)]
xlib: fix glXGetCurrentDisplay() failure
glXGetCurrentDisplay() has been broken for years and nobody noticed until
recently. This change adds a new XMesaGetCurrentDisplay() that the GLX
emulation API can call, just as we did for glXGetCurrentContext().
Tested by hacking glxgears to call glXGetCurrentContext() before and
after glXMakeCurrent() to verify the return value is NULL beforehand and
the same as the opened display afterward.
Also tested by Tom Hudson with his tests programs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100988
Cc: mesa-stable@lists.freedesktop.org
Tested-by: Tom Hudson <tom.hudson.phd@gmail.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Thu, 1 Jun 2017 04:40:10 +0000 (05:40 +0100)]
radv: realign cp dma code with radeonsi
This reworks this code to be like radeonsi, which will make it
easier to add GFX9 support to it in the future.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 1 Jun 2017 04:32:25 +0000 (05:32 +0100)]
radv: bump some base addresses to 64-bits.
For GFX9 these will be needed to be 64-bit, so bump them early,
to avoid it causing any wierdness later.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 1 Jun 2017 04:24:34 +0000 (05:24 +0100)]
radv: factor out eop event writing code. (v2)
In prep for GFX9 refactor some of the eop event writing code
out.
This changes behaviour, but aligns with what radeonsi does,
it does double emits on CIK/VI, whereas previously it only
did this on CIK.
v2: bump the size checks.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>