Tom Stellard [Mon, 26 Jul 2021 23:49:30 +0000 (23:49 +0000)]
libclang.so: Fix version script to work with gold
The changes made in
0cf37a3b0617457daaed3224373ffa07724f8482 are not
compatible with gold, which does not seem to support a symbol version
with the name local.
Albion Fung [Mon, 26 Jul 2021 23:44:19 +0000 (18:44 -0500)]
[PowerPC] Changed sema checking range for tdw td builtin
To match xlc behaviour and definition in the PowerPC ISA3.1,
it is a better idea to have ibm-clang produce an error when a
0 is passed to the builtin, which will match xlc's behaviour.
This patch changes the accepted range from 0 to 31 to 1 to 31.
Differential revision: https://reviews.llvm.org/D106817
Philip Reames [Mon, 26 Jul 2021 23:39:11 +0000 (16:39 -0700)]
[SCEV] Add a comment about invariant in howManyLessThans
Tom Stellard [Mon, 26 Jul 2021 23:36:32 +0000 (16:36 -0700)]
libclang.so: Make SONAME independent from LLVM version
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D105527
Jon Roelofs [Wed, 21 Jul 2021 20:04:06 +0000 (13:04 -0700)]
[AArch64][GlobalISel] Legalize ctpop s128
Differential revision: https://reviews.llvm.org/D106494
Leonard Chan [Thu, 8 Jul 2021 22:25:32 +0000 (15:25 -0700)]
[compiler-rt][hwasan][fuchsia] Implement TagMemoryAligned for fuchsia
This will just be a call into __sanitizer_fill_shadow defined in the fuchsia source tree. This depends on D105663.
Differential Revision: https://reviews.llvm.org/D105664
Masoud Ataei [Mon, 26 Jul 2021 23:21:38 +0000 (23:21 +0000)]
[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX
Before MASSV only supported P8 and P9 on AIX ans Linux . This patch proposes
MASSV to add support of P7 and P10 only on AIX too.
Differential: https://reviews.llvm.org/D106678
Reid Kleckner [Mon, 26 Jul 2021 23:06:17 +0000 (16:06 -0700)]
[DebugInfo] Use per-enumerator signedness for DIEnumerator
Allegedly the DWARF backend ignores this field of DIEnumerator, but we
set it nonetheless in case we decide to use it in the future.
Alternatively, we could remove it, but it is simpler to pass down the
signed bit as it is in the AST for now.
Implemented to address comments on D106585
Mehdi Amini [Fri, 16 Jul 2021 03:32:59 +0000 (03:32 +0000)]
Build libSupport with -Werror=global-constructors (NFC)
Ensure that libSupport does not carry any static global initializer.
libSupport can be embedded in use cases where we don't want to load all
cl::opt unless we want to parse the command line.
ManagedStatic can be used to enable lazy-initialization of globals.
The -Werror=global-constructors is only added on platform that have
support for the flag and for which std::mutex does not have a global
destructor. This is ensured by having CMake trying to compile a file
with a global mutex before adding the flag to libSupport.
Leonard Chan [Thu, 8 Jul 2021 22:44:53 +0000 (15:44 -0700)]
[compiler-rt][hwasan][fuchsia] Implement InitializeOsSupport
This is empty for now, but we will add a check that TBI is enabled once the
tagged pointer ABI for zircon is finalized. This depends on D105667.
Differential Revision: https://reviews.llvm.org/D105668
Reid Kleckner [Mon, 26 Jul 2021 22:47:54 +0000 (15:47 -0700)]
Disable the new enum i128 test under ASan, it uncovers an existing leak
See llvm.org/pr51221
Michał Górny [Mon, 26 Jul 2021 21:59:57 +0000 (23:59 +0200)]
[lldb] [gdb-remote client] Avoid zero padding PID/TID in H packet
Change SetCurrentThread*() logic not to include the zero padding
in PID/TID that was a side effect of
02ef0f5ab483. This should fix
problems caused by sending 64-bit integers to 32-bit servers. Reported
by Ted Woodward.
Differential Revision: https://reviews.llvm.org/D106832
Leonard Chan [Fri, 9 Jul 2021 22:17:35 +0000 (15:17 -0700)]
[compiler-rt][hwasan][fuchsia] Define shadow bound globals
These are required by MemIsShadow for checking if an address actually is shadow memory.
Differential Revision: https://reviews.llvm.org/D105745
Rahul Joshi [Mon, 26 Jul 2021 16:39:25 +0000 (09:39 -0700)]
[MLIR][SCF][NFC] Fix typo in documentation of scf.while
- `scf.yield` in the "after" region supplies new arguments to the "before" region.
Differential Revision: https://reviews.llvm.org/D106806
Arthur O'Dwyer [Mon, 26 Jul 2021 22:23:00 +0000 (18:23 -0400)]
[libc++] Fix spacing in <vector>. NFCI.
Thanks to gAlfonso-bit for the patch!
Differential Revision: https://reviews.llvm.org/D106691
Amara Emerson [Mon, 26 Jul 2021 18:46:24 +0000 (11:46 -0700)]
[AArch64][GlobalISel] Add identity combines to post-legal combiner.
We see some shifts of zero emitted during legalization.
Differential Revision: https://reviews.llvm.org/D106816
Fangrui Song [Mon, 26 Jul 2021 22:09:15 +0000 (15:09 -0700)]
[llvm-objcopy] Fix section group flag read/write when operating on a cross-endian object file
Peter Steinfeld [Mon, 26 Jul 2021 21:28:36 +0000 (14:28 -0700)]
[flang] Disallow BOZ literal constants as arguments of implicit interfaces
Since BOZ literal arguments are typeless, we cannot know how to pass them as
actual arguments to procedures with implicit interfaces. This change avoids
the problem by emitting an error message in such situations.
This change stemmed from the following issue --
https://github.com/flang-compiler/f18-llvm-project/issues/794
Differential Revision: https://reviews.llvm.org/D106831
Amara Emerson [Sun, 25 Jul 2021 21:42:38 +0000 (14:42 -0700)]
[GlobalISel] Add a constant folding combine.
Use it AArch64 post-legal combiner. These don't always get folded because when
the instructions are created the constants are obscured by artifacts.
Differential Revision: https://reviews.llvm.org/D106776
Heejin Ahn [Mon, 26 Jul 2021 01:00:52 +0000 (18:00 -0700)]
[WebAssembly] Remove dominator dependency in WasmEHPrepare (NFC)
Dominator trees were previously used for an optimization related to
`wasm.lsda` but the optimization was removed in D97309. Currently
dominators are not doing anything in this pass. Also removes some
`include` lines without which it compiles.
Reviewed By: tlively
Differential Revision: https://reviews.llvm.org/D106811
Joseph Huber [Mon, 26 Jul 2021 15:32:26 +0000 (11:32 -0400)]
[OpenMP] Always inline the OpenMP outlined function
This patch adds the always inline attribute to the outlined functions generated
by OpenMP regions. Because there is only a single instance of this function and
it always has internal linkage it is safe to inline in every instance it is
created. This could potentially lead to performance degredation due to
inflated register counts in the parallel region.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D106799
Omar Emara [Mon, 26 Jul 2021 21:21:57 +0000 (14:21 -0700)]
[LLDB][GUI] Add Arch Field
This patch adds an Arch field that inputs and validates an arch spec.
Differential Revision: https://reviews.llvm.org/D106564
Omar Emara [Mon, 26 Jul 2021 18:19:35 +0000 (11:19 -0700)]
[LLDB][GUI] Expand selected thread tree item by default
This patch expands the tree item that corresponds to the selected thread
by default in the Threads window. Additionally, the tree root item is
always expanded, which is the process in the Threads window.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D100243
Heejin Ahn [Sat, 17 Jul 2021 06:37:09 +0000 (23:37 -0700)]
[WebAssembly] Make Emscripten EH work with Emscripten SjLj
When Emscripten EH mixes with Emscripten SjLj, we are not currently
handling some of them correctly. There are three cases:
1. The current function calls `setjmp` and there is an `invoke` to a
function that can either throw or longjmp. In this case, we have to
check both for exception and longjmp. We are currently handling this
case correctly:
https://github.com/llvm/llvm-project/blob/
0c0eb76782d5224b8d81a5afbb9a152bcf7c94c7/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp#L1058-L1090
When inserting routines for functions that can longjmp, which we do
only for setjmp-calling functions, we check if the function was
previously an `invoke` and handle it correctly.
2. The current function does NOT call `setjmp` and there is an `invoke`
to a function that can either throw or longjmp. Because there is no
`setjmp` call, we haven't been doing any check for functions that can
longjmp. But in that case, for `invoke`, we only check for an
exception and if it is not an exception we reset `__THREW__` to 0,
which can silently swallow the longjmp:
https://github.com/llvm/llvm-project/blob/
0c0eb76782d5224b8d81a5afbb9a152bcf7c94c7/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp#L70-L80
This CL fixes this.
3. The current function calls `setjmp` and there is no `invoke`. Because
it is not an `invoke`, we haven't been doing any check for functions
that can throw, and only insert longjmp-checking routines for
functions that can longjmp. But in that case, if a longjmpable
function throws, we only check for a longjmp so if it is not a
longjmp we reset `__THREW__` to 0, which can silently swallow the
exception:
https://github.com/llvm/llvm-project/blob/
0c0eb76782d5224b8d81a5afbb9a152bcf7c94c7/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp#L156-L169
This CL fixes this.
To do that, this moves around some code, so we register necessary
functions for both EH and SjLj and precompute some data (the set of
functions that contains `setjmp`) before doing actual EH or SjLj
transformation.
This CL makes 2nd and 3rd tests in
https://github.com/emscripten-core/emscripten/pull/14732 work.
Reviewed By: dschuff
Differential Revision: https://reviews.llvm.org/D106525
Arthur O'Dwyer [Sat, 24 Jul 2021 02:05:31 +0000 (22:05 -0400)]
[libc++] Fix signed overflow inside ranges::advance.
See LWG reflector thread of 2021-07-23 titled
'Question on ranges::advance and "past-the-sentinel iterators"'.
Test case heavily based on one graciously provided by Casey Carter.
Differential Revision: https://reviews.llvm.org/D106735
Arthur O'Dwyer [Sat, 24 Jul 2021 01:34:53 +0000 (21:34 -0400)]
[libc++] Remove "pass by const value" in <random>. NFCI.
Louis Dionne [Mon, 26 Jul 2021 20:36:43 +0000 (16:36 -0400)]
[libc++abi/unwind] NFC: Normalize how we set target properties
This is a NFC commit to normalize how we set target properties on the
various runtime targets. A follow-up patch is going to add new properties,
and I wanted that follow-up patch to be cleaner.
Joseph Huber [Mon, 26 Jul 2021 14:25:40 +0000 (10:25 -0400)]
[OpenMP] Add a driver flag to enable the new device runtime library
This patch adds a driver flag `-fopenmp-target-new-runtime` to optionally enable the new device runtime
bitcode library. This allows users to enable the new experimental runtime
before it becomes the default in the future.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D106793
Michael Kruse [Mon, 26 Jul 2021 20:02:08 +0000 (15:02 -0500)]
[flang][msvc] Fix external-io unittest.
Fix the external-io unittest under Windows.
In particular, fixes the following issues:
1. When creating a temporary file, open it with read+write permissions
using the _O_RDWR flag. _S_IREAD and _S_IWRITE are for the file
permissions of the created file.
2. _chsize returns 0 on success (just like ftruncate).
3. To set a std::optional, use its assign-operator overload instead of
getting a reference to its value and overwrite that. The latter is
invalid if the std::optional has no value, and is caught by
msvc's debug STL.
The non-GTest unittest is currently not executed under Windows because
of the added .exe extension to the output file: external-io.text.exe.
llvm-lit skips the file because .exe is not in the lists of test
suffixes (.test is). D105315 is going to change that by converting it
to a GTest-test.
Reviewed By: awarzynski
Differential Revision: https://reviews.llvm.org/D106726
Roman Lebedev [Mon, 26 Jul 2021 20:28:33 +0000 (23:28 +0300)]
[SimplifyCFG] SwitchToLookupTable(): don't increase ret count
The very next SimplifyCFG pass invocation will tail-merge these two ret's
anyways, there is not much point in creating more work for ourselves.
Roman Lebedev [Mon, 26 Jul 2021 20:14:06 +0000 (23:14 +0300)]
[SimplifyCFG] Drop support for simplifying cond branch to two (different) ret's
Nowadays, simplifycfg pass already tail-merges all the ret blocks together
before doing anything, and it should not increase the count of ret's,
so this is dead code.
Roman Lebedev [Mon, 26 Jul 2021 20:08:36 +0000 (23:08 +0300)]
[SimplifyCFG] Drop support for duplicating ret's into uncond predecessors
This functionality existed only under a default-off flag,
and simplifycfg nowadays prefers to not increase the count of ret's.
Matheus Izvekov [Tue, 13 Jul 2021 23:55:34 +0000 (01:55 +0200)]
[clang] P2266 implicit moves STL workaround
This patch replaces the workaround for simpler implicit moves
implemented in D105518.
The Microsoft STL currently has some issues with P2266.
Where before, with -fms-compatibility, we would disable simpler
implicit moves globally, with this change, we disable it only
when the returned expression is in a context contained by
std namespace and is located within a system header.
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Reviewed By: aaron.ballman, mibintc
Differential Revision: https://reviews.llvm.org/D105951
Matheus Izvekov [Thu, 1 Jul 2021 22:26:17 +0000 (00:26 +0200)]
[CodeView] Saturate values bigger than supported by APInt.
This fixes an assert firing when compiling code which involves 128 bit
integrals.
This would trigger runtime checks similar to this:
```
Assertion failed: getMinSignedBits() <= 64 && "Too many bits for int64_t", file llvm/include/llvm/ADT/APInt.h, line 1646
```
To get around this, we just saturate those big values.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D105320
Joseph Huber [Mon, 26 Jul 2021 20:01:41 +0000 (16:01 -0400)]
[OpenMP][NFC] Fix a few typos in OpenMP documentation
Summary:
Fixes some typos in the OpenMP documentation.
David Green [Mon, 26 Jul 2021 19:56:22 +0000 (20:56 +0100)]
[ARM] Fixup vst4 test. NFC
Lei Huang [Fri, 23 Jul 2021 14:27:16 +0000 (09:27 -0500)]
[PowerPC]Add addex instruction definition and MC tests
Add td definitions and asm/disasm tests for the addex instruction introduced in
ISA 3.0.
Reviewed By: nemanjai, amyk, NeHuang
Differential Revision: https://reviews.llvm.org/D106666
Sander de Smalen [Mon, 26 Jul 2021 16:12:51 +0000 (17:12 +0100)]
[LV] Don't let ForceTargetInstructionCost override Invalid cost.
Invalid costs can be used to avoid vectorization with a given VF, which is
used for scalable vectors to avoid things that the code-generator cannot
handle. If we override the cost using the -force-target-instruction-cost
option of the LV, we would override this mechanism, rendering the flag useless.
This change ensures the cost is only overriden when the original cost that
was calculated is valid. That allows the flag to be used in combination
with the -scalable-vectorization option.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D106677
Sander de Smalen [Mon, 26 Jul 2021 19:17:22 +0000 (20:17 +0100)]
[AArch64] NFC: Make some AArch64-SVE LoopVectorize tests generic.
This change moves most of `sve-inductions.ll` to non-AArch64 specific
LV tests using the `-target-supports-scalable-vectors` flag, because they're
not explicitly AArch64-specific. One test builds on AArch64-specific
knowledge regarding masked loads/stores, and remains in sve-inductions.ll.
Alex Langford [Wed, 21 Jul 2021 20:57:49 +0000 (13:57 -0700)]
[lldb][NFC] Delete unused and commented out DWARF constants
I cannot find any users of these anywhere and they have been commented out
for years.
Reid Kleckner [Mon, 26 Jul 2021 19:20:48 +0000 (12:20 -0700)]
[SimplifyCFG] Remove stale comment after
d7378259aa, NFC
Reid Kleckner [Thu, 22 Jul 2021 19:38:57 +0000 (12:38 -0700)]
Fix clang debug info irgen of i128 enums
DIEnumerator stores an APInt as of April 2020, so now we don't need to
truncate the enumerator value to 64 bits. Fixes assertions during IRGen.
Split from D105320, thanks to Matheus Izvekov for the test case and
report.
Differential Revision: https://reviews.llvm.org/D106585
Lei Huang [Thu, 22 Jul 2021 21:32:08 +0000 (16:32 -0500)]
[PowerPC] Add implicit-def RM to instructions mtfsb[01]
This is a followup patch for D105930 to add implicit-def of RM for
mtfsb[01] instructions as per review comments.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D106603
Joseph Huber [Mon, 26 Jul 2021 18:57:38 +0000 (14:57 -0400)]
[OpenMP][NFC] Remove unncessary capture in RAII struct
Summary:
There was an unnecessary variable assigned to the information cache when we
only need it in the constructor to extract the function declaration.
Louis Dionne [Fri, 23 Jul 2021 19:26:23 +0000 (15:26 -0400)]
[libc++] Implement the output_iterator and output_range concepts
Differential Revision: https://reviews.llvm.org/D106704
Louis Dionne [Mon, 26 Jul 2021 15:27:53 +0000 (11:27 -0400)]
[libc++] Set the target triple by default in the standalone build
Even though the standalone build is deprecated, some people are still
relying on it (including libc++ itself for some configurations). Setting
the target triple will ensure that the build and the test suite behaves
consistently in the standalone and normal builds.
Differential Revision: https://reviews.llvm.org/D106800
Eli Friedman [Mon, 26 Jul 2021 18:59:40 +0000 (11:59 -0700)]
Fix clang regression test after
5c486ce0
Michael Liao [Sun, 18 Jul 2021 17:45:52 +0000 (13:45 -0400)]
[amdgpu] Add 64-bit PC support when expanding unconditional branches.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D106445
Craig Topper [Mon, 26 Jul 2021 18:46:31 +0000 (11:46 -0700)]
[TypePromotion] Remove redundant if. NFC
The same condition was checked in the previous if. Maybe this was
a bad merge resolution?
Raul Tambre [Wed, 21 Jul 2021 17:38:24 +0000 (20:38 +0300)]
[compiler-rt][CMake][arm64] Use a custom target for symlinking LSE sources
On Apple platforms the builtins may be built for both arm64 and arm64e.
With Makefile generators separate targets are built using Make sub-invocations.
This causes a race when creating the symlink which may sometimes fail.
Work around this by using a custom target that the builtin targets depend on.
This causes any sub-invocations to depend on the symlinks having been created before.
Mailing list thread: https://lists.llvm.org/pipermail/llvm-dev/2021-July/151822.html
Reviewed By: thakis, steven_wu
Differential Revision: https://reviews.llvm.org/D106305
Nemanja Ivanovic [Mon, 26 Jul 2021 17:35:19 +0000 (12:35 -0500)]
[PowerPC] Implement partial vector ld/st builtins for XL compatibility
XL provides functions __vec_ldrmb/__vec_strmb for loading/storing a
sequence of 1 to 16 bytes in big endian order, right justified in the
vector register (regardless of target endianness).
This is equivalent to vec_xl_len_r/vec_xst_len_r which are only
available on Power9.
This patch simply uses the Power9 functions when compiled for Power9,
but provides a more general implementation for Power8.
Differential revision: https://reviews.llvm.org/D106757
Derek Schuff [Fri, 23 Jul 2021 23:57:37 +0000 (16:57 -0700)]
[lld][WebAssembly] Do not remove name section with --strip-debug
Leave the name section in the output when using the --strip-debug
flag. This treats it more like ELF symbol tables, as the name
section has similar uses at runtime (e.g. wasm engines understand
it and it can be used for symbolization at runtime).
Fixes https://github.com/emscripten-core/emscripten/issues/14623
Differential Revision: https://reviews.llvm.org/D106728
Kevin P. Neal [Mon, 26 Jul 2021 17:57:12 +0000 (13:57 -0400)]
[FPEnv][InstSimplify] Enable more folds for constrained fadd
Precommit tests, try 2. My tree is up-to-date as of this morning so this
should go better than my first try.
Omar Emara [Mon, 26 Jul 2021 18:04:21 +0000 (11:04 -0700)]
[LLDB][GUI] Resolve paths in file/directory fields
This patch resolves the paths in the file/directory fields before
performing checks. Those checks are applied on the file system if
m_need_to_exist is true, so remote files can set this to false to avoid
performing host-side file system checks. Additionally, methods to get
a resolved and a direct file specs were added to be used by client code.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D106553
Amara Emerson [Sun, 25 Jul 2021 14:32:44 +0000 (07:32 -0700)]
[AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT.
These are generated as a byproduce of legalization.
Differential Revision: https://reviews.llvm.org/D106768
Eli Friedman [Mon, 26 Jul 2021 17:51:00 +0000 (10:51 -0700)]
[LLVM IR] Allow volatile stores to trap.
Proposed alternative to D105338.
This is ugly, but short-term I think it's the best way forward: first,
let's formalize the hacks into a coherent model. Then we can consider
extensions of that model (we could have different flavors of volatile
with different rules).
Differential Revision: https://reviews.llvm.org/D106309
Amara Emerson [Sun, 25 Jul 2021 07:47:03 +0000 (00:47 -0700)]
[AArch64][GlobalISel] Enable some select combines after legalization.
The legalizer generates selects for some operations, which can have constant
condition values, resulting in lots of dead code if it's not folded away.
Differential Revision: https://reviews.llvm.org/D106762
Amara Emerson [Sun, 25 Jul 2021 06:44:29 +0000 (23:44 -0700)]
[GlobalISel] Add combine for merge(unmerge) and use AArch64 postlegal-combiner.
Differential Revision: https://reviews.llvm.org/D106761
Michael Jones [Fri, 23 Jul 2021 22:15:03 +0000 (22:15 +0000)]
[libc] add scudo wrappers to llvm libc
The previous patch included the implementations for the scudo allocator,
but not the wrappers. This change fixes that.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D106718
Heejin Ahn [Thu, 22 Jul 2021 05:29:31 +0000 (22:29 -0700)]
[WebAssembly] Improve pseudocode in LowerEmscriptenEHSjLj
Both `__THREW__` and `__threwValue` are global variables, and we have
been distinguishing the global variable `__THREW__` and the loaded value
`%__THREW__.val` in comments but not doing it for `__threwValue`. Made
the pseudocode comments consistent for both variables.
Reviewed By: dschuff
Differential Revision: https://reviews.llvm.org/D106524
Rob Suderman [Thu, 22 Jul 2021 22:12:43 +0000 (15:12 -0700)]
[mlir][tosa] Disable tosa shape verification between operands/results
Tosa shape verification prevent shape propagation when coming from a dialect
of known shape. Relax this constraint to allow ingestion / shape propagation
from these other dialects.
Differential Revision: https://reviews.llvm.org/D106610
Fangrui Song [Mon, 26 Jul 2021 17:00:05 +0000 (10:00 -0700)]
[test] Fix PayloadString: in lldb tests
Simon Pilgrim [Mon, 26 Jul 2021 16:57:09 +0000 (17:57 +0100)]
[X86][AVX] Add PR50053 test case
Florian Hahn [Mon, 26 Jul 2021 16:38:10 +0000 (17:38 +0100)]
[LAA] Remove RuntimeCheckingPtrGroup::RtCheck member (NFC).
This patch removes RtCheck from RuntimeCheckingPtrGroup to make it
possible to construct RuntimeCheckingPtrGroup objects without a
RuntimePointerChecking object. This should make it easier to
re-use the code to generate runtime checks, e.g. in D102834.
RtCheck was only used to access the pointer info for a given index.
Instead, the start and end expressions can be passed directly.
For code-gen, we also need to know the address space to use. This can
also be explicitly passed at construction.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D105481
Stephen Tozer [Mon, 26 Jul 2021 08:59:20 +0000 (09:59 +0100)]
[DebugInfo] Correctly update debug users of SSA values in tail duplication
During tail duplication, SSA values may be updated and have their uses
replaced with a virtual register, and any debug instructions that use
that value are deleted. This patch fixes the implementation of the debug
instruction deletion to work correctly for debug instructions that use
the SSA value multiple times, by batching deletions so that we don't
attempt to delete the same instruction twice.
Differential Revision: https://reviews.llvm.org/D106557
Qiu Chaofan [Mon, 26 Jul 2021 16:20:56 +0000 (00:20 +0800)]
[PowerPC] Change altivec indexed load/store builtins argument type
This patch changes the index argument of lvxl?/lve[bhw]x and
stvxl?/stve[bhw]x builtins from int to long. Because on 64-bit
subtargets, an extra extsw will always been generated, which is
incorrect.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D106530
Louis Dionne [Fri, 23 Jul 2021 20:46:31 +0000 (16:46 -0400)]
[libc++] Add range_size_t
Differential Revision: https://reviews.llvm.org/D106708
Simon Pilgrim [Mon, 26 Jul 2021 16:15:15 +0000 (17:15 +0100)]
[Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation
The getOrderedReductionCost implementation introduced in D105432 calls the CRTP base version getArithmeticInstrCost instead of the redirecting to the target version.
Differential Revision: https://reviews.llvm.org/D106795
Sander de Smalen [Mon, 26 Jul 2021 15:04:25 +0000 (16:04 +0100)]
[LV] Remove assert that VF cannot be scalable in setCostBasedWideningDecision.
Scalarization for scalable vectors is not (yet) supported, so the
LV discards a VF when scalarization is chosen as the widening
decision. It should therefore not assert that the VF is not scalable
when it computes the decision to scalarize.
The code can get here when both the interleave-cost, gather/scatter cost
and scalarization-cost are all illegal. This may e.g. happen for SVE
when the VF=1, to avoid generating `<vscale x 1 x eltty>` types that
the code-generator cannot yet handle.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D106656
Christopher Di Bella [Thu, 22 Jul 2021 20:30:43 +0000 (20:30 +0000)]
[clang][pp] adds '#pragma include_instead'
`#pragma clang include_instead(<header>)` is a pragma that can be used
by system headers (and only system headers) to indicate to a tool that
the file containing said pragma is an implementation-detail header and
should not be directly included by user code.
The library alternative is very messy code that can be seen in the first
diff of D106124, and we'd rather avoid that with something more
universal.
This patch takes the first step by warning a user when they include a
detail header in their code, and suggests alternative headers that the
user should include instead. Future work will involve adding a fixit to
automate the process, as well as cleaning up modules diagnostics to not
suggest said detail headers. Other tools, such as clangd can also take
advantage of this pragma to add the correct user headers.
Differential Revision: https://reviews.llvm.org/D106394
Nikita Popov [Mon, 26 Jul 2021 16:05:47 +0000 (18:05 +0200)]
[MergeICmps] Collect block instructions once (NFC)
Collect the relevant instructions for a given BCECmpBlock once
on construction, rather than repeating this logic in multiple
places.
Fangrui Song [Mon, 26 Jul 2021 16:05:18 +0000 (09:05 -0700)]
[llvm-objcopy] Drop GRP_COMDAT if the group signature is localized
See [GRP_COMDAT group with STB_LOCAL signature](https://groups.google.com/g/generic-abi/c/2X6mR-s2zoc)
objcopy PR: https://sourceware.org/bugzilla/show_bug.cgi?id=27931
GRP_COMDAT deduplication is purely based on the signature symbol name in
ld.lld/GNU ld/gold. The local/global status is not part of the equation.
If the signature symbol is localized by --localize-hidden or
--keep-global-symbol, the intention is likely to make the group fully
localized. Drop GRP_COMDAT to suppress deduplication.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D106782
Fangrui Song [Mon, 26 Jul 2021 16:04:51 +0000 (09:04 -0700)]
[yaml2obj][MachO] Rename PayloadString to Content
The new name is conciser and matches yaml2obj ELF & DWARF.
Reviewed By: #lld-macho, thakis
Differential Revision: https://reviews.llvm.org/D106759
Nikita Popov [Mon, 26 Jul 2021 15:29:07 +0000 (17:29 +0200)]
[MergeICmps] Try to fix MSVC build failure
Apparently this fails to line up the types -- try to sidestep the
issue entirely by writing the code in a more reasonable way: Walk
over the operands and perform a set lookup, rather than walking
over the set and performing an operand scan.
Kazu Hirata [Mon, 26 Jul 2021 15:29:32 +0000 (08:29 -0700)]
[AsmParser] Remove MDRef (NFC)
The last use was removed on Jan 12, 2015 in commit
ab617d597708fcf3c4b829bf595e9d990ca66c07.
Paul Walker [Thu, 22 Jul 2021 16:16:20 +0000 (17:16 +0100)]
[SVE] Use reg+reg addressing mode for immediate offsets.
For reg+imm SVE addressing mode imm is implictly scaled by VL,
making them impractical for truely immediate offsets. However, if
the offset can be unscaled based on the storage element type we
can use the reg+reg SVE addressing mode and thus either reduce the
number of generate add instructions or replace them with a mov
instruction that can be hoisted from the hot code path.
Differential Revision: https://reviews.llvm.org/D106744
Louis Dionne [Mon, 26 Jul 2021 15:22:34 +0000 (11:22 -0400)]
[libc++][NFC] Change a few instances of > > to >> in C++20 code
Sanjay Patel [Mon, 26 Jul 2021 14:52:43 +0000 (10:52 -0400)]
[SimplifyLibCalls] avoid crash on pointer math
We could try harder to screen out libcalls by
function signature (and that would be a much larger
change than for sprintf alone), but that might make
the transition to type-less pointers more difficult.
https://llvm.org/PR51200
Sanjay Patel [Mon, 26 Jul 2021 14:28:43 +0000 (10:28 -0400)]
[SimplifyLibCalls] reduce code duplication; NFC
Nikita Popov [Mon, 26 Jul 2021 12:40:12 +0000 (14:40 +0200)]
[MergeICmps] Separate out BCECmp and use Optional (NFC)
Separate out the BCECmp part from BCECmpBlock, which just stores
the comparison atoms without the branch instruction. At the same
time switch the code to return Optional<> rather than objects in
invalid state and partially constructed objects.
Sander de Smalen [Mon, 26 Jul 2021 14:22:01 +0000 (15:22 +0100)]
[LV] Don't assume isScalarAfterVectorization if one of the uses needs widening.
This fixes an issue that was found in D105199, where a GEP instruction
is used both as the address of a store, as well as the value of a store.
For the former, the value is scalar after vectorization, but the latter
(as value) requires widening.
Other code in that function seems to prevent similar cases from happening,
but it seems this case was missed.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D106164
Bradley Smith [Thu, 8 Jul 2021 16:12:54 +0000 (16:12 +0000)]
[AArch64][SVE] Break false dependencies for inactive lanes of unary operations
Differential Revision: https://reviews.llvm.org/D105889
Shilei Tian [Mon, 26 Jul 2021 15:00:32 +0000 (11:00 -0400)]
[Clang][OpenMP] Remove the mandatory flush for capture for OpenMP 5.1
In OpenMP 5.1:
> If the `write` or `update` clause is specifieded, the atomic operation is not an atomic conditional update for which the comparison fails, and the effective memory ordering is `release`, `acq_rel`, or `seq_cst`, the strong flush on entry to the atomic operation is also a release flush. If the `read` or `update` clause is specified and the effective memory ordering is `acquire`, `acq_rel`, or `seq_cst` then the strong flush on exit from the atomic operation is also an acquire flush.
In OpenMP 5.0:
> If the `write`, `update`, or **`capture`** clause is specified and the `release`, `acq_rel`, or `seq_cst` clause is specified then the strong flush on entry to the atomic operation is also a release flush. If the `read` or `capture` clause is specified and the `acquire`, `acq_rel`, or `seq_cst` clause is specified then the strong flush on exit from the atomic operation is also an acquire flush.
From my understanding, in OpenMP 5.1, `capture` is removed from the requirement for flush, therefore we don't have to enforce it.
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D100768
Ulrich Weigand [Tue, 20 Jul 2021 16:14:38 +0000 (18:14 +0200)]
[SystemZ] Add support for new cpu architecture - arch14
This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.
This includes:
- Basic support for the new processor and its features.
- Detection of arch14 as host processor.
- Assembler/disassembler support for new instructions.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining __VEC__ == 10304.
Note: No currently available Z system supports the arch14
architecture. Once new systems become available, the
official system name will be added as supported -march name.
Florian Hahn [Mon, 26 Jul 2021 14:21:16 +0000 (15:21 +0100)]
Recommit "[VPlan] Add recipe for first-order rec phis, make splicing explicit."
This reverts the revert commit
b1777b04dc4b1a9fee0e7effa7e177892ab32ef0.
The patch originally got reverted due to a crash:
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2
The underlying issue was that we were not using the stored values from
the modified memory recipes, but the out-of-date values directly from
the IR (accessed via the VPlan). This should be fixed in
d995d6376. A
reduced version of the reproducer has been added in
93664503be6b.
Mark de Wever [Thu, 22 Jul 2021 09:17:53 +0000 (11:17 +0200)]
[libc++][ci] Detect not committed generated files.
The Generated output CI job only tests for modified files. This job
should also fail the generated output contains new files.
It would be possible to test modified and untracked files in one
execution of `git ls-files`. However the diff is stored as an artifact
so the execution of `git diff` would still be required.
Discussion: Would it be better to do `git ls-files -om` and remove the
excution of
`! grep -q '^--- a' ${BUILD_DIR}/generated_output.patch || false` ?
(Obviously then the name `generated_output.untracked` should change to
something like `generated_output.status`)
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D106534
Nikita Popov [Wed, 21 Jul 2021 19:23:38 +0000 (21:23 +0200)]
[IR] Consider non-willreturn as side effect (PR50511)
This adjusts mayHaveSideEffect() to return true for !willReturn()
instructions. Just like other side-effects, non-willreturn calls
(aka "divergence") cannot be removed and cannot be reordered relative
to other side effects. This fixes a number of bugs where
non-willreturn calls are either incorrectly dropped or moved. In
particular, it also fixes the last open problem in
https://bugs.llvm.org/show_bug.cgi?id=50511.
I performed a cursory review of all current mayHaveSideEffect()
uses, which convinced me that these are indeed the desired default
semantics. Places that do not want to consider non-willreturn as a
sideeffect generally do not want mayHaveSideEffect() semantics at
all. I identified two such cases, which are addressed by D106591
and D106742. Finally, there is a use in SCEV for which we don't
really have an appropriate API right now -- what it wants is
basically "would this be considered forward progress". I've just
spelled out the previous semantics there.
Differential Revision: https://reviews.llvm.org/D106749
Benjamin Kramer [Mon, 26 Jul 2021 14:32:22 +0000 (16:32 +0200)]
Simplify away some SmallVector copies. NFCI.
The lifetime of the initializer list is the full expression, so we can
skip storing it in a temporary vector.
Gabor Marton [Tue, 20 Jul 2021 14:46:15 +0000 (16:46 +0200)]
[Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation)
This change is an extension to D103967 where I added dump methods for
(dis)equality classes of the State. There, the (dis)equality classes and their
contents are dumped in an ordered fashion, they are ordered based on their
string representation. This is very useful once we start to use FileCheck to
test the State dump in certain tests.
Differential Revision: https://reviews.llvm.org/D106642
Jeremy Morse [Mon, 26 Jul 2021 14:00:08 +0000 (15:00 +0100)]
[InstrRef][AArch64][1/4] Accept constant physreg variable locations
Late in SelectionDAG we join up instruction numbers with their defining
instructions, if it couldn't be done during the main part of SelectionDAG.
One exception is function arguments, where we have to point a DBG_PHI
instruction at the incoming live register, as they don't have a defining
instruction. This patch adds another exception, for constant physregs, like
aarch64 has.
It may seem wasteful to use two instructions where we could use a single
DBG_VALUE, however the whole point of instruction referencing is to
decouple the identification of values from the specification of where
variable location ranges start.
(Part of my aarch64 work to ease adoption of instruction referencing, as
in the meta comment on D104520)
Differential Revision: https://reviews.llvm.org/D104520
Florian Hahn [Mon, 26 Jul 2021 13:47:00 +0000 (14:47 +0100)]
[LV] Add test to store a first-order rec via interleave group.
This is a reduced version of the reproducer from
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2
Alexey Bataev [Mon, 26 Jul 2021 12:43:53 +0000 (05:43 -0700)]
[SLP]Fix costs calculations.
Need to fix several cost-related problems. The final type may be defined
incorrectly because of to early definition (we may end up with the wider
type), the CommonCost should not be redefined in ExtractElements
cost related calculations and the shuffle of the final insertelements
vectors should be calculated as a cost of single vector permutations
+ costs of two vector permutations for other n-1 incoming vectors.
Differential Revision: https://reviews.llvm.org/D106578
Anastasia Stulova [Mon, 26 Jul 2021 13:59:47 +0000 (14:59 +0100)]
[OpenCL] Change default standard version to CL1.2
Set default version for OpenCL C to 1.2. This means that the
absence of any standard flag will be equivalent to passing
'-cl-std=CL1.2'.
Note that this patch also fixes incorrect version check for
the pointer to pointer kernel arguments diagnostic and
atomic test.
Differential Revision: https://reviews.llvm.org/D106504
gbreynoo [Mon, 26 Jul 2021 13:49:53 +0000 (14:49 +0100)]
[llvm-readobj] Display multiple function names for stack size entries
The current implementation of displaying .stack_size information
presumes that each entry represents a single function but this is not
always the case. For example with the use of ICF multiple functions can
be represented with the same code, meaning that the address found in a
.stack_size entry corresponds to multiple function symbols.
This change allows multiple function names to be displayed when
appropriate.
Differential Revision: https://reviews.llvm.org/D105884
Jay Foad [Wed, 21 Jul 2021 14:53:59 +0000 (15:53 +0100)]
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.
Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.
D106284 did this for SelectionDAG. This is the corresponding fix for
GlobalISel.
Differential Revision: https://reviews.llvm.org/D106451
Jay Foad [Wed, 21 Jul 2021 10:29:04 +0000 (11:29 +0100)]
[AMDGPU] Pre-commit global-isel test case for D106451
This test case shows the scheduler wrongly reordering two buffer
accesses that might alias.
Jay Foad [Mon, 19 Jul 2021 15:29:39 +0000 (16:29 +0100)]
[AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset
Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.
Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.
Differential Revision: https://reviews.llvm.org/D106284
David Green [Mon, 26 Jul 2021 13:26:38 +0000 (14:26 +0100)]
[ARM] Ensure correct regclass in distributing postinc
The register class required for some MVE loads/stores is more
constrained than the register we use when creating postinc. Make sure we
constrain the register class to keep the code correct.
Tim Northover [Mon, 26 Jul 2021 12:53:34 +0000 (13:53 +0100)]
AArch64: support i128 (& larger) returns in GlobalISel
Nikita Popov [Wed, 21 Jul 2021 20:34:28 +0000 (22:34 +0200)]
[SimplifyCFG] Improve store speculation check
isSafeToSpeculateStore() looks for a preceding store to the same
location to make sure that introducing a new store of the same
value is safe. It currently bails on intervening mayHaveSideEffect()
instructions. However, I believe just checking mayWriteToMemory()
is sufficient there -- we just need to make sure that we know which
value was stored, we don't care if we can unwind in the meantime.
While looking into this, I started having some doubts about the
correctness of the transform with regard to thread safety. While
we don't try to hoist non-simple stores, I believe we also need
to make sure that the preceding store is simple as well. Otherwise
we could introduce a spurious non-atomic write after an atomic write
-- under our memory model this would result in a subsequent undef
atomic read, even if the second write stores the same value as the
first.
Example: https://alive2.llvm.org/ce/z/q_3YAL
Differential Revision: https://reviews.llvm.org/D106742