Paulo Zanoni [Wed, 7 Apr 2021 00:15:21 +0000 (17:15 -0700)]
iris: finish converting from drmIoctl to intel_ioctl
Only 3 remaining users. The implementations are exactly the same.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11194>
Caio Marcelo de Oliveira Filho [Thu, 29 Apr 2021 22:12:24 +0000 (15:12 -0700)]
nir/gather_info: Rename per_vertex to is_arrayed
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11252>
Caio Marcelo de Oliveira Filho [Thu, 29 Apr 2021 21:50:06 +0000 (14:50 -0700)]
nir/lower_io: Rename vertex_index to array_index in helpers
The helpers will be reused for per-primitive variables that are also
arrayed, so use a more general name.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11252>
Samuel Pitoiset [Mon, 7 Jun 2021 13:19:59 +0000 (15:19 +0200)]
aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7
GFX6-7 are affected by a hw bug that prevents address clamping to work
correctly when the SGPR offset is used. Use the VGPR offset to fix it.
Fixes various hangs with dEQP-VK.robustness.robustness2.* on Bonaire.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11238>
Tomeu Vizoso [Wed, 9 Jun 2021 05:33:26 +0000 (07:33 +0200)]
ci: Disable windows builds due to runner not being available
Warning from Gitlab:
This job is stuck because you don't have any active runners online or
available with any of these tags assigned to them: windows shell 1809
mesa
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
Alyssa Rosenzweig [Mon, 7 Jun 2021 17:59:26 +0000 (13:59 -0400)]
nir/lower_fragcolor: Avoid redundant load_output
At best, this is an extra instruction for NIR to optimize out. At worst,
depending on pass ordering nir_load_output could sneak into the final
NIR, even on drivers that don't support fbfetch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
Alyssa Rosenzweig [Tue, 8 Jun 2021 23:46:12 +0000 (19:46 -0400)]
ci: Disable the iris APL jobs
Someone's cat is chewing on the Ethernet adaptor.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
Rob Clark [Sun, 18 Apr 2021 16:10:07 +0000 (09:10 -0700)]
freedreno/ir3: Fix use after free
If the tex/sfu ssa src is from a different block than the one currently
being scheduled, we do not have a valid sched-node. So fallback to
previous behavior rather than dereference an invalid ptr.
Fixes:
7821e5a3f8d ("ir3/sched: Don't penalize uses of already-waited tex/SFU")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10306>
Jason Ekstrand [Tue, 8 Jun 2021 14:22:44 +0000 (09:22 -0500)]
anv/blorp: Optimize addresses/relocations when ANV_ALWAYS_SOFTPIN
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 14:25:57 +0000 (09:25 -0500)]
anv: Optimize anv_address_physical when ANV_ALWAYS_SOFTPIN
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 14:15:09 +0000 (09:15 -0500)]
anv: Fast-path surface relocs when we have softpin
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 01:16:07 +0000 (20:16 -0500)]
anv: Make anv_batch_emit_reloc inline and optimize SKL+
This should drop the CPU overhead of processing buffers on SKL+ by
dropping some of the logic contained in anv_reloc_list_add() whenever we
have enough compile-time information to know we have softpin.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Fri, 7 Aug 2020 03:46:12 +0000 (22:46 -0500)]
anv: Add a helper to add a BO to the batch list without a reloc
The relocation list currently serves two purposes. One is for
relocations on older non-softpin platforms. The second is to keep track
of driver-managed BOs which are used by the given command buffer. We
going to need a mechanism to add BOs to the command buffer without doing
a relocation into the batch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 01:02:22 +0000 (20:02 -0500)]
anv: Handle OOM in the pinned path in anv_reloc_list_add
Fixes:
b3c0b1b21880 "anv: Use a bitset for tracking residency"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 00:53:42 +0000 (19:53 -0500)]
anv: Make use_softpin compile-time in genX code
Whenever we have the GFX_VERx10 macro available, we can make use_softpin
a compile-time thing for everything but Broadwell and Cherryview. This
should save us some CPU cycles especially on SKL+.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Fri, 3 Apr 2020 13:17:43 +0000 (08:17 -0500)]
anv: Require softpin on Gen8+
Softpin was added to i915 in
commit
506a8e87d8d2746b9e9d2433503fe237c54e4750
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Dec 8 11:55:07 2015 +0000
drm/i915: Add soft-pinning API for execbuffer
which was included in Linux 4.5. It's been over 5 years so it's
probably reasonable to make it a hard requirement.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Caio Marcelo de Oliveira Filho [Mon, 7 Jun 2021 21:17:12 +0000 (14:17 -0700)]
anv: Support workgroup memory in other shaders
Mesh and Task shaders can use workgroup memory, so generalize its
handling in anv by moving it from anv_pipeline_compile_cs() to
anv_pipeline_lower_nir().
Update Pipeline Statistics accordingly.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11230>
Caio Marcelo de Oliveira Filho [Wed, 5 May 2021 19:24:44 +0000 (12:24 -0700)]
nir: Move workgroup_size and workgroup_variable_size into common shader_info
Move it out the "cs" sub-struct, since these will be used for other
shader stages in the future.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
Caio Marcelo de Oliveira Filho [Wed, 5 May 2021 16:34:46 +0000 (09:34 -0700)]
nir: Move zero_initialize_shared_memory into common shader_info
Move it out the "cs" sub-struct, since the bit will be used for other
shader stages in the future.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
Mike Blumenkrantz [Tue, 8 Jun 2021 15:23:43 +0000 (11:23 -0400)]
zink: more accurately handle shader layer/viewport caps
the spirv extension is required for spirv < 1.5, but the core cap should
be used for spirv >= 1.5
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11244>
Tony Wasserka [Thu, 27 May 2021 11:16:01 +0000 (13:16 +0200)]
aco/ra: Split print_regs by lines of 64 registers
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10517>
Tony Wasserka [Thu, 29 Apr 2021 10:18:24 +0000 (12:18 +0200)]
aco/ra: Clean up print_regs output and support byte-allocated variables
Example output:
00 03 06 09 12 15 18 21 24 27 30 33 36 39 42
sgprs: ·▉█▉███▉▉█··████···········▉████············
00 03 06 09 12 15 18 21 24 27 30 33 36 39 42
vgprs: ▉▉··▉▉▉▉▘▀▉▉▉···▉▘▘▉▉▉▉···▉▉▉▀▀▉············
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10517>
Tony Wasserka [Thu, 29 Apr 2021 16:06:53 +0000 (18:06 +0200)]
aco/ra: Fix off-by-one-error in print_regs
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
3675aefa84e ("aco/ra: Fix build with print_regs enabled")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10517>
Boyuan Zhang [Tue, 8 Jun 2021 00:33:43 +0000 (20:33 -0400)]
frontends/omx: use pipe buffer map instead of texture map
Fixes:
eb74f9776 ("gallium: split transfer_(un)map into buffer_(un)map and texture_(un)map")
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11233>
Leo Liu [Sat, 5 Jun 2021 23:34:40 +0000 (19:34 -0400)]
frontends/va: use the entrypoint from context instead of the hard-coded one
It could fail the case where this is only encode available.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Leo Liu [Sat, 5 Jun 2021 23:31:34 +0000 (19:31 -0400)]
frontends/va: include the profile queries for encoder as well
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Leo Liu [Sat, 5 Jun 2021 23:29:08 +0000 (19:29 -0400)]
frontends/va: use the correct entrypoint to get config attributes
PIPE_VIDEO_ENTRYPOINT_ENCODE should be used in this case.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Leo Liu [Sat, 5 Jun 2021 22:46:58 +0000 (18:46 -0400)]
radeonsi: separate video hw info based on HW engine individually
This removes previous "has_hw_decode" and "uvd_enc_supported" and
makes information more accuate for cases where HW decode, HW encode,
and HW JPEG decode might partially available.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Leo Liu [Sat, 5 Jun 2021 21:03:32 +0000 (17:03 -0400)]
radeonsi: add PIPE_FORMAT_P010 for HEVC Main10 profile to encode param
The format can be queried through the encode entrypoint
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Bas Nieuwenhuizen [Mon, 7 Jun 2021 00:50:09 +0000 (02:50 +0200)]
nir/lower_returns: Deal with single-arg phis after if.
if we have
if ... {
return;
} else {
// block X
}
// block Y
phi(X: ...)
then nir_lower_returns tries to move block Y into the else body,
except nir_cf_extract doesn't move the phi. As the return is removed
in the then-body the phi suddenly has the wrong number of arguments
(and the phi doesn't dominate its uses anymore).
In this case we know that the phi has to be single arg, so we can just
rewrite the users of the phis and drop them.
Hit this in my RT adventures, not sure if this is actually reachable
right now, as single arg phis tend to be kind of exceptional outside
of CSSA and we typically call nir_lower_returns pretty early.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11207>
Hubert Jasudowicz [Tue, 8 Jun 2021 09:09:03 +0000 (11:09 +0200)]
docs/egl: Add missing backticks
Signed-off-by: Hubert Jasudowicz <hubert.jasudowicz@gmail.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11240>
Juan A. Suarez Romero [Mon, 7 Jun 2021 12:19:33 +0000 (14:19 +0200)]
broadcom/ci: Report flakes on IRC
Report flakes in #videocore-ci channel.
v2 (Emma):
- Add glx@glx_arb_sync_control@timing.* as flakes.
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11220>
Juan A. Suarez Romero [Mon, 7 Jun 2021 09:11:42 +0000 (11:11 +0200)]
ci/v3dv: test v3dv in arm64 environment
As most of the development is done in arm64, execute the v3dv related
tests in this environment.
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11220>
Juan A. Suarez Romero [Fri, 4 Jun 2021 17:04:59 +0000 (19:04 +0200)]
ci/broadcom: unset manual jobs
Make some of the jobs for vc4 and v3d to run automatically, in order to
identify more regressions.
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11220>
Samuel Pitoiset [Mon, 7 Jun 2021 05:56:19 +0000 (07:56 +0200)]
ac/debug: fix color printing PKT3 when count in header is too low
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11211>
Rhys Perry [Mon, 3 Feb 2020 15:22:11 +0000 (15:22 +0000)]
aco/tests: add SDWA tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Fri, 14 Aug 2020 15:12:55 +0000 (16:12 +0100)]
aco/tests: add tests for p_extract/p_insert lowering
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Fri, 23 Apr 2021 10:56:18 +0000 (11:56 +0100)]
aco: disallow literals with some instruction formats
Because isVOPn() is true for many VOP3, SDWA and DPP instructions, this
would often not complain.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 7 Oct 2020 13:35:21 +0000 (14:35 +0100)]
aco: make validate_ir() output usable in tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 12 Aug 2020 13:23:56 +0000 (14:23 +0100)]
aco: optimize 32-bit extracts and inserts using SDWA
Still need to use dst_u=preserve field to optimize packs
fossil-db (Sienna Cichlid):
Totals from 15974 (10.66% of 149839) affected shaders:
VGPRs: 1009064 -> 1008968 (-0.01%); split: -0.03%, +0.02%
SpillSGPRs: 7959 -> 7964 (+0.06%)
CodeSize:
101716436 ->
101159568 (-0.55%); split: -0.55%, +0.01%
MaxWaves: 284464 -> 284490 (+0.01%); split: +0.02%, -0.01%
Instrs:
19334216 ->
19224241 (-0.57%); split: -0.57%, +0.00%
Latency:
375465295 ->
375230478 (-0.06%); split: -0.14%, +0.08%
InvThroughput:
79006105 ->
78860705 (-0.18%); split: -0.25%, +0.07%
fossil-db (Polaris):
Totals from 11369 (7.51% of 151365) affected shaders:
SGPRs: 787920 -> 787680 (-0.03%); split: -0.04%, +0.01%
VGPRs: 681056 -> 681040 (-0.00%); split: -0.01%, +0.00%
CodeSize:
68127288 ->
67664120 (-0.68%); split: -0.69%, +0.01%
MaxWaves: 54370 -> 54371 (+0.00%)
Instrs:
13294638 ->
13214109 (-0.61%); split: -0.62%, +0.01%
Latency:
373515759 ->
373214571 (-0.08%); split: -0.11%, +0.03%
InvThroughput:
166529524 ->
166275291 (-0.15%); split: -0.20%, +0.05%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 28 Oct 2020 13:32:55 +0000 (13:32 +0000)]
radv: use byte/word extract/insert instructions
ACO doesn't yet combine extract/insert into instructions, but it seems to
already generate less instructions because NIR optimizes shift+and to
these instructions. Code size is worse in some cases though because we
have to always use a literal when masking.
fossil-db (Sienna Cichlid):
Totals from 14361 (9.58% of 149839) affected shaders:
VGPRs: 850152 -> 850304 (+0.02%); split: -0.02%, +0.04%
SpillSGPRs: 7979 -> 7989 (+0.13%); split: -0.03%, +0.15%
CodeSize:
88031216 ->
88162520 (+0.15%); split: -0.01%, +0.16%
MaxWaves: 269414 -> 269426 (+0.00%)
Instrs:
16695182 ->
16662852 (-0.19%); split: -0.21%, +0.01%
Latency:
375592693 ->
375544364 (-0.01%); split: -0.04%, +0.03%
InvThroughput:
75627700 ->
75607720 (-0.03%); split: -0.07%, +0.04%
fossil-db (Polaris):
Totals from 13816 (9.13% of 151365) affected shaders:
SGPRs: 984896 -> 982512 (-0.24%); split: -0.29%, +0.05%
VGPRs: 809220 -> 809112 (-0.01%); split: -0.02%, +0.01%
SpillSGPRs: 9181 -> 9185 (+0.04%); split: -0.04%, +0.09%
CodeSize:
82017952 ->
82123484 (+0.13%); split: -0.01%, +0.14%
MaxWaves: 65721 -> 65723 (+0.00%)
Instrs:
16008744 ->
15988007 (-0.13%); split: -0.18%, +0.05%
Latency:
439911623 ->
439869622 (-0.01%); split: -0.04%, +0.03%
InvThroughput:
185898770 ->
185841742 (-0.03%); split: -0.08%, +0.05%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 28 Oct 2020 13:32:25 +0000 (13:32 +0000)]
ac/llvm: implement byte/word extract/insert instructions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 12 Aug 2020 13:35:15 +0000 (14:35 +0100)]
aco: use byte/word extract pseudo-instructions
fossil-db (Sienna Cichild):
Totals from 1890 (1.26% of 149839) affected shaders:
CodeSize: 5104196 -> 5104300 (+0.00%); split: -0.00%, +0.01%
Latency:
11572943 ->
11572880 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 4876941 -> 4876982 (+0.00%); split: -0.00%, +0.00%
SClause: 26774 -> 26775 (+0.00%)
Copies: 125778 -> 125813 (+0.03%)
PreSGPRs: 56452 -> 56451 (-0.00%)
fossil-db (Polaris):
Totals from 1884 (1.24% of 151365) affected shaders:
CodeSize: 3849340 -> 3849312 (-0.00%); split: -0.00%, +0.00%
Instrs: 741391 -> 741382 (-0.00%)
Latency:
13533815 ->
13533439 (-0.00%)
InvThroughput:
12058777 ->
12058500 (-0.00%)
Copies: 120890 -> 120891 (+0.00%)
PreSGPRs: 48940 -> 48939 (-0.00%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 12 Aug 2020 13:35:15 +0000 (14:35 +0100)]
aco: implement nir_op_extract/nir_op_insert
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 12 Aug 2020 13:35:15 +0000 (14:35 +0100)]
aco: add p_extract/p_insert
These will let us make the SDWA optimizer much simpler than if we were to
recognize combinations of shift/and/bfe.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Mon, 7 Jun 2021 15:56:45 +0000 (16:56 +0100)]
aco: disallow SDWA for instructions with 64-bit definitions/operands
For example, v_cvt_f64_i32. LLVM doesn't seem to allow this either and it
doesn't seem to work correctly.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 25 Mar 2020 15:38:06 +0000 (15:38 +0000)]
nir, nir/algebraic: add byte/word insertion instructions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Fri, 3 Apr 2020 13:41:38 +0000 (14:41 +0100)]
nir/algebraic: optimize extract of extract
Found in some sottr shaders (originally iand(ishr(a, 16), 0xffff))
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Samuel Pitoiset [Mon, 7 Jun 2021 05:40:54 +0000 (07:40 +0200)]
radv: emit PA_SC_CONSERVATIVE_RASTERIZATION_CNTL only on GFX9+
This context register doesn't exist on older generations.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11210>
Dave Airlie [Tue, 4 May 2021 04:05:10 +0000 (14:05 +1000)]
intel/isl: add blend enable flag to gen4/5
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10655>
Dave Airlie [Sun, 6 Jun 2021 19:28:07 +0000 (05:28 +1000)]
intel/isl: add levels and minimum array element to null fill
gen4/5 needs these to avoid gpu hangs around matching depth/null
surfaces
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10655>
Dave Airlie [Sun, 6 Jun 2021 19:26:05 +0000 (05:26 +1000)]
intel/isl: convert null surface fill to a struct.
Suggested by Jason, pre-convert this to a struct so it can
be expanded for gen4/5 crocus support
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10655>
Dave Airlie [Tue, 8 Jun 2021 00:00:20 +0000 (10:00 +1000)]
intel/isl: decrease isl_format_layouts size by 36k
This drops
-
0000000000011e90 R isl_format_layouts
+
0000000000008f48 R isl_format_layouts
I think that's about 36k.
Thanks to Jason for suggesting PACKED
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11232>
Yiwei Zhang [Thu, 3 Jun 2021 20:46:08 +0000 (20:46 +0000)]
venus: forward the host renderer hardware info
Some game engines rely on the real hardware info to adjust default
graphics quality and other attributes.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11175>
Caio Marcelo de Oliveira Filho [Fri, 4 Jun 2021 19:04:15 +0000 (12:04 -0700)]
nir: Rename WORK_GROUP (and similar) to WORKGROUP
Be consistent with other usages in Vulkan and SPIR-V, and the recently
added workgroup_size field.
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
Caio Marcelo de Oliveira Filho [Thu, 27 May 2021 21:44:54 +0000 (14:44 -0700)]
nir: Rename nir_intrinsic_load_local_group_size to nir_intrinsic_load_workgroup_size
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
Caio Marcelo de Oliveira Filho [Thu, 27 May 2021 21:39:03 +0000 (14:39 -0700)]
compiler: Rename SYSTEM_VALUE_LOCAL_GROUP_SIZE to SYSTEM_VALUE_WORKGROUP_SIZE
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
Caio Marcelo de Oliveira Filho [Thu, 27 May 2021 06:53:32 +0000 (23:53 -0700)]
compiler: Rename local_size to workgroup_size
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
Emma Anholt [Mon, 7 Jun 2021 18:51:21 +0000 (11:51 -0700)]
i915g: Make sure we don't try to texture from the const file.
It's an invalid value for the texture coordinate source, and this becomes
more common if we enable nir-to-tgsi.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11227>
Emma Anholt [Mon, 7 Jun 2021 19:44:50 +0000 (12:44 -0700)]
ci/i915g: Fix incorrect expectation.
I think this was an edit failure on my part when fixing up the
expectations for merge.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11227>
Timur Kristóf [Mon, 31 May 2021 15:46:19 +0000 (17:46 +0200)]
radv: Assert that there is no GS copy shader when the pipeline has NGG.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11092>
Timur Kristóf [Mon, 31 May 2021 15:43:23 +0000 (17:43 +0200)]
radv: Don't generate GS copy shader when the pipeline has NGG.
Previously the code used radv_pipeline_has_ngg but that always
returned false because the pipeline->shaders was all NULL at the
time when the GS copy shader was created.
Fixes:
ca783612e721bc66af545075d76dc578ddbf7666
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11092>
Timur Kristóf [Mon, 31 May 2021 15:42:46 +0000 (17:42 +0200)]
radv: Remove duplicate code for getting GS info.
This was my mistake for forgetting to delete this code.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11092>
Alejandro Piñeiro [Fri, 23 Apr 2021 10:21:29 +0000 (12:21 +0200)]
v3d/simulator: get rid of has_gca wrapper
We can assume that it is always present on 3.3 and below. In fact,
recent updates of the simulator will remove it, so this change would
be needed soon.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11040>
Alejandro Piñeiro [Fri, 23 Apr 2021 10:12:49 +0000 (12:12 +0200)]
v3d/simulator: hw mem is now an v3d_size_t, typedef to uint32_t
It would be really awesome to be able to write this so it would work
with old and new versions of the simulator, but I was not able to do
that.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11040>
Jason Ekstrand [Mon, 7 Jun 2021 17:09:15 +0000 (12:09 -0500)]
ttn: Stop manually managing system_values_read
There's no point in duplicating all the ops here. The caller should run
nir_gather_info if they want system_values_read. Hand-rolling it all in
tgsi_to_nir is just asking for bugs.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11222>
Andres Gomez [Mon, 7 Jun 2021 17:46:39 +0000 (20:46 +0300)]
ci: update some radv trace checksums
After
7d23ea20a02 ("radv: don't allocate DCC predicate if the image doesn't use DCC")
some checksums for the radv driver remained to be updated.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11223>
Rob Clark [Sun, 6 Jun 2021 18:02:26 +0000 (11:02 -0700)]
frontend/dri: Fix fence-fd logic
We can't ask for a fence fd if we don't pass PIPE_FLUSH_FENCE_FD. Also
don't leak fences.
Fixes:
abec42c9a30 ("gallium/dri: implement EGL_KHR_mutable_render_buffer")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11202>
Rob Clark [Sun, 6 Jun 2021 16:27:52 +0000 (09:27 -0700)]
egl+libsync: Add check for valid fence-fd
Debugging fd mix-ups (ie. where, possibly via close()ing the original
fd, etc, you end up with something that is a valid fd but not a valid
*fence* fd) can be difficult. Fortunately we can use the FILE_INFO
ioctl, which will return an error if the fd is not a fence fd.
For android, we instead use the libsync API, which does a similar thing
on modern kernels, but has a fallback path for older android kernels.
Note that the FILE_INFO ioctl has existed upstream since at least prior
to destaging of sync_file.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11202>
Rob Clark [Sun, 6 Jun 2021 15:43:28 +0000 (08:43 -0700)]
egl: zero is a valid fd
We shouldn't be using RETURN_EGL_EVAL() for eglDupNativeFenceFDANDROID()
return, as (while perhaps unlikely) zero is a valid fd. The error case
for EGL_NO_NATIVE_FENCE_FD_ANDROID is already handled in egl_dri2.c
(dri2_dup_native_fence_fd()) so just use RETURN_EGL_SUCCESS() instead.
Also fix ret type.
Fixes:
0201f01dc4e ("egl: add EGL_ANDROID_native_fence_sync")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11202>
Kenneth Graunke [Tue, 11 May 2021 21:56:58 +0000 (14:56 -0700)]
iris: Add a BO_ALLOC_SMEM flag for allocating from system memory
Most allocations will want to be in device local memory (if it exists),
so we default to LMEM in the absence of a flag. However, some buffers
are expected to be read/written from the CPU multiple times, and we may
want to explicitly place those buffers in system memory.
This patch adds the infrastructure for deciding on the allocation,
and sets the flags, but does not actually hook up the flag to do
anything, as the kernel infrastructure for LMEM support hasn't landed.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11169>
Kenneth Graunke [Wed, 2 Jun 2021 22:21:35 +0000 (15:21 -0700)]
iris: Only use SET/GET_TILING when exporting/importing BOs
In the past, we tracked bo->tiling_mode and bo->stride, and used
GEM_{GET,SET}_TILING on all buffers we allocated. This made more sense
in the old days (long before iris even existed) when we used GTT maps to
detile resources. However, that support is now gone, and we never used
it in iris anyway. We don't need to do this in most cases anymore.
We are trying to deprecate these kernel APIs. They have many issues.
One is having a global tiling mode for a buffer when userspace may
want to suballocate multiple resources with different tiling modes
from the same object. Another is...what if processes want to interpret
the data differently, and hot-swap the tiling mode out from under
another process? Another is the fundamental race conditions. There
are many reasons not to use these APIs.
Unfortunately, there is still one case where it's used: when importing
and exporting DMABUFs, we have to communicate the tiling somehow. The
right way to do that is using modifiers, but those didn't always exist,
and aren't always enabled (maybe aren't even commonly enabled). So we
use GET/SET_TILING as a poor-man's IPC mechanism of sorts.
This patch stops calling those APIs in general but continues doing so
for imported/exported objects when we don't have modifiers.
We eliminate iris_bo_alloc_tiled entirely. There is now only one!
One small behavioral change snuck in: iris_memobj_create_from_handle
now aligns the virtual address to 64K rather than 1B when modifiers
aren't present. This should be harmless, and lets us delete a whole
bunch of code.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11169>
Kenneth Graunke [Wed, 2 Jun 2021 23:16:53 +0000 (16:16 -0700)]
iris: Add an alignment parameter to iris_bo_alloc()
This is rarely useful, but after the next patch removes tiling tracking,
this would literally be the only difference between iris_bo_alloc and
iris_bo_alloc_tiled, so we may as well add it.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11169>
Kenneth Graunke [Tue, 11 May 2021 21:21:25 +0000 (14:21 -0700)]
iris: Add a flags argument to iris_bo_alloc()
Based on a patch by Rafael Antognolli.
We already had a flags parameter, but omitted it from the simple alloc
interface because most callers were passing 0. However, we'll want to
use it for selecting between device local memory and system memory, and
possibly mmap cacheability modes, in the future. At that point, many
more callers will want to specify, so I think we should include flags
in iris_bo_alloc() as well.
A few places used the iris_bo_alloc_tiled() function simply to pass
flags, so this patch converts them to use iris_bo_alloc() instead now
it does everything they want.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11169>
Jason Ekstrand [Mon, 7 Jun 2021 15:18:03 +0000 (10:18 -0500)]
intel/fs/ra: Fix payload node setup for SIMD16 on Gen4-5
Since
40e1d798c6d5, we are now using physical register numbers for
everything which makes it all simpler. In particular, we no longer need
the special case for setting up the payload for SIMD16 on Gen4-5. This
fixes a pile of piglit tests on ILK and similar.
Fixes:
40e1d798c6d5 "intel/fs: Use ra_alloc_contig_reg_class()..."
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11221>
Roman Stratiienko [Mon, 12 Apr 2021 14:44:20 +0000 (17:44 +0300)]
android: Add scripts to build using meson
How to use:
- For GALLIUM drivers:
1. Add gallium drivers into your board.mk file:
board.mk:
BOARD_MESA3D_USES_MESON_BUILD := true
BOARD_MESA3D_GALLIUM_DRIVERS := lima panfrost v3d
2. Add the following packages into your device.mk file:
device.mk:
PRODUCT_PACKAGES += \
libEGL_mesa \
libGLESv1_CM_mesa \
libGLESv2_mesa \
libgallium_dri \
libglapi
- For VULKAN drivers:
1. Add single vulkan driver into your board.mk file:
board.mk:
BOARD_MESA3D_USES_MESON_BUILD := true
BOARD_MESA3D_VULKAN_DRIVERS := freedreno broadcom
2. Add the following package configuration into your device.mk file:
device.mk:
PRODUCT_PACKAGES += \
vulkan.freedreno
PRODUCT_PROPERTY_OVERRIDES += \
ro.hardware.vulkan=freedreno
- To build 'libgbm' set definition in the board.mk:
BOARD_MESA3D_BUILD_LIBGBM := true
And add a package to the device.mk:
PRODUCT_PACKAGES += libgbm
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10183>
Roman Stratiienko [Tue, 20 Apr 2021 15:37:21 +0000 (18:37 +0300)]
meson: egl: Do not build platform_drm for Android
'platform_android' wasn't designed to coexist with 'platform_drm' within
single build, therefore a lot of conflicts appears during compile-time.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10183>
Erik Faye-Lund [Thu, 3 Jun 2021 09:49:48 +0000 (11:49 +0200)]
docs: update master -> main in edit-links
Since the move from master to main, our "Edit on GitLab" links on
docs.mesa3d.org has been pointing to the wrong branch.
Let's fix this, so we don't confuse users who want to contribute
changes.
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11160>
Erik Faye-Lund [Thu, 3 Jun 2021 14:51:09 +0000 (16:51 +0200)]
st/pbo: use correct type for images and textures
Not all hardware can treat float, uint and sint samplers and images the
same way, so we need to respect the format-types here.
This has the added benefit of making sure sint and uint data doesn't
get copied through a float, which might mess with signaling nan
encodings.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11164>
Erik Faye-Lund [Mon, 7 Jun 2021 11:37:49 +0000 (13:37 +0200)]
zink: use a macro for spir-v versions
Instead of repeating constants over and over, let's use a macro for the
SPIR-V version definition instead.
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11044>
Erik Faye-Lund [Thu, 27 May 2021 12:55:55 +0000 (14:55 +0200)]
zink: only enable vote if we can support it
We can only support subgroup vote if we have support for SPIR-V 1.3 or
later.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11044>
Erik Faye-Lund [Thu, 27 May 2021 12:48:52 +0000 (14:48 +0200)]
zink: calculate spir-v version based on vk version
This moves the previous check up to the screen-creation, making it
possible to enable features based on the SPIR-V version.
The reason we want to be able to do this, is so we can force specific
SPIR-V versions, in order to work around bugs in tools.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11044>
Erik Faye-Lund [Thu, 27 May 2021 12:42:12 +0000 (14:42 +0200)]
zink: allow to specify any spir-v version to nir_to_spirv
This will hopefully helps making it easier to override the SPIR-V
version we emit, in case some drivers or tools have issues with too
recent SPIR-V versions.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11044>
Erik Faye-Lund [Thu, 27 May 2021 12:42:12 +0000 (14:42 +0200)]
zink: rename spirv_15 bool to spirv_1_4_interfaces
To make it a bit easier to follow what's going on here, rename the
"spirv_15" boolean to "spirv_1_4_interfaces", and add a comment about
what it's all about.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11044>
Erik Faye-Lund [Sat, 29 May 2021 07:51:29 +0000 (09:51 +0200)]
zink: limit images we mark as cube-compatible
The Vulkan spec says the following:
> If imageType is VK_IMAGE_TYPE_2D and flags contains
> VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT, extent.width and extent.height
> must be equal and arrayLayers must be greater than or equal to 6
This makes a lot of sense, as these are also requirements for being able
to create cubemaps from them in the first place.
Let's thread a bit more careful, and only set this bit in these cases.
This matters in the new case of setting this flag on 2D array textures.
In the other cases, this should already be the case.
I haven't seen this trigger any issues, I just realized this while
reading the Vulkan-spec.
Fixes:
1887ff2ebb7 ("zink: mark 2d-arrays as cube-compatible")
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11081>
Iago Toral Quiroga [Thu, 3 Jun 2021 08:44:49 +0000 (10:44 +0200)]
v3dv: fix incorrect render area setup
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4875
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11158>
Iago Toral Quiroga [Mon, 7 Jun 2021 07:08:22 +0000 (09:08 +0200)]
v3dv: implement VK_KHR_descriptor_update_template
Relevant tests:
dEQP-VK.binding_model.*.with_template.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11213>
Iago Toral Quiroga [Mon, 7 Jun 2021 07:07:00 +0000 (09:07 +0200)]
v3dv: refactor descriptor updates
Make helper functions for all descriptor types and have them handle
all of the descriptor update so we can reuse them later to implement
template updates.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11213>
Tony Wasserka [Mon, 7 Jun 2021 10:02:43 +0000 (12:02 +0200)]
aco/scheduler: Move cursor handling state to dedicated interfaces
This clarifies the semantics of the index variables compared to the previous
version, which used the same variables in a slightly different way depending
on whether they were used for downwards moves or upwards ones.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10885>
Tony Wasserka [Mon, 10 May 2021 09:54:21 +0000 (11:54 +0200)]
aco/scheduler: Clean up register demand tracking
Refactoring total_demand and total_demand_clause to cover non-overlapping
instruction intervals makes the code easier to follow and allows the register
demand to be updated more efficiently in some cases.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10885>
Marcin Ślusarz [Fri, 28 May 2021 16:05:55 +0000 (18:05 +0200)]
intel/disasm: remove useless space after "("
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11070>
Marcin Ślusarz [Fri, 28 May 2021 15:59:21 +0000 (17:59 +0200)]
intel/disasm: decode/describe more send messages
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11070>
Pierre-Eric Pelloux-Prayer [Wed, 26 May 2021 13:19:16 +0000 (15:19 +0200)]
winsys/amdgpu: use int16 for buffer_indices_hashlist
int16 allows to correctly store the indices of 32k buffers; this
seems sufficient and is twice smaller than regular int.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11010>
Pierre-Eric Pelloux-Prayer [Wed, 26 May 2021 10:24:31 +0000 (12:24 +0200)]
winsys/amdgpu: reduce amdgpu_cs size
buffer_indices_hashlist is only used by the current
amdgpu_cs_context (= amdgpu_cs.csc).
So store a single 16k int array instead of 2, and switch
the owner when flushing the cs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11010>
Pierre-Eric Pelloux-Prayer [Wed, 26 May 2021 10:02:48 +0000 (12:02 +0200)]
amdgpu/winsys: remove amdgpu_cs_has_chaining
Store this property in admgpu_cs instead of using a function.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11010>
Pierre-Eric Pelloux-Prayer [Mon, 17 May 2021 16:41:26 +0000 (18:41 +0200)]
winsys/amdgpu: don't read bo->u.slab.entry after pb_slab_free
Otherwise the pb_slabs might be freed by another thread in between.
Valgrind example:
==676841== Invalid read of size 1
==676841== at 0x6B0A8B3: get_slab_wasted_size (amdgpu_bo.c:659)
==676841== by 0x6B0AD7D: amdgpu_bo_slab_destroy (amdgpu_bo.c:684)
==676841== by 0x6ACF94F: pb_destroy (pb_buffer.h:259)
==676841== by 0x6ACF94F: pb_reference_with_winsys (pb_buffer.h:282)
==676841== by 0x6ACF94F: radeon_bo_reference (radeon_winsys.h:754)
==676841== by 0x6ACF94F: si_replace_buffer_storage (si_buffer.c:274)
==676841== by 0x6957036: tc_call_replace_buffer_storage (u_threaded_context.c:1554)
[...]
==676841== by 0x4ECCDEE: clone (clone.S:95)
==676841== Address 0x27879945 is 5 bytes inside a block of size 208 free'd
==676841== at 0x48399AB: free (vg_replace_malloc.c:538)
==676841== by 0x6B0E8BD: amdgpu_bo_slab_free (amdgpu_bo.c:863)
==676841== by 0x6B89D4A: pb_slabs_reclaim_locked (pb_slab.c:84)
==676841== by 0x6B89D4A: pb_slab_alloc (pb_slab.c:130)
==676841== by 0x6B0EE7F: amdgpu_bo_create (amdgpu_bo.c:1429)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4736
Fixes:
965c6445ad4 ("winsys/amdgpu,radeonsi: add HUD counters for how much memory is wasted by slabs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11010>
Pierre-Eric Pelloux-Prayer [Fri, 4 Jun 2021 10:21:58 +0000 (12:21 +0200)]
radeonsi: dirty msaa_config on rs->multisample_enable change
si_emit_msaa_config uses si_get_num_coverage_samples, and
si_get_num_coverage_samples depends on old_rs->multisample_enable.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4613
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11182>
Iago Toral Quiroga [Fri, 4 Jun 2021 12:00:47 +0000 (14:00 +0200)]
v3dv: expose VK_KHR_storage_buffer_storage_class
This extension is basically only wrapping SPV_KHR_storage_buffer_storage_class
which is entirely implemented in the SPIR-V frontend.
Relevant CTS tests:
dEQP-VK.glsl.opaque_type_indexing.ssbo_storage_buffer_decoration.*
dEQP-VK.spirv_assembly.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11184>
Iago Toral Quiroga [Fri, 4 Jun 2021 12:00:13 +0000 (14:00 +0200)]
v3dv: document VK_KHR_relaxed_block_layout as implemented
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11184>
Steve Pronovost [Sun, 25 Apr 2021 18:20:46 +0000 (11:20 -0700)]
d3d12: Add mechanism for D3D12 Adapter Selection
This add a simple mechanism to select which GPU adapter the d3d12
driver should be using. A new environment variable is introduced.
MESA_D3D12_DEFAULT_ADAPTER_NAME
This represent a substring to search for in the GPU descrition,
for example "NVIDIA" or "INTEL", or "NVIDIA GeForce RTX 3090",
etc...
GPU are searched in order and the first one to include the substring
becomes a match. If no match is found, we default to the first
enumerated GPU.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10710>