mesa: Avoid temp images in _mesa_texstore_rgb_dxt1 for GL_RGBA source

The compressor can handle 3 or 4-component sources, so allow a GL_RGBA
source and just pass that along with the correct number of components.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16631>

mesa: Split tx_compress_dxtn into per-format functions

This avoids an unnecessary switch statement in many cases.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16631>

st/mesa: remove unused GENERIC input and output from the clear VS

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16711>

r300,r600,svga: save the FS constant buffer for u_blitter to fix a regression

Fixes: 773a23eb6da - gallium/u_blitter: clear color buffers using color from a constant buffer
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6548
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6539

Tested-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16711>

util: Fixes typo in test_util_get_process_exec_path

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16723>

util: Fixes test_util_get_process_exec_path on windows host with msys2/mingw

```
stderr:
Error: Test 'test_util_get_process_exec_path' failed:
        Expected="C:/work/xemu/xemu-opengl/mesa/build/windows-mingw64/src/util/process_test.exe", Actual="C:\work\xemu\xemu-opengl\mesa\build\windows-mingw64\src\util\process_test.exe"
――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――
```

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16723>

v3dv/format: Add support for VK_KHR_format_feature_flags2

VK_KHR_format_feature_flags2 is mostly about define a new 64-bit
VkFormatFeatureFlagBits2KHR format feature flag type, as 29 bits of
the 32-bit VkFormatFeatureFlagBits are already in use.

So all the bits from VkFormatFeatureFlagBits are being replicated, and
most of the work here consist on switch to the new flags.

From the new (not replicated from VkFormatFeatureFlagBits) flag bits,
we don't support
VK_FORMAT_FEATURE_2_STORAGE_READ_WITHOUT_FORMAT_BIT_KHR or
VK_FORMAT_FEATURE_2_STORAGE_WRITE_WITHOUT_FORMAT_BIT_KHR, as right now
we require the format on the shader for doing the read and stores.

We use now VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_DEPTH_COMPARISON_BIT_KHR,
but only applying it for depth formats.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16718>

v3dv/format: no need for GetPhysicalDeviceFormatProperties

The common Mesa Vulkan framework already provides a common
implementation based on GetPhysicalDeviceFormatProperties2.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16718>

zink: update radv piglit fails

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16727>

panfrost: Use tiled AFBC textures

On GPUs that support AFBC with tiled headers, try to use tiled headers instead
of linear headers. This should be a bit more efficient for the caches.
Additionally, on Mali, tiled headers are tied to solid colour blocks, so this
has the effect of enabling AFBC with solid colour blocks where supported.

Unfortunately, results are disappointing. Mali-G52:

-btexture from 856fps to 859fps
-bdesktop from 292fps to 294fps

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Advertise 16x16 tiled AFBC

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Gate tiled AFBC on GPUs that support it

Introduced with v7.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Add helper checking tiled AFBC support

Tiled AFBC support was introduced with v7. Add a helper encoding this fact.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Handle AFBC Tiled

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Put comment in correct #ifdef

Minor fix to make the code less confusing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Fix AFBC flags on v6

Tiled headers and bounds checking were introduced with v7. The flags don't exist
on v6. Fix the XML accordingly so we don't accidentally use features too new for
the hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Add 1x1 layout unit tests

These check the alignments are correct. Of course, ideally these cases aren't
hit in practice, since it's a waste of memory.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Add a tiled 16x16 layout unit test

To exercise the layout code introduced in this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Calculate header_size based on row_stride

The header size is the header stride times the number of rows in the header
(number of tiles of superblocks). We already calculate the header stride, so
eliminate the separate header size calculation.

Delete the old header size calculation. It has no notion of wide blocks, let
alone tiled AFBC headers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Add 3D texture layout unit test

3D AFBC is pretty subtle, let's make sure we have adequate unit test coverage.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Add AFBC stride unit tests

Demonstrating correctness of the low level calculations.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Align layouts to tiles of superblocks

Required to satisfy the alignment constraints on tiled AFBC.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Support tiled AFBC in stride helpers

Part 1 of tiled AFBC. This requires modifier information.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Add pan_afbc_tile_size helper

To unify calculations with linear and tiled AFBC formats.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Fix is_wide return type

By inspection.

Fixes: e4ee2c213a0 ("panfrost: Extract panfrost_afbc_is_wide helper")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Extract pan_afbc_row_stride helper

Extract a helper for calculating AFBC strides. This is used in two places in
pan_layout. It will need extension for tiled AFBC, and the extended version
could benefit from unit testing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Extract afbc_stride_blocks helper

Let's keep all the AFBC computations inside the layout code, to keep pan_cs
dumb. This helper will need some extension for tiled AFBC.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>

panfrost: Fix crash with GALLIUM_HUD

Due to the order of binding shaders, GALLIUM_HUD triggered a NULL pointer
dereference in the new shader variants code.

Fixes: 0fcddd4d2c4 ("pan/bi: Rework varying linking on Valhall")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16707>

radeonsi: Set display_remote for non-refernced frames

When we do SVC temporal encoding, we see output bitsream is not proper. To fix
this , incase of SVC passing session init varaible display_remote as enable.

Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16468>

ir3: handle gl_Layer and gl_ViewportIndex when there is TES + GS

Fixes CTS tests:
 KHR-GL46.shader_viewport_layer_array.ShaderViewportIndexTestCase
 KHR-GL46.shader_viewport_layer_array.ShaderLayerFramebufferLayeredTestCase
 KHR-GL46.shader_viewport_layer_array.ShaderLayerFramebufferNonLayeredTestCase

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6497

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16696>

radv: fix writing buffer markers with non-zero memory offset

Found by insepction.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16698>

radv: use pipeline->slab_bo in more places

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16687>

radv: disable attachementFragmentShadingRate on GFX11

The VRS image no longer uses HTILE like on GFX10.3 and I don't know
yet how to program it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: disable VK_AMD_shader_fragment_mask on GFX11

No FMASK on GFX11 which means I don't think we can expose this ext.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: configure DB_Z_INFO.NUM_SAMPLES correctly on GFX11

It affects VRS and occlusion queries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: fix VK_BLEND_FACTOR_CONSTANT_COLOR translation on GFX11

This one was missing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: fix configuring COLOR_INVALID on GFX11

It's a different bitfield but this one was missing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: report adjusted LDS size for fragment shaders on GFX11

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: use the fragment resolve path by default on GFX11

GFX11 doesn't support CB_RESOLVE which means it doesn't support the
hardware resolve path. If necessary (for arrays or integer formats)
the driver will select the compute path.

No CTS regressions by forcing the fragment resolve path on GFX10.3

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: update VRS rates on GFX11

GFX11 uses enum instead of 2-bit integer numbers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
iReviewed-by: Timur Kristóf <timur.kristof@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: update framebuffer registers on GFX11

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: do not emit more non-existent registers on GFX11

Found these by diffing the list of registers between GFX10_3 and GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

radv: rename VERT_GRP_SIZE to VERTS_PER_SUBGRP on GFX11

Same bitfield but it has been renamed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

util/perf: add options to enable/disable tracepoints

We want to add more tracepoints for intel drivers. Having them all
enabled at the same time can be both costly and unreadable.

This allows a driver to specify an environment variable and values to
enable/disable tracepoints.

v2: s/TRACEPOINTS_ENABLES/TRACEPOINTS_TOGGLES/ (Danylo)
    s/config_name/toggle_name/

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16717>

util/debug: add an enable parsing helper

This allows to parse something like :

 ENV_VAR=+a,-b

which will enable a and disable b.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16717>

intel/disasm: add missing handling of <1;1,0>

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7cd9adeb415e ("intel/compiler: In XeHP prefer <1;1,0> regions before compacting")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16704>

llvmpipe: flush resources for kms swrast path.

The kms_swrast path calls this callback via the dri2 paths,
not flushing caused artifacts when running inside a VM or on hw
in weston/gnome-shell.

Fixes: 6bbbe15a783a ("Reinstate: llvmpipe: allow vertex processing and fragment processing in parallel")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16715>

zink: add renderpass bits for color/depth r/w

these are different renderpasses according to compatibility rules

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16621>

zink: use a zink_render_pass_pipeline_state bit for fbfetch

improve compatibility detection

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16621>

egl/wgl: On win32, there is no support for EGL_EXT_device and EGL_EXT_platform_device

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16537>

dri2: Fix memory leak.

Fix defect reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable psp going out of scope leaks the storage it points to.

Fixes: 68aa2099fa4 ("dri2: Require a loader with working buffer invalidation")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16680>

pan/bi: Allow CSEing LEA_BUF_IMM

Cleans up the code gen a lot in varying shaders. Instruction count regression
due to how we handle 64-bit on Valhall. (TODO: A better solution for that...)

total instructions in shared programs: 2730186 -> 2736193 (0.22%)
instructions in affected programs: 775825 -> 781832 (0.77%)
helped: 2010
HURT: 4433
helped stats (abs) min: 1.0 max: 18.0 x̄: 2.16 x̃: 2
helped stats (rel) min: 0.16% max: 26.67% x̄: 3.75% x̃: 2.22%
HURT stats (abs)   min: 1.0 max: 10.0 x̄: 2.33 x̃: 2
HURT stats (rel)   min: 0.20% max: 23.08% x̄: 4.79% x̃: 2.79%
95% mean confidence interval for instructions value: 0.87 1.00
95% mean confidence interval for instructions %-change: 1.98% 2.27%
Instructions are HURT.

total cycles in shared programs: 161178.77 -> 144303.77 (-10.47%)
cycles in affected programs: 85720 -> 68845 (-19.69%)
helped: 6910
HURT: 0
helped stats (abs) min: 1.0 max: 18.0 x̄: 2.44 x̃: 2
helped stats (rel) min: 1.05% max: 41.18% x̄: 19.72% x̃: 20.00%
95% mean confidence interval for cycles value: -2.48 -2.41
95% mean confidence interval for cycles %-change: -19.86% -19.58%
Cycles are helped.

total cvt in shared programs: 13655.45 -> 14013 (2.62%)
cvt in affected programs: 2978.06 -> 3335.61 (12.01%)
helped: 381
HURT: 5242
helped stats (abs) min: 0.015625 max: 0.0625 x̄: 0.02 x̃: 0
helped stats (rel) min: 0.37% max: 50.00% x̄: 7.61% x̃: 3.85%
HURT stats (abs)   min: 0.015625 max: 0.296875 x̄: 0.07 x̃: 0
HURT stats (rel)   min: 0.00% max: 400.00% x̄: 28.51% x̃: 16.00%
95% mean confidence interval for cvt value: 0.06 0.06
95% mean confidence interval for cvt %-change: 25.13% 27.00%
Cvt are HURT.

total ls in shared programs: 147856 -> 130980 (-11.41%)
ls in affected programs: 85725 -> 68849 (-19.69%)
helped: 6911
HURT: 0
helped stats (abs) min: 1.0 max: 18.0 x̄: 2.44 x̃: 2
helped stats (rel) min: 1.05% max: 41.18% x̄: 19.72% x̃: 20.00%
95% mean confidence interval for ls value: -2.48 -2.41
95% mean confidence interval for ls %-change: -19.86% -19.58%
Ls are helped.

total quadwords in shared programs: 1483576 -> 1486872 (0.22%)
quadwords in affected programs: 73816 -> 77112 (4.47%)
helped: 286
HURT: 698
helped stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
helped stats (rel) min: 2.38% max: 50.00% x̄: 16.83% x̃: 16.67%
HURT stats (abs)   min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel)   min: 2.78% max: 100.00% x̄: 37.38% x̃: 16.67%
95% mean confidence interval for quadwords value: 2.89 3.80
95% mean confidence interval for quadwords %-change: 19.02% 24.22%
Quadwords are HURT.

total threads in shared programs: 53186 -> 53189 (<.01%)
threads in affected programs: 3 -> 6 (100.00%)
helped: 3
HURT: 0
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%

total fills in shared programs: 2172 -> 2163 (-0.41%)
fills in affected programs: 11 -> 2 (-81.82%)
helped: 1
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16710>

kopper: Only include XCB headers on supported platforms

Fixes: 054bd2d38f83 ("kopper: copy a bunch of code for texture_from_pixmap")

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16675>

pan/bi: Schedule for pressure pre-RA

Add a bottom-up pre-RA list scheduler that aims to reduce register pressure,
roughly the same as we use on Midgard to great effect. It uses a simple
heuristic: greedily select instructions that have reduce liveness.  To avoid
regressions, the algorithm throws away schedules that increase maximum number of
lives (used as an estimate of register pressure -- if we had SSA form, this
would be exact).

We might be better off using Sarkar. But for something I could type out in an
afternoon, I'll happily accept a >50% reduction in spills. Instruction count is
regressed due to extra moves around the blend shader ABI in some cases, at least
on Bifrost this is mostly hidden by the clause scheduler. Thread count and
spills/fills are both much improved here.

There are numerous opportunities for future improvements to pre-RA scheduling:

* Better heuristics? (Something more global than liveness alone)
* Reducing false dependencies with memory access
* Improve ILP for message-passing instructions? This is a tradeoff.
* Simplify the code if we have SSA in the future.

But for now, I think this is well worth it already.

v2: Various clean-ups and memory leak fix (Icecream95). Reduce false
dependencies to eliminate spilling in more shaders.

shader-db stats on Mali-G52:

total instructions in shared programs: 2438841 -> 2439698 (0.04%)
instructions in affected programs: 1206421 -> 1207278 (0.07%)
helped: 3113
HURT: 4011
helped stats (abs) min: 1.0 max: 50.0 x̄: 3.25 x̃: 2
helped stats (rel) min: 0.13% max: 44.83% x̄: 4.09% x̃: 2.11%
HURT stats (abs)   min: 1.0 max: 18.0 x̄: 2.73 x̃: 2
HURT stats (rel)   min: 0.11% max: 57.14% x̄: 3.86% x̃: 2.07%
95% mean confidence interval for instructions value: 0.02 0.22
95% mean confidence interval for instructions %-change: 0.23% 0.54%
Instructions are HURT.

total tuples in shared programs: 1927077 -> 1946583 (1.01%)
tuples in affected programs: 1118627 -> 1138133 (1.74%)
helped: 2874
HURT: 6295
helped stats (abs) min: 1.0 max: 82.0 x̄: 3.51 x̃: 2
helped stats (rel) min: 0.17% max: 33.33% x̄: 4.60% x̃: 3.57%
HURT stats (abs)   min: 1.0 max: 47.0 x̄: 4.70 x̃: 3
HURT stats (rel)   min: 0.20% max: 50.00% x̄: 5.16% x̃: 4.32%
95% mean confidence interval for tuples value: 2.00 2.25
95% mean confidence interval for tuples %-change: 1.97% 2.23%
Tuples are HURT.

total clauses in shared programs: 356053 -> 357793 (0.49%)
clauses in affected programs: 151578 -> 153318 (1.15%)
helped: 2196
HURT: 3813
helped stats (abs) min: 1.0 max: 49.0 x̄: 2.16 x̃: 1
helped stats (rel) min: 0.18% max: 69.01% x̄: 10.26% x̃: 8.33%
HURT stats (abs)   min: 1.0 max: 25.0 x̄: 1.70 x̃: 1
HURT stats (rel)   min: 0.57% max: 66.67% x̄: 10.64% x̃: 8.33%
95% mean confidence interval for clauses value: 0.22 0.36
95% mean confidence interval for clauses %-change: 2.68% 3.33%
Clauses are HURT.

total cycles in shared programs: 167761.17 -> 167922.04 (0.10%)
cycles in affected programs: 24494.21 -> 24655.08 (0.66%)
helped: 862
HURT: 3054
helped stats (abs) min: 0.041665999999999315 max: 53.0 x̄: 0.69 x̃: 0
helped stats (rel) min: 0.28% max: 76.81% x̄: 5.65% x̃: 3.03%
HURT stats (abs)   min: 0.041665999999999315 max: 2.0416659999999993 x̄: 0.25 x̃: 0
HURT stats (rel)   min: 0.26% max: 41.18% x̄: 4.91% x̃: 3.92%
95% mean confidence interval for cycles value: -0.04 0.12
95% mean confidence interval for cycles %-change: 2.36% 2.81%
Inconclusive result (value mean confidence interval includes 0).

total arith in shared programs: 73875.37 -> 74393.17 (0.70%)
arith in affected programs: 43142.42 -> 43660.21 (1.20%)
helped: 3632
HURT: 5443
helped stats (abs) min: 0.041665999999999315 max: 1.2083360000000027 x̄: 0.15 x̃: 0
helped stats (rel) min: 0.22% max: 100.00% x̄: 6.70% x̃: 4.76%
HURT stats (abs)   min: 0.041665999999999315 max: 2.0416659999999993 x̄: 0.19 x̃: 0
HURT stats (rel)   min: 0.00% max: 166.67% x̄: 5.91% x̃: 4.08%
95% mean confidence interval for arith value: 0.05 0.06
95% mean confidence interval for arith %-change: 0.65% 1.07%
Arith are HURT.

total texture in shared programs: 11936 -> 11936 (0.00%)
texture in affected programs: 0 -> 0
helped: 0
HURT: 0

total vary in shared programs: 4180.88 -> 4180.88 (0.00%)
vary in affected programs: 0 -> 0
helped: 0
HURT: 0

total ldst in shared programs: 137551 -> 137028 (-0.38%)
ldst in affected programs: 834 -> 311 (-62.71%)
helped: 13
HURT: 0
helped stats (abs) min: 15.0 max: 53.0 x̄: 40.23 x̃: 53
helped stats (rel) min: 19.15% max: 100.00% x̄: 68.11% x̃: 76.81%
95% mean confidence interval for ldst value: -50.49 -29.98
95% mean confidence interval for ldst %-change: -84.37% -51.84%
Ldst are helped.

total quadwords in shared programs: 1684883 -> 1692021 (0.42%)
quadwords in affected programs: 949463 -> 956601 (0.75%)
helped: 3981
HURT: 5098
helped stats (abs) min: 1.0 max: 86.0 x̄: 3.53 x̃: 3
helped stats (rel) min: 0.18% max: 33.33% x̄: 5.82% x̃: 4.48%
HURT stats (abs)   min: 1.0 max: 50.0 x̄: 4.15 x̃: 3
HURT stats (rel)   min: 0.17% max: 50.00% x̄: 5.11% x̃: 3.85%
95% mean confidence interval for quadwords value: 0.67 0.90
95% mean confidence interval for quadwords %-change: 0.17% 0.47%
Quadwords are HURT.

total threads in shared programs: 53276 -> 53653 (0.71%)
threads in affected programs: 581 -> 958 (64.89%)
helped: 445
HURT: 68
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.68 0.79
95% mean confidence interval for threads %-change: 75.70% 84.53%
Threads are helped.

total preloads in shared programs: 116312 -> 116312 (0.00%)
preloads in affected programs: 0 -> 0
helped: 0
HURT: 0

total loops in shared programs: 128 -> 128 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 92 -> 37 (-59.78%)
spills in affected programs: 55 -> 0
helped: 13
HURT: 0

total fills in shared programs: 658 -> 190 (-71.12%)
fills in affected programs: 468 -> 0
helped: 13
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16378>

pan/bi: Recoalesce tied operands after spilling

Otherwise we can fail to allocate tied operands if we spill the tied operand.
Seen in shaders/android/com.miHoYo.GenshinImpact/16.shader_test with a
particularly bad scheduling causing excessive spilling.

No shader-db changes.

Fixes: bc17288697f ("pan/bi: Lower split/collect before RA")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16378>

radeonsi: Add support for EGL_IMG_context_priority

This allows creating high priority contexts when using radeonsi. It's
primarily intended for apps whose rendering commands must be processed
as soon as possible, e.g. wayland compositors.

Signed-off-by: Vlad Zahorodnii <vlad.zahorodnii@kde.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16594>

winsys/amdgpu-radeon: Allow specifying context priority

This is needed to implement EGL_IMG_context_priority in radeonsi.

Signed-off-by: Vlad Zahorodnii <vlad.zahorodnii@kde.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16594>

zink: radv ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16706>

radv: Disable predication for supass clear and image clears.

According to the Vulkan spec 21.4 "Conditional Rendering",
only clearing attachments with vkCmdClearAttachments is subject to
conditional rendering.

Subpass clear and vkCmdClearColorImage / vkCmdClearDepthStencilImage
should always be executed even if it happens in a
conditional rendering block.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16654>

radv: Remove trailing whitespace.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16702>

aco: Remove trailing whitespace.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16702>

ac: Remove trailing white space.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16702>

ac: reset LLVM command line parser

In some scenario ac_init_llvm_target may be called twice,
but the LLVM library won't have been unloaded between
the 2 calls, leading to a LLVM warning being printed.

Example pseudo-code to trigger this for radeonsi:
   gbm_create_device();
   eglInitialize();
   eglTerminate();
   gbm_device_destroy();
   gbm_create_device();
   eglInitialize();
   eglTerminate();
   gbm_device_destroy();

To avoid the warning message from LLVM, clear the command line
parser state before calling LLVMParseCommandLineOptions.

This might fix https://gitlab.freedesktop.org/mesa/mesa/-/issues/5960

This is done only on LLVM 12+ because it seems to break some apps
on LLVM 11 (there has been some work post LLVM 11 release to refactor
CommandLine.cpp, see 42f588f39c5c and the following commits).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16587>

ac: export LLVM c++ ResetCommandLineParser method

This method isn't part of the C API but we can still use it and
avoid getting error messages from the command line parser:

   mesa: for the [...]: may only occur zero or one times

We could call it at the beginning of ac_init_llvm_target but
this may hide some real bugs so let drivers call it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16587>

radeonsi: don't use sel->nir in si_check_blend_dst_sampler_noop

We don't want to modify sel->nir so force the use of the serialized
version of the shader.
Waiting on sel->ready guarantees that sel->nir will be NULL and that
si_get_nir_shader will use sel->nir_binary.

Fixes: b78a38bd022 ("radeonsi: use si_nir_is_output_const_if_tex_is_const")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6415
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16587>

radv: move active_stages to radv_graphics_pipeline

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>

radv: move streamout_shader to radv_graphics_pipeline

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>

radv: unify radv_pipeline_has_XXX() helpers

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>

radv: rename radv_cmd_state::pipeline to graphics_pipeline

To be consistent with compute pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>

radv: move HS info and task_num_entries to the physical device

They are not logical device properties.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>

radv: Implement conditional rendering for async compute queue.

MEC (the compute queue firmware) does not support real
predication, so we have to emulate that using COND_EXEC
packets before each dispatch.

Additionally, COND_EXEC doesn't have an inverted mode, so
in order to support inverted mode conditional rendering, we
allocate a new piece of memory in which we invert the condition.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6533
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16653>

v3dv/bo: unmap any bo that goes to the bo cache

As it could happens that when a bo is reused from the cache, it is
being mapped with a smaller size that needed. So let's just unmap it,
and let be remapped with the needed size.

Even if we could try to be smarter when deciding when to unmap or not,
to avoid uneeded re-mappings later, it is also true that doing the
unmap would help to reduce the memory used.

This fixes an assert when running the following tests in a row (same
deqp-vk execution):
   dEQP-VK.pipeline.creation_feedback.graphics_tests.vertex_stage_fragment_stage
   dEQP-VK.pipeline.executable_properties.graphics.vertex_stage_geometry_stage_fragment_stage
   dEQP-VK.pipeline.executable_properties.graphics.vertex_stage_fragment_stage_internal_representations

That hits the following assertion:
   assert(qpu_bo && qpu_bo->map_size >= variant->assembly_offset +
                                        variant->qpu_insts_size);
at v3dv_pipeline.c, pipeline_get_qpu.

v2: use just one call to v3dv_bo_unmap (move call at v3dv_bo_free,
    replace call at bo_free for assert) (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16678>

intel/compiler: Move spill/fill tracking to the register allocator

Originally, we had virtual opcodes for scratch access, and let the
generator count spills/fills separately from other sends.  Later, we
started using the generic SHADER_OPCODE_SEND for spills/fills on some
generations of hardware, and simply detected stateless messages there.

But then we started using stateless messages for other things:
- anv uses stateless messages for the buffer device address feature.
- nir_opt_large_constants generates stateless messages.
- XeHP curbe setup can generate stateless messages.

So counting stateless messages is not accurate.  Instead, we move the
spill/fill accounting to the register allocator, as it generates such
things, as well as the load/store_scratch intrinsic handling, as those
are basically spill/fills, just at a higher level.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16691>

lavapipe: fix depth bias offset flag enables.

When vulkan enables depth bias, enable it for all 3 prim types
in gallium.

This fixes:
dEQP-VK.draw.renderpass.depth_bias.depth_bias_*
and
one zink test in CI

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16701>

zink: use XOR for descriptor hash accumulation

these values are already hashed, so there's no need to use as much cpu
to fully re-hash them again

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16645>

zink: add a "compact" descriptor mode

this compacts the ubo+ssbo and samplerview+image sets, enabling zink
to run fully featured with only 4 descriptor sets used

fixes #4964

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16645>

zink: flag descriptor sets as changed before updating hashes

if the program changes, assume the hashes changed

this could probably be improved in the future to check for matching shader
interfaces, but that's a problem for later

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16645>

zink: use descriptor set index indirection in cache state updates

no functional changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16645>

zink: use descriptor set index indirection in program init

should be no functional changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16645>

zink: use descriptor indices in compiler

should be no functional changes, just adding indirection

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16645>

zink: add screen-based indexing to descriptor sets

this allows indirection for internal descriptor type -> vk descriptor set
and enables more easily altering the descriptor set index at runtime

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16645>

zink: create all descriptor ref templates at once

no functional changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16645>

zink: clamp dynamic render layerCount to 1

util function unhelpfully returns 0

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16656>

zink: only warn once for SRGB fb without KHR_swapchain_mutable_format

Fixes: 4bb45bcd168 ("zink: add error logging for SRGB framebuffer without KHR_swapchain_mutable_format")

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16642>

venus: use common entry point for VkPhysicalDeviceMemoryProperties

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16694>

radv: remove VkPhysicalDeviceMemoryProperties2 workaround

This reverts 03888bf09c0dce42d1857f3c7acbb86715837198

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16694>

vulkan: remove the VkPhysicalDeviceMemoryProperties workaround

cts fix landed in vulkan-cts-1.2.5 while mesa CI has bumped once.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16694>

anv: Update line range

This commit increases the maximum line width to 8.0 for SLK+
and to 7.9921875 for BDW and earlier.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6234
Fixes: fce0027d ("anv: Unbreak wide lines on HSW/BDW")
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15879>

intel: Fix analysis invalidation in eliminate_find_live_channel

If we saw a HALT instruction, we would forget to invalidate our analysis
pass information before returning progress.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16677>

intel/tools: fix 32-bit build

Fixes: 0aac3b1009d ("intel/tools/aubinator: add support for 2 "new" subopcodes")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6553
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16695>

nir: add load_task_payload intrinsic to nir_divergence_analysis

It's divergent depending on sources.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16668>

nir: add load_mesh_inline_data_intel intrinsic to nir_divergence_analysis

It's not divergent.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16668>

nir: Add explicit task payload atomic intrinsics.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16693>

panfrost: Don't allocate SHARED as scanout

This is useless and might cause problems.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Extremely-acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16334>

panfrost: Simplify the kmsro create path

Unify the "create regular resource" and "create scanout resource" code paths.
They only differ in how the backing memory is allocated. This unifies the layout
code as well, avoiding hacks for AFBC.

What I really care about is that, if we're creating the resource, we choose the
layout first with pan_image_layout_init and allocate that layout.
pan_image_layout_init is a common, extensively tested (including unit tested)
helper written for correctness with a deep understanding of the hardware.

By contrast, we currently guess the layout with some hacks specific to AFBC,
allocate our guess, and then then tell pan_image_layout_init to use the layout
we guessed and pray everything works out. (It does work out, but it's all kinds
of wrong, in terms of layering violation. If that really is the way to go, I can
add the required routines to the layout code. But that doesn't seem right.)

All of this is motivated by extending the layout code to handle AFBC with other
superblock sizes or tiled headers without having to pile on extra hacks in this
WSI path.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16334>

meson: Add build option for gallium-d3d12-video feature

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6511
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16597>

meson: Update DirectX-Headers dependency to 1.602.0 version with fallback to the wrap

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16597>

panfrost: Only write depth / stencil once if MRT is used

We can't assume that RT0 will be written, so this has to be based on
whether a combined store has already been emitted, not the location of
the store.

Emit a non-special combined_store intrinsic that only writes colour
for the other RTs, as reordering stores breaks the Midgard compiler.

Fixes: d37e901e35a ("pan/mdg: Add new depth store lowering")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6527
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16685>

pan/mdg: Read base for combined stores

Fixes depth/stencil writes with MRT.

Fixes: b3d72727537 ("pan/mdg: Don't read base for combined stores")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16685>

pan/bi: Read base for combined stores

Fixes depth/stencil writes with MRT.

Fixes: 996645e4794 ("pan/bi: Don't read base for combined stores")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16685>