Heejin Ahn [Wed, 22 Aug 2018 00:33:34 +0000 (00:33 +0000)]
[WebAssembly] Fix typos in mem.grow/memory.grow opcodes
This should be not 0x3f but 0x40.
llvm-svn: 340373
Heejin Ahn [Wed, 22 Aug 2018 00:20:02 +0000 (00:20 +0000)]
[WebAssembly] Change comments on SP writing back (NFC)
Summary: We now write back not to memory but to __stack_pointer global.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51074
llvm-svn: 340372
Vedant Kumar [Wed, 22 Aug 2018 00:10:37 +0000 (00:10 +0000)]
[CodeGenPrepare] Set debug locations when splitting selects
When splitting a select into a diamond, set debug locations on
newly-created branch instructions and phi nodes.
llvm-svn: 340371
Vedant Kumar [Tue, 21 Aug 2018 23:43:08 +0000 (23:43 +0000)]
[CodeGenPrepare] Clean up dbg.value use-before-def as late as possible
CodeGenPrepare has a strategy for moving dbg.values so that a value's
definition always dominates its debug users. This cleanup was happening
too early (before certain CGP transforms were run), resulting in some
dbg.value use-before-def errors.
Perform this cleanup as late as possible to avoid use-before-def.
llvm-svn: 340370
Vedant Kumar [Tue, 21 Aug 2018 23:42:53 +0000 (23:42 +0000)]
[CodeGenPrepare] Pre-commit debug info test for optimizeSelectInst
This test shows that optimizeSelectInst splits a select and sinks a
`fdiv` operation to one side of the diamond. However, the dbg.value for
the operation isn't moved.
llvm-svn: 340369
Vedant Kumar [Tue, 21 Aug 2018 23:42:38 +0000 (23:42 +0000)]
[CodeGenPrepare] Scan past debug intrinsics to find select candidates (NFC)
In optimizeSelectInst, when scanning for candidate selects to rewrite
into branches, scan past debug intrinsics. This makes the debug-enabled
and non-debug paths through optimizeSelectInst more congruent.
NFC because every select is eventually visited either way.
llvm-svn: 340368
Vedant Kumar [Tue, 21 Aug 2018 23:42:23 +0000 (23:42 +0000)]
[CodeGenPrepare] Exit earlier when optimizing selects (NFC)
When optimizing for size, this allows optimizeSelectInst to skip a
linear scan and exit early.
llvm-svn: 340367
Vedant Kumar [Tue, 21 Aug 2018 23:42:08 +0000 (23:42 +0000)]
Avoid dbg.value use-before-def in a few tests (NFC)
This is preparation for landing a use-before-def verifier for debug
intrinsics (D46100).
As a drive-by, remove `tail` from debug intrinsic calls because it
doesn't mean anything in that context.
llvm-svn: 340366
Alina Sbirlea [Tue, 21 Aug 2018 23:32:03 +0000 (23:32 +0000)]
Update MemorySSA in BasicBlockUtils.
Summary:
Extend BasicBlocksUtils to update MemorySSA.
Subscribers: sanjoy, arsenm, nhaehnle, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D45300
llvm-svn: 340365
Fangrui Song [Tue, 21 Aug 2018 23:28:12 +0000 (23:28 +0000)]
[ELF] -thinlto-object-suffix-replace=: don't error if the path does not end with old suffix
Summary:
For -thinlto-object-suffix-replace=old\;new, in
tools/gold/gold-plugin.cpp, the thinlto object filename is Path minus
optional old suffix.
static std::string getThinLTOObjectFileName(StringRef Path, StringRef OldSuffix,
StringRef NewSuffix) {
if (OldSuffix.empty() && NewSuffix.empty())
return Path;
StringRef NewPath = Path;
NewPath.consume_back(OldSuffix);
std::string NewNewPath = NewPath;
NewNewPath += NewSuffix;
return NewNewPath;
}
Currently lld will error that the path does not end with old suffix.
This patch makes lld accept such paths but only add new suffix if Path
ends with old suffix. This fixes a link error where bitcode members in
an archive are regular LTO objects without old suffix.
Acording to tejohnson, this will "enable supporting mix and match of
minimized ThinLTO bitcode files with normal ThinLTO bitcode files in a
single link (where we want to apply the suffix replacement to the
minimized files, and just ignore it for the normal ThinLTO files)."
Reviewers: ruiu, pcc, tejohnson, espindola
Reviewed By: tejohnson
Subscribers: emaste, inglorion, arichardson, eraman, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D51055
llvm-svn: 340364
Alina Sbirlea [Tue, 21 Aug 2018 23:13:02 +0000 (23:13 +0000)]
[MemorySSA] Update comment for move APIs to clarify behavior (NFC).
llvm-svn: 340362
Richard Trieu [Tue, 21 Aug 2018 22:55:26 +0000 (22:55 +0000)]
Add space to TemplateArgument dump
Add a missing space when dumping a template argument which is a template
expansion. Found during debugging so no test.
llvm-svn: 340357
Zachary Turner [Tue, 21 Aug 2018 22:52:52 +0000 (22:52 +0000)]
[MS Demangler] Print template constructor args.
Previously if you had something like this:
template<typename T>
struct Foo {
template<typename U>
Foo(U);
};
Foo F(3.7);
this would mangle as ??$?0N@?$Foo@H@@QEAA@N@Z
and this would be demangled as:
undname: __cdecl Foo<int>::Foo<int><double>(double)
llvm-undname: __cdecl Foo<int>::Foo<int>(double)
Note the lack of the constructor template parameter in our
demangling.
This patch makes it so we print the constructor argument list.
llvm-svn: 340356
Kuba Mracek [Tue, 21 Aug 2018 22:35:52 +0000 (22:35 +0000)]
[tsan] Adjust setjmp/longjmp handling on Darwin for macOS Mojave
On macOS Mojave, the OS started using the XOR-by-a-secret-key scheme (same as glibc is alread doing) for storing the SP value in setjmp environment. We need to adjust for that to keep supporting setjmp/longjmp on latest Darwin. The patch is basically doing the same what we're already doing for glibc.
rdar://problem/
43542596
Differential Revision: https://reviews.llvm.org/D51064
llvm-svn: 340350
Nico Weber [Tue, 21 Aug 2018 22:19:55 +0000 (22:19 +0000)]
Eliminate instances of `EmitScalarExpr(E->getArg(n))` in EmitX86BuiltinExpr().
EmitX86BuiltinExpr() emits all args into Ops at the beginning, so don't do that
work again.
This changes behavior: If e.g. ++a was passed as an arg, we incremented a twice
previously. This change fixes that bug.
https://reviews.llvm.org/D50979
llvm-svn: 340348
Kuba Mracek [Tue, 21 Aug 2018 22:03:28 +0000 (22:03 +0000)]
Fixup for r340342: Avoid Block_release'ing the block since we're no longer making a copy.
rdar://problem/
42242579
llvm-svn: 340347
Tom Stellard [Tue, 21 Aug 2018 21:48:43 +0000 (21:48 +0000)]
MachineScheduler: Refactor setPolicy() to limit computing remaining latency
Summary:
Computing the remaining latency can be very expensive especially
on graphs of N nodes where the number of edges approaches N^2.
This reduces the compile time of a pathological case with the
AMDGPU backend from ~7.5 seconds to ~3 seconds. This test case has
a basic block with 2655 stores, each with somewhere between 500
and 1500 successors and predecessors.
Reviewers: atrick, MatzeB, airlied, mareko
Reviewed By: mareko
Subscribers: tpr, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D50486
llvm-svn: 340346
Philip Reames [Tue, 21 Aug 2018 21:27:26 +0000 (21:27 +0000)]
[LICM] Fix a test so it actualy checks what was meant [NFC]
llvm-svn: 340344
Scott Linder [Tue, 21 Aug 2018 21:24:31 +0000 (21:24 +0000)]
[AMDGPU] Consider loads from flat addrspace to be potentially divergent
In general we can't assume flat loads are uniform, and cases where we can prove
they are should be handled through infer-address-spaces.
Differential Revision: https://reviews.llvm.org/D50991
llvm-svn: 340343
Kuba Mracek [Tue, 21 Aug 2018 21:24:22 +0000 (21:24 +0000)]
[tsan] Avoid calling Block_copy in the "sync" GCD interceptors
The synchronous dispatch functions in GCD (dispatch_sync, dispatch_barrier_sync), don't make a copy of the passed block. To maintain binary compatibility, we should avoid doing that as well in TSan, as there's no reason to do that. The synchronous dispatch functions will not return before the block is actually executed.
rdar://problem/
42242579
Differential Revision: https://reviews.llvm.org/D50920
llvm-svn: 340342
Zachary Turner [Tue, 21 Aug 2018 21:23:49 +0000 (21:23 +0000)]
[MS Demangler] Fix a few more edge cases.
I found these by running llvm-undname over a couple hundred
megabytes of object files generated as part of building chromium.
The issues fixed in this patch are:
1) decltype-auto return types.
2) Indirect vtables (e.g. const A::`vftable'{for `B'})
3) Pointers, references, and rvalue-references to member pointers.
I have exactly one remaining symbol out of a few hundred MB of object
files that produces a name we can't demangle, and it's related to
back-referencing.
llvm-svn: 340341
Zachary Turner [Tue, 21 Aug 2018 21:23:29 +0000 (21:23 +0000)]
Print "invalid mangled name" when we can't demangle something.
llvm-svn: 340340
Heejin Ahn [Tue, 21 Aug 2018 21:23:07 +0000 (21:23 +0000)]
[WebAssembly] Restore __stack_pointer after catch instructions
Summary:
After the stack is unwound due to a thrown exception, the
`__stack_pointer` global can point to an invalid address. This inserts
instructions that restore `__stack_pointer` global.
Reviewers: jgravelle-google, dschuff
Subscribers: mgorny, sbc100, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D50980
llvm-svn: 340339
Anna Thomas [Tue, 21 Aug 2018 21:12:02 +0000 (21:12 +0000)]
NFC: update the test comments in LV test about early exit loops
llvm-svn: 340337
Thomas Lively [Tue, 21 Aug 2018 21:03:18 +0000 (21:03 +0000)]
[WebAssembly] v128.const
Summary:
This CL implements v128.const for each vector type. New operand types
are added to ensure the vector contents can be serialized without LEB
encoding. Tests are added for instruction selection, encoding,
assembly and disassembly.
Reviewers: aheejin, dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D50873
llvm-svn: 340336
Fangrui Song [Tue, 21 Aug 2018 21:00:54 +0000 (21:00 +0000)]
[docs][gold] Fix a typo
llvm-svn: 340335
Martin Storsjo [Tue, 21 Aug 2018 20:41:17 +0000 (20:41 +0000)]
[CodeGen] Implicitly set stackrealign on the main function, if custom stack alignment is used
If using a custom stack alignment, one is expected to make sure
that all callers provide such alignment, or realign the stack in
all entry points (and callbacks).
Despite this, the compiler can assume that the main function will
need realignment in these cases, since the startup routines calling
the main function most probably won't provide the custom alignment.
This matches what GCC does in similar cases; if compiling with
-mincoming-stack-boundary=X -mpreferred-stack-boundary=X, GCC normally
assumes such alignment on entry to a function, but specifically for
the main function still does realignment.
Differential Revision: https://reviews.llvm.org/D51026
llvm-svn: 340334
Marcello Maggioni [Tue, 21 Aug 2018 20:30:14 +0000 (20:30 +0000)]
[LICM] Refactor some AliasSetTracker code to get rid of new/deletes. NFC
Differential Revision: https://reviews.llvm.org/D51024
llvm-svn: 340333
Florian Hahn [Tue, 21 Aug 2018 20:07:46 +0000 (20:07 +0000)]
[CodeExtractor] Use 'normal destination' BB as insert point to store invoke results.
Currently CodeExtractor tries to use the next node after an invoke to
place the store for the result of the invoke, if it is an out parameter
of the region. This fails, as the invoke terminates the current BB.
In that case, we can place the store in the 'normal destination' BB, as
the result will only be available in that case.
Reviewers: davidxl, davide, efriedma
Reviewed By: davidxl
Differential Revision: https://reviews.llvm.org/D51037
llvm-svn: 340331
Heejin Ahn [Tue, 21 Aug 2018 20:04:42 +0000 (20:04 +0000)]
[WebAssembly] Don't make wasm cleanuppads into funclet entries
Summary:
Catchpads and cleanuppads are not funclet entries; they are only EH
scope entries. We already dont't set `isEHFuncletEntry` for catchpads.
This patch does the same thing for cleanuppads.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D50654
llvm-svn: 340330
Heejin Ahn [Tue, 21 Aug 2018 19:52:19 +0000 (19:52 +0000)]
[WebAssembly] Change writeSPToMemory to writeSPToGlobal (NFC)
Summary: SP is now a __stack_pointer global and not a memory address anymore.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51046
llvm-svn: 340328
Bjorn Pettersson [Tue, 21 Aug 2018 19:47:32 +0000 (19:47 +0000)]
[RegisterCoalescer] Use substPhysReg in reMaterializeTrivialDef
Summary:
When RegisterCoalescer::reMaterializeTrivialDef is substituting
a register use in a DBG_VALUE instruction, and the old register
is a subreg, and the new register is a physical register,
then we need to use substPhysReg in order to extract the correct
subreg.
Reviewers: wmi, aprantl
Reviewed By: wmi
Subscribers: hiraditya, MatzeB, qcolombet, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D50844
llvm-svn: 340326
Heejin Ahn [Tue, 21 Aug 2018 19:44:11 +0000 (19:44 +0000)]
[WebAssembly] Add isEHScopeReturn instruction property
Summary:
So far, `isReturn` property is used to mean both a return instruction
from a functon and the end of an EH scope, a scope that starts with a EH
scope entry BB and ends with a catchret or a cleanupret instruction.
Because WinEH uses funclets, all EH-scope-ending instructions are also
real return instruction from a function. But for wasm, they only serve
as the end marker of an EH scope but not a return instruction that
exits a function. This mismatch caused incorrect prolog and epilog
generation in wasm EH scopes. This patch fixes this.
This patch is in the same vein with rL333045, which splits
`MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and
`isEHScopeEntry`.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D50653
llvm-svn: 340325
Simon Pilgrim [Tue, 21 Aug 2018 19:29:39 +0000 (19:29 +0000)]
Fix Wdocumentation warning. NFCI.
llvm-svn: 340324
Craig Topper [Tue, 21 Aug 2018 19:17:00 +0000 (19:17 +0000)]
[InstCombine] Pull simple checks above a more complicated one. NFCI
I'm assuming its easier to make sure the RHS of an XOR is all ones than it is to check for the many select patterns we have. So lets check that first. Same with the one use check.
llvm-svn: 340321
Florian Hahn [Tue, 21 Aug 2018 19:11:27 +0000 (19:11 +0000)]
[GVN] Assign new value number to calls reading memory, if there is no MemDep info.
Currently we assign the same value number to two calls reading the same
memory location if we do not have MemoryDependence info. Without MemDep
Info we cannot guarantee that there is no store between the two calls, so we
have to assign a new number to the second call.
It also adds a new option EnableMemDep to enable/disable running
MemoryDependenceAnalysis and also renamed NoLoads to NoMemDepAnalysis to
be more explicit what it does. As it also impacts calls that read memory,
NoLoads is a bit confusing.
Reviewers: efriedma, sebpop, john.brawn, wmi
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D50893
llvm-svn: 340319
Krzysztof Parzyszek [Tue, 21 Aug 2018 19:01:26 +0000 (19:01 +0000)]
[RegisterCoalscer] Manually remove leftover segments when commuting def
In removeCopyByCommutingDef, segments from the source live range are
copied into (and merged with) the segments of the target live range.
This is performed for all subranges of the source interval. It can
happen that there will be subranges of the target interval that had
no corresponding subranges in the source interval, and in such cases
these subrages will not be updated. Since the copy being coalesced
is about to be removed, these ranges need to be updated by removing
the segments that are started by the copy.
llvm-svn: 340318
Benjamin Kramer [Tue, 21 Aug 2018 18:44:25 +0000 (18:44 +0000)]
[NVPTX] Remove ftz variants of cvt with rounding mode
These do not exist in ptxas, it refuses to compile them.
Differential Revision: https://reviews.llvm.org/D51042
llvm-svn: 340317
Matt Davis [Tue, 21 Aug 2018 18:39:20 +0000 (18:39 +0000)]
[llvm-mca] Remove unused decl. NFC.
llvm-svn: 340316
Eric Christopher [Tue, 21 Aug 2018 18:35:08 +0000 (18:35 +0000)]
Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction" due to it causing a compiler crash on valid.
This reverts commit r340016, testcase forthcoming.
llvm-svn: 340315
Andrea Di Biagio [Tue, 21 Aug 2018 18:20:16 +0000 (18:20 +0000)]
[llvm-mca] Add the ability to customize the instruction selection strategy in the Scheduler.
The constructor of Scheduler now accepts a SchedulerStrategy object, which is
used internally by method Scheduler::select() to drive the instruction selection
process.
The goal of this patch is to enable the definition of custom selection
strategies while reusing the same algorithms implemented by class Scheduler.
The motivation is that, on some targets, the default strategy may not well
approximate the selection logic in the hardware schedulers.
This patch also adds the ability to pass a ResourceManager object to the
constructor of Scheduler. This gives a bit more flexibility to the design, and
potentially it allows to expose processor resources to SchedulerStrategy
objects.
Differential Revision: https://reviews.llvm.org/D51051
llvm-svn: 340314
Simon Pilgrim [Tue, 21 Aug 2018 18:02:28 +0000 (18:02 +0000)]
[X86][SSE] Add non-uniform udiv test that is mostly divide by 1.
The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this......
llvm-svn: 340313
Philip Reames [Tue, 21 Aug 2018 17:59:11 +0000 (17:59 +0000)]
[AST] Remove notion of volatile from alias sets [NFCI]
Volatility is not an aliasing property. We used to model volatile as if it had extremely conservative aliasing implications, but that hasn't been true for several years now. So, it doesn't make sense to be in AliasSet.
It also turns out the code is entirely a noop. Outside of the AST code to update it, there was only one user: load store promotion in LICM. L/S promotion doesn't need the check since it walks all the users of the address anyway. It already checks each load or store via !isUnordered which causes us to bail for volatile accesses. (Look at the lines immediately following the two remove asserts.)
There is the possibility of some small compile time impact here, but the only case which will get noticeably slower is a loop with a large number of loads and stores to the same address where only the last one we inspect is volatile. This is sufficiently rare it's not worth optimizing for..
llvm-svn: 340312
Erik Pilkington [Tue, 21 Aug 2018 17:50:10 +0000 (17:50 +0000)]
Address Aaron Ballman's post-commit review comments from r340306, NFC
llvm-svn: 340311
Yury Delendik [Tue, 21 Aug 2018 17:48:28 +0000 (17:48 +0000)]
Update DBG_VALUE register operand during LiveInterval operations
Summary:
Handling of DBG_VALUE in ConnectedVNInfoEqClasses::Distribute() was fixed in
PR16110. However DBG_VALUE register operands are not getting updated. This
patch properly resolves the value location.
Reviewers: MatzeB, vsk
Reviewed By: MatzeB
Subscribers: kparzysz, thegameg, vsk, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D48994
llvm-svn: 340310
Aditya Nandakumar [Tue, 21 Aug 2018 17:30:31 +0000 (17:30 +0000)]
Revert "Revert rr340111 "[GISel]: Add Legalization/lowering code for bit counting operations""
This reverts commit
d1341152d91398e9a882ba2ee924147ea2f9b589.
This patch originally made use of Nested MachineIRBuilder buildInstr
calls, and since order of argument processing is not well defined, the
instructions were built slightly in a different order (still correct).
I've removed the nested buildInstr calls to have a defined order now.
Patch was tested by Mikael.
llvm-svn: 340309
Vlad Tsyrklevich [Tue, 21 Aug 2018 17:29:01 +0000 (17:29 +0000)]
SafeStack: Use correct unsafe stack sizes
Summary:
When deallocating thread stacks, we use one thread's unsafe stack size
to deallocate another thread's unsafe stack; however, the two sizes may
differ. Record an unsafe stack's size in the thread stack linked list.
Reviewers: pcc, eugenis
Reviewed By: eugenis
Subscribers: delcypher, llvm-commits, #sanitizers, kcc
Differential Revision: https://reviews.llvm.org/D51016
llvm-svn: 340308
Simon Pilgrim [Tue, 21 Aug 2018 17:27:03 +0000 (17:27 +0000)]
[X86][SSE] Lower vXi8 general shifts to SSE shifts directly. NFCI.
Most of these shifts are extended to vXi16 so we don't gain anything from forcing another round of generic shift lowering - we know these extended cases are legal constant splat shifts.
llvm-svn: 340307
Erik Pilkington [Tue, 21 Aug 2018 17:24:06 +0000 (17:24 +0000)]
Add a new flag and attributes to control static destructor registration
This commit adds the flag -fno-c++-static-destructors and the attributes
[[clang::no_destroy]] and [[clang::always_destroy]]. no_destroy specifies that a
specific static or thread duration variable shouldn't have it's destructor
registered, and is the default in -fno-c++-static-destructors mode.
always_destroy is the opposite, and is the default in -fc++-static-destructors
mode.
A variable whose destructor is disabled (either because of
-fno-c++-static-destructors or [[clang::no_destroy]]) doesn't count as a use of
the destructor, so we don't do any access checking or mark it referenced. We
also don't emit -Wexit-time-destructors for these variables.
rdar://
21734598
Differential revision: https://reviews.llvm.org/D50994
llvm-svn: 340306
Peter Collingbourne [Tue, 21 Aug 2018 17:18:18 +0000 (17:18 +0000)]
llvm-readobj: Simplify. NFCI.
llvm-svn: 340305
Raphael Isemann [Tue, 21 Aug 2018 17:15:57 +0000 (17:15 +0000)]
[ASTImporter] Add test for CXXNoexceptExpr
Reviewers: a.sidorin, a_sidorin
Reviewed By: a_sidorin
Subscribers: a_sidorin, hiraditya, martong, cfe-commits
Differential Revision: https://reviews.llvm.org/D50737
llvm-svn: 340304
Craig Topper [Tue, 21 Aug 2018 17:15:33 +0000 (17:15 +0000)]
[BypassSlowDivision] Teach bypass slow division not to interfere with div by constant where constants have been constant hoisted, but not moved from their basic block
DAGCombiner doesn't pay attention to whether constants are opaque before doing the div by constant optimization. So BypassSlowDivision shouldn't introduce control flow that would make DAGCombiner unable to see an opaque constant. This can occur when a div and rem of the same constant are used in the same basic block. it will be hoisted, but not leave the block.
Longer term we probably need to look into the X86 immediate cost model used by constant hoisting and maybe not mark div/rem immediates for hoisting at all.
This fixes the case from PR38649.
Differential Revision: https://reviews.llvm.org/D51000
llvm-svn: 340303
Simon Pilgrim [Tue, 21 Aug 2018 17:05:07 +0000 (17:05 +0000)]
[X86][SSE] Lower v8i16 general shifts to SSE shifts directly. NFCI.
We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts.
llvm-svn: 340302
Erik Pilkington [Tue, 21 Aug 2018 16:47:04 +0000 (16:47 +0000)]
[Parser] Support alternative operator token keyword args in Objective-C++
rdar://
30741878
Differential revision: https://reviews.llvm.org/D50527
llvm-svn: 340301
Simon Pilgrim [Tue, 21 Aug 2018 16:46:48 +0000 (16:46 +0000)]
[X86][SSE] Lower directly to SSE shifts in the BLEND(SHIFT, SHIFT) combine. NFCI.
We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts.
llvm-svn: 340300
Raphael Isemann [Tue, 21 Aug 2018 16:36:49 +0000 (16:36 +0000)]
[ASTImporter] Add test for CXXForRangeStmt
Reviewers: a.sidorin, martong
Reviewed By: martong
Subscribers: rnkovacs, martong, cfe-commits
Differential Revision: https://reviews.llvm.org/D51001
llvm-svn: 340297
Matt Arsenault [Tue, 21 Aug 2018 16:24:56 +0000 (16:24 +0000)]
Try to fix bot build failure
llvm-svn: 340296
Farhana Aleen [Tue, 21 Aug 2018 16:21:15 +0000 (16:21 +0000)]
[AMDGPU] Support idot2 pattern.
Summary: Transform add (mul ((i32)S0.x, (i32)S1.x),
add( mul ((i32)S0.y, (i32)S1.y), (i32)S3) => i/udot2((v2i16)S0, (v2i16)S1, (i32)S3)
Author: FarhanaAleen
Reviewed By: arsenm
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D50024
llvm-svn: 340295
Adrian Prantl [Tue, 21 Aug 2018 16:13:37 +0000 (16:13 +0000)]
lldbtest.py: Unconditionally set the clang module cache path.
This should fix the errors observable on the new lldb-cmake bot.
llvm-svn: 340293
Matt Arsenault [Tue, 21 Aug 2018 16:13:29 +0000 (16:13 +0000)]
AMDGPU: Move target code into TargetParser
llvm-svn: 340292
Matt Arsenault [Tue, 21 Aug 2018 16:13:01 +0000 (16:13 +0000)]
AMDGPU: Partially move target handling code from clang to TargetParser
A future change in clang necessitates access of this information
from the driver, so move this into a common place.
Try to mimic something resembling the API the other targets are
using here.
One thing I'm uncertain about is how to split amdgcn and r600
handling. Here I've mostly duplicated the functions for each,
while keeping the same enums. I think this is a bit awkward
for the features which don't matter for amdgcn.
It's also a bit messy that this isn't a complete set of
subtarget features. This is just the minimum set needed
for the driver code. For example building the list of
subtarget feature names is still in clang.
llvm-svn: 340291
Simon Pilgrim [Tue, 21 Aug 2018 15:57:33 +0000 (15:57 +0000)]
[X86][SSE] Add helper function to convert to/between the SSE vector shift opcodes. NFCI.
Also remove some more getOpcode calls from LowerShift when we already have Opc.
llvm-svn: 340290
Louis Dionne [Tue, 21 Aug 2018 15:54:24 +0000 (15:54 +0000)]
[clang][NFC] Fix typo in the name of a note
Summary:
r306722 introduced a new note called note_silence_unligned_allocation_unavailable
where I believe what was meant is note_silence_aligned_allocation_unavailable.
Reviewers: ahatanak
Subscribers: dexonsmith, cfe-commits
Differential Revision: https://reviews.llvm.org/D51043
llvm-svn: 340288
Daniel Sanders [Tue, 21 Aug 2018 15:47:25 +0000 (15:47 +0000)]
[aarch64][mc] Don't lookup symbols when there is no symbol lookup callback
Summary: When run under llvm-mc-disassemble-fuzzer, there is no symbol lookup callback so tryAddingSymbolicOperand() must fail gracefully instead of crashing
Reviewers: aemerson, javed.absar
Reviewed By: aemerson
Subscribers: lhames, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D51005
llvm-svn: 340287
Adrian Prantl [Tue, 21 Aug 2018 15:46:15 +0000 (15:46 +0000)]
Makefile.rules: Use an absolute path to the module cache directory.
This change is NFC, but it makes it more obvious in log files what happened.
llvm-svn: 340286
Nicola Zaghen [Tue, 21 Aug 2018 15:27:32 +0000 (15:27 +0000)]
[InstCombine] Add new tests for icmp ugt/ult (add nuw X, C2), C
Differential Revision: https://reviews.llvm.org/D51040
llvm-svn: 340284
Simon Pilgrim [Tue, 21 Aug 2018 15:21:45 +0000 (15:21 +0000)]
[X86] Add SSE2 and XOP udiv combine tests
llvm-svn: 340282
Zaara Syeda [Tue, 21 Aug 2018 15:13:53 +0000 (15:13 +0000)]
[PPC64] Add TLS initial exec to local exec relaxation
This patch adds the target call back relaxTlsIeToLe to support TLS relaxation
from initial exec to local exec model.
Differential Revision: https://reviews.llvm.org/D48091
llvm-svn: 340281
Kristof Umann [Tue, 21 Aug 2018 15:09:22 +0000 (15:09 +0000)]
[analyzer] Correctly marked a virtual function 'override'
llvm-svn: 340280
Sanjay Patel [Tue, 21 Aug 2018 14:45:13 +0000 (14:45 +0000)]
[InstSimplify] use isKnownNeverNaN to fold more fcmp ord/uno
Remove duplicate tests from InstCombine that were added with
D50582. I left negative tests there to verify that nothing
in InstCombine tries to go overboard. If isKnownNeverNaN is
improved to handle the FP binops or other cases, we should
have coverage under InstSimplify, so we could remove more
duplicate tests from InstCombine at that time.
llvm-svn: 340279
Anna Thomas [Tue, 21 Aug 2018 14:40:27 +0000 (14:40 +0000)]
[LV] Vectorize loops where non-phi instructions used outside loop
Summary:
Follow up change to rL339703, where we now vectorize loops with non-phi
instructions used outside the loop. Note that the cyclic dependency
identification occurs when identifying reduction/induction vars.
We also need to identify that we do not allow users where the PSCEV information
within and outside the loop are different. This was the fix added in rL307837
for PR33706.
Reviewers: Ayal, mkuper, fhahn
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D50778
llvm-svn: 340278
Balazs Keri [Tue, 21 Aug 2018 14:32:21 +0000 (14:32 +0000)]
[ASTImporter] Adding some friend function related unittests.
Reviewers: a.sidorin, a_sidorin
Reviewed By: a_sidorin
Subscribers: a_sidorin, martong, cfe-commits
Differential Revision: https://reviews.llvm.org/D49798
llvm-svn: 340277
Sanjay Patel [Tue, 21 Aug 2018 13:33:13 +0000 (13:33 +0000)]
[InstSimplify] add tests for FP uno/ord with nnan; NFC
This is a slight modification of the tests from D50582;
change half of the predicates to 'uno' so we have coverage
for that side too. All of the positive tests can fold to a
constant (true/false), so that should happen in instsimplify.
llvm-svn: 340276
Anna Thomas [Tue, 21 Aug 2018 13:02:09 +0000 (13:02 +0000)]
NFC: Add loop vectorizer tests showing various control flow within loop that skip iterations
llvm-svn: 340275
Andrea Di Biagio [Tue, 21 Aug 2018 13:00:44 +0000 (13:00 +0000)]
[llvm-mca] Replace use of llvm::any_of with std::any_of.
This should unbreak the buildbots.
llvm-svn: 340274
Andrea Di Biagio [Tue, 21 Aug 2018 12:40:15 +0000 (12:40 +0000)]
[llvm-mca] Add method cycleEvent() to class Scheduler. NFCI
The goal of this patch is to simplify the Scheduler's interface in preparation
for D50929.
Some methods in the Scheduler's interface should not be exposed to external
users, since their presence makes it hard to both understand, and extend the
Scheduler's interface.
This patch removes the following two methods from the public Scheduler's API:
- reclaimSimulatedResources()
- updatePendingQueue()
Their logic has been migrated to a new method named 'cycleEvent()'.
Methods 'updateIssuedSet()' and 'promoteToReadySet()' still exist. However,
they are now private members of class Scheduler.
This simplifies the interaction with the Scheduler from the ExecuteStage.
llvm-svn: 340273
Kristof Umann [Tue, 21 Aug 2018 12:16:59 +0000 (12:16 +0000)]
[analyzer][UninitializedObjectChecker] Explicit namespace resolution for inherited data members
For the following example:
struct Base {
int x;
};
// In a different translation unit
struct Derived : public Base {
Derived() {}
};
For a call to Derived::Derived(), we'll receive a note that
this->x is uninitialized. Since x is not a direct field of Derived,
it could be a little confusing. This patch aims to fix this, as well
as the case when the derived object has a field that has the name as
an inherited uninitialized data member:
struct Base {
int x; // note: uninitialized field 'this->Base::x'
};
struct Derived : public Base {
int x = 5;
Derived() {}
};
Differential Revision: https://reviews.llvm.org/D50905
llvm-svn: 340272
Hiroshi Inoue [Tue, 21 Aug 2018 11:41:41 +0000 (11:41 +0000)]
Add missing library dependency to fix build break after rC340247
llvm-svn: 340271
Tim Renouf [Tue, 21 Aug 2018 11:08:12 +0000 (11:08 +0000)]
[AMDGPU] Allow int types for MUBUF vdata
Summary:
Previously the new llvm.amdgcn.raw/struct.buffer.load/store intrinsics
only allowed float types for the data to be loaded or stored, which
sometimes meant the frontend needed to generate a bitcast. In this, the
new intrinsics copied the old buffer intrinsics.
This commit extends the new intrinsics to allow int types as well.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D50315
Change-Id: I8202af2d036455553681dcbb3d7d32ae273f8f85
llvm-svn: 340270
Tim Renouf [Tue, 21 Aug 2018 11:07:10 +0000 (11:07 +0000)]
[AMDGPU] New buffer intrinsics
Summary:
This commit adds new intrinsics
llvm.amdgcn.raw.buffer.load
llvm.amdgcn.raw.buffer.load.format
llvm.amdgcn.raw.buffer.load.format.d16
llvm.amdgcn.struct.buffer.load
llvm.amdgcn.struct.buffer.load.format
llvm.amdgcn.struct.buffer.load.format.d16
llvm.amdgcn.raw.buffer.store
llvm.amdgcn.raw.buffer.store.format
llvm.amdgcn.raw.buffer.store.format.d16
llvm.amdgcn.struct.buffer.store
llvm.amdgcn.struct.buffer.store.format
llvm.amdgcn.struct.buffer.store.format.d16
llvm.amdgcn.raw.buffer.atomic.*
llvm.amdgcn.struct.buffer.atomic.*
with the following changes from the llvm.amdgcn.buffer.*
intrinsics:
* there are separate raw and struct versions: raw does not have an
index arg and sets idxen=0 in the instruction, and struct always sets
idxen=1 in the instruction even if the index is 0, to allow for the
fact that gfx9 does bounds checking differently depending on whether
idxen is set;
* there is a combined cachepolicy arg (glc+slc)
* there are now only two offset args: one for the offset that is
included in bounds checking and swizzling, to be split between the
instruction's voffset and immoffset fields, and one for the offset
that is excluded from bounds checking and swizzling, to go into the
instruction's soffset field.
The AMDISD::BUFFER_* SD nodes always have an index operand, all three
offset operands, combined cachepolicy operand, and an extra idxen
operand.
The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D50306
Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205
llvm-svn: 340269
Tim Renouf [Tue, 21 Aug 2018 11:06:05 +0000 (11:06 +0000)]
[AMDGPU] New tbuffer intrinsics
Summary:
This commit adds new intrinsics
llvm.amdgcn.raw.tbuffer.load
llvm.amdgcn.struct.tbuffer.load
llvm.amdgcn.raw.tbuffer.store
llvm.amdgcn.struct.tbuffer.store
with the following changes from the llvm.amdgcn.tbuffer.* intrinsics:
* there are separate raw and struct versions: raw does not have an index
arg and sets idxen=0 in the instruction, and struct always sets
idxen=1 in the instruction even if the index is 0, to allow for the
fact that gfx9 does bounds checking differently depending on whether
idxen is set;
* there is a combined format arg (dfmt+nfmt)
* there is a combined cachepolicy arg (glc+slc)
* there are now only two offset args: one for the offset that is
included in bounds checking and swizzling, to be split between the
instruction's voffset and immoffset fields, and one for the offset
that is excluded from bounds checking and swizzling, to go into the
instruction's soffset field.
The AMDISD::TBUFFER_* SD nodes always have an index operand, all three
offset operands, combined format operand, combined cachepolicy operand,
and an extra idxen operand.
The tbuffer pseudo- and real instructions now also have a combined
format operand.
The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store
intrinsics continue to work.
V2: Separate raw and struct intrinsics.
V3: Moved extract_glc and extract_slc defs to a more sensible place.
V4: Rebased on D49995.
V5: Only two separate offset args instead of three.
V6: Pseudo- and real instructions have joint format operand.
V7: Restored optionality of dfmt and nfmt in assembler.
V8: Addressed minor review comments.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D49026
Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4
llvm-svn: 340268
Bjorn Pettersson [Tue, 21 Aug 2018 10:59:50 +0000 (10:59 +0000)]
Change how finalizeBundle selects debug location for the BUNDLE instruction
Summary:
Previously a BUNDLE instruction inherited the DebugLoc from the
first instruction in the bundle, even if that DebugLoc had no
DILocation. With this commit this is changed into selecting the
first DebugLoc that has a DILocation, by searching among the
bundled instructions.
The idea is to reduce amount of bundles that are lacking
debug locations.
Reviewers: #debug-info, JDevlieghere
Reviewed By: JDevlieghere
Subscribers: JDevlieghere, mattd, llvm-commits
Differential Revision: https://reviews.llvm.org/D50639
llvm-svn: 340267
Kristof Umann [Tue, 21 Aug 2018 10:47:19 +0000 (10:47 +0000)]
[analyzer][UninitializedObjectChecker] Added documentation to the checker list
Differential Revision: https://reviews.llvm.org/D50904
llvm-svn: 340266
Kristof Umann [Tue, 21 Aug 2018 10:45:21 +0000 (10:45 +0000)]
[analyzer][UninitializedObjectChecker] Refactoring p6.: Move dereferencing to a function
Now that it has it's own file, it makes little sense for
isPointerOrReferenceUninit to be this large, so I moved
dereferencing to a separate function.
Differential Revision: https://reviews.llvm.org/D50509
llvm-svn: 340265
Simon Pilgrim [Tue, 21 Aug 2018 10:44:06 +0000 (10:44 +0000)]
[X86] Add SSE2 sdiv combine tests
llvm-svn: 340264
Kirill Bobyrev [Tue, 21 Aug 2018 10:40:19 +0000 (10:40 +0000)]
[clangd] NFC: Fix broken build
llvm-svn: 340263
Kirill Bobyrev [Tue, 21 Aug 2018 10:32:27 +0000 (10:32 +0000)]
[clangd] Allow using experimental Dex index
This patch adds hidden Clangd flag ("use-dex-index") which replaces
(currently) default `MemIndex` with `DexIndex` for the static index.
Reviewed by: ioeric
Differential Revision: https://reviews.llvm.org/D50897
llvm-svn: 340262
Sam Parker [Tue, 21 Aug 2018 10:26:59 +0000 (10:26 +0000)]
[DAGCombiner] Reduce load widths of shifted masks
During combining, ReduceLoadWdith is used to combine AND nodes that
mask loads into narrow loads. This patch allows the mask to be a
shifted constant. This results in a narrow load which is then left
shifted to compensate for the new offset.
Differential Revision: https://reviews.llvm.org/D50432
llvm-svn: 340261
Simon Pilgrim [Tue, 21 Aug 2018 10:20:36 +0000 (10:20 +0000)]
[TargetLowering] Add BuildSDiv support for division by one or negone.
This reduces most of the sdiv stages (the MULHS, shifts etc.) to just zero/identity values and use the numerator scale factor to multiply by +1/-1.
llvm-svn: 340260
George Rimar [Tue, 21 Aug 2018 08:27:23 +0000 (08:27 +0000)]
[LLD][ELF] - Fix BB after r340257.
Renamed Filecheck->FileCheck.
llvm-svn: 340259
Petar Jovanovic [Tue, 21 Aug 2018 08:15:56 +0000 (08:15 +0000)]
[MIPS GlobalISel] Select bitwise instructions
Select bitwise instructions for i32.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D50183
llvm-svn: 340258
George Rimar [Tue, 21 Aug 2018 08:13:06 +0000 (08:13 +0000)]
[LLD][ELF] - Check the architecture of lazy objects earlier.
Our code in LazyObjFile::parse() has an ELFT switch and
adds a lazy object by its ELFT kind.
Though it might be possible to add a file using a different
architecture and make LLD to silently accept it (if the file
is empty or contains only week symbols). That itself, not a
huge issue perhaps (because the error would be reported later
if the file is fetched), but still does not look clean and correct.
It is possible to report an error earlier and clean up the
code. That is what the patch does.
Ideally, we might want to reuse isCompatible from SymbolTable.cpp,
but it is static and accepts a file as an argument, what is not
convenient. Since such a situation should be rare, I think it
should be OK to go with the way chosen in this patch.
Differential revision: https://reviews.llvm.org/D50899
llvm-svn: 340257
Max Kazantsev [Tue, 21 Aug 2018 08:11:31 +0000 (08:11 +0000)]
[LICM] Hoist guards with invariant conditions
This patch teaches LICM to hoist guards from the loop if they are guaranteed to execute and
if there are no side effects that could prevent that.
Differential Revision: https://reviews.llvm.org/D50501
Reviewed By: reames
llvm-svn: 340256
Bjorn Pettersson [Tue, 21 Aug 2018 07:49:05 +0000 (07:49 +0000)]
[RegisterCoalescer] Do not assert when trying to remat dead values
Summary:
RegisterCoalescer::reMaterializeTrivialDef used to assert that
the input register was live in. But as shown by the new
coalesce-dead-lanes.mir test case that seems to be a valid
scenario. We now return false instead of the assert, simply
avoiding to remat the dead def.
Normally a COPY of an undef value is eliminated by
eliminateUndefCopy(). Although we only do that when the
destination isn't a physical register. So the situation
above should be limited to the case when we copy an undef
value to a physical register.
Reviewers: kparzysz, wmi, tpr
Reviewed By: kparzysz
Subscribers: MatzeB, qcolombet, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D50842
llvm-svn: 340255
Max Kazantsev [Tue, 21 Aug 2018 07:37:02 +0000 (07:37 +0000)]
[NFC] Add some LICM tests
llvm-svn: 340254
Fangrui Song [Tue, 21 Aug 2018 07:35:23 +0000 (07:35 +0000)]
[docs] Add --print-icf-sections to ld.lld.1
llvm-svn: 340253
Kirill Bobyrev [Tue, 21 Aug 2018 07:23:45 +0000 (07:23 +0000)]
[llvm] NFC: Fix assert condition and suppress warning
As mentioned by andreadb, assert condition is wrong and causes
GCC warning.
Related Revision: https://reviews.llvm.org/D50839
llvm-svn: 340252
Mikael Holmen [Tue, 21 Aug 2018 07:22:45 +0000 (07:22 +0000)]
Removed unused variable [NFC]
The compiler warned:
../tools/clang/lib/Sema/SemaType.cpp:6788:31: error: unused variable 'AT' [-Werror,-Wunused-variable]
if (const AttributedType *AT = S.getCallingConvAttributedType(type)) {
^
1 error generated.
llvm-svn: 340251
Max Kazantsev [Tue, 21 Aug 2018 07:15:06 +0000 (07:15 +0000)]
[NFC] Factor out predecessors collection into a separate method
It may be reused in a different piece of logic.
Differential Revision: https://reviews.llvm.org/D50890
Reviewed By: reames
llvm-svn: 340250
Serguei Katkov [Tue, 21 Aug 2018 04:27:07 +0000 (04:27 +0000)]
[IR Verifier] Do not allow bitcast of pointer to vector of pointers and vice versa.
LangRef for BitCast requires that
"The bit sizes of value and the destination type, ty2, must be identical".
Currently verifier allows BitCast of pointer to vector of pointers so that
the sizes are different.
This change fixes that.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: llvm-commits, wdng
Differential Revision: https://reviews.llvm.org/D50886
llvm-svn: 340249