Alyssa Rosenzweig [Sat, 24 Apr 2021 23:15:43 +0000 (19:15 -0400)]
asahi: Add tiling routines
For the 64x64 Morton order pattern we know how to use for textures and
framebuffers. (AGX also supports a framebuffer compression scheme. This
is not that.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 23:13:29 +0000 (19:13 -0400)]
asahi: Add command buffer decode helpers
Forked from Panfrost's pandecode. Like pandecode, most of the
heavylifting is generated with GenXML, so this is relatively simple.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 23:13:11 +0000 (19:13 -0400)]
asahi: Add (clean room) IOKit uABI header
This only builds on macOS (depends on IOKit), where it is required for
command buffer submission and tracing the Metal blob.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 23:10:10 +0000 (19:10 -0400)]
asahi: Add a GenXML fork
Via Panfrost via v3d via Intel. Sour dough!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 23:08:51 +0000 (19:08 -0400)]
asahi: Add allocation data structure
Something half-way between what IOKit (macOS) and DRM (Linux) want.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 23:08:14 +0000 (19:08 -0400)]
asahi: Add command buffer XML definitions
Formatted for GenXML. Incomplete and probably riddled with errors, but a
good start.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 23:07:59 +0000 (19:07 -0400)]
asahi: Add hexdump utility
Used in our decoder.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 21:41:19 +0000 (17:41 -0400)]
agx: Support bcsel
We're already using cmpsel in lots of places, pipe through the real
thing!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 20:24:17 +0000 (16:24 -0400)]
agx: Pack cmpsel
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 2 May 2021 13:36:09 +0000 (09:36 -0400)]
agx: Add b2i implementation
Another icmpsel variant.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 20:23:15 +0000 (16:23 -0400)]
agx: Implement b2f
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 20:23:01 +0000 (16:23 -0400)]
agx: Support 1-bit booleans
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 18 Apr 2021 19:16:04 +0000 (15:16 -0400)]
agx: Add min/max support
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 18:01:32 +0000 (14:01 -0400)]
agx: Pack texture ops
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 18:01:08 +0000 (14:01 -0400)]
agx: Emit texture ops
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 24 Apr 2021 18:00:55 +0000 (14:00 -0400)]
agx: Add agx_tex_dim helper
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 18 Apr 2021 00:43:32 +0000 (20:43 -0400)]
agx: Implement vertex_id
Preloaded to r5 in vertex shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 23:57:51 +0000 (19:57 -0400)]
agx: Lower load_attr to device memory accesses
This is pretty annoying but not as catastrophic as I feared... at least,
until we need to support indirect access, non-native formats, or instancing.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 22:09:41 +0000 (18:09 -0400)]
agx: Set flag on last st_vary instruction
Not sure what the point is but let's match the blob.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 20:55:45 +0000 (16:55 -0400)]
agx: Implement load_ubo/kernel_input
Lower to a read from global memory at a base address specified in a
sysval.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 20:59:51 +0000 (16:59 -0400)]
agx: Add sysval management helper
Will be used for lowering UBO loads, among other applications.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 20:57:01 +0000 (16:57 -0400)]
agx: Implement limited case of i2i16/i2i32 as iadd
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 15:38:00 +0000 (11:38 -0400)]
agx: Propagate immediates
8-bit integers can be inlined to immediates on integer ops. Likewise,
floats with simple representations can be converted to 8-bit minifloats
and inlined on float ops.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 15:13:32 +0000 (11:13 -0400)]
agx: Propagate fmov backwards as well
Primarily for fsat. Also folds conversions but this is more of an
accident, and it doesn't do so optimally (due to the f2f16/f2f32
orientation issue outlined in the pass comments).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 14:52:15 +0000 (10:52 -0400)]
agx: Add dead code eliminator
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 14:29:27 +0000 (10:29 -0400)]
agx: Add forward optimizing pass for fmov
Explain the ideas behind our SSA-based optimizer (inspired by ACO's,
thank you to Daniel Schuermann for discussing this with me in the
context of Bifrost), and implement the subset needed to propagate
abs/neg through.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 13:58:20 +0000 (09:58 -0400)]
agx: Add 32-bit bitwise shifts
Only ishr has an actual native instruction, the others are special cases
of the bitfield insertion/extraction ops.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 00:49:23 +0000 (20:49 -0400)]
agx: Add saturated integer add/subtract support
Just a flag on the regular iadd instruction.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 00:36:39 +0000 (20:36 -0400)]
agx: Add iadd/imad integer arithmetic
Lots of optimizations will be possible later on.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Fri, 16 Apr 2021 22:36:06 +0000 (18:36 -0400)]
agx: Add bitwise operations
This get translated to bitop with the corresponding truth table with
some builder syntax sugar.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Fri, 16 Apr 2021 22:02:24 +0000 (18:02 -0400)]
agx: Implement native int->float conversions
This time 8, 16, and 32-bit sources are supported natively, but not
64-bit.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Fri, 16 Apr 2021 21:55:49 +0000 (17:55 -0400)]
agx: Implement native float->int conversions
No 8-bit or 64-bit yet since those need lowerings.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Fri, 16 Apr 2021 18:55:39 +0000 (14:55 -0400)]
agx: Add minifloat tests
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Fri, 16 Apr 2021 03:30:33 +0000 (23:30 -0400)]
agx: Add 8-bit AGX minifloat routines
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Fri, 16 Apr 2021 02:51:47 +0000 (22:51 -0400)]
agx: Implement fsin/fcos
First, we lower to fsin_agx and some ALU in NIR. Then, we implement
fsin_agx with the underlying transcental ops.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Wed, 14 Apr 2021 19:28:13 +0000 (15:28 -0400)]
agx: Implement simple floating point ops
These are all direct translations of NIR->AIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Mon, 12 Apr 2021 03:45:35 +0000 (23:45 -0400)]
agx: Implement ld_vary
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Mon, 12 Apr 2021 03:00:35 +0000 (23:00 -0400)]
agx: Terminate programs with stop and traps
The function of stop is clear. The function of trap, let alone a whole
sled of them, is less so. Maybe a debugging feature for later.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 22:11:05 +0000 (18:11 -0400)]
agx: Add st_vary(_final) instruction packing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 21:01:20 +0000 (17:01 -0400)]
agx: Add packing for memory loads/stores
Encoding is dramatically different from ALU.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Mon, 12 Apr 2021 03:49:30 +0000 (23:49 -0400)]
agx: Add instruction packing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 20:01:47 +0000 (16:01 -0400)]
agx: Add a trivial register allocator
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:29:08 +0000 (15:29 -0400)]
agx: Add instruction printing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:19:49 +0000 (15:19 -0400)]
agx: Implement fragment_out
For a single colour render target.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:10:39 +0000 (15:10 -0400)]
agx: Implement vec2/vec3/vec4 ops
As p_combine, to un-stub emit_alu.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:09:36 +0000 (15:09 -0400)]
agx: Add agx_alu_src_index helper for emit_alu
Since we don't use abs/neg in NIR, this just needs to construct
p_extract ops to deal with swizzles.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:09:03 +0000 (15:09 -0400)]
agx: Implement direct st_vary
Indirection can come later, if at all..
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:08:44 +0000 (15:08 -0400)]
agx: Implement load_const as mov
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 15:26:00 +0000 (11:26 -0400)]
agx: Stub emit_intrinsic
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 15:05:52 +0000 (11:05 -0400)]
agx: Stub NIR instruction iteration
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 14:57:55 +0000 (10:57 -0400)]
agx: Stub control flow walking
From Bifrost. We'll need to diverge (no pun intended) due to exec_mask
handling specific to Apple.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 2 May 2021 13:44:15 +0000 (09:44 -0400)]
agx: Remap varyings to match AGX ABI
It's not clear if this is software or hardware defined, but until we
know more about linkage, let's match the blob. Fixes dEQP issues with
gl_PointSize.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 02:03:19 +0000 (22:03 -0400)]
agx: Stub NIR backend compiler
A fork of the Bifrost compiler, tailored to AGX. nir_register support is
removed, as I want to use an SSA-based allocator for AGX. (There are no
VLIW-like requirements and extremely limited vector semantics, so we can
use an ACO approach with ease.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Thu, 15 Apr 2021 23:08:26 +0000 (19:08 -0400)]
agx: Generate builder routines
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Thu, 15 Apr 2021 23:08:00 +0000 (19:08 -0400)]
agx: Generate runtime-accessible opcode table
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Thu, 15 Apr 2021 23:08:13 +0000 (19:08 -0400)]
agx: Generate opcode list
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Wed, 14 Apr 2021 20:50:23 +0000 (16:50 -0400)]
agx: Add opcode descriptions as Python
Pattern lifted from NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 00:17:21 +0000 (20:17 -0400)]
asahi: Stub command-line compiler for AGX G13B
Based on the Bifrost standalone compiler, which was based on Midgard's
standalone compiler, which was based on Freedreno's standalone compiler,
which was.....
It's like sour dough!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Fri, 16 Apr 2021 02:46:45 +0000 (22:46 -0400)]
nir: Add fsin_agx opcode
Used to split up the fsin/fcos lowering for AGX between NIR and the
backend, to permit algebraic optimizations without polluting NIR with
too many hardware details. The backend NIR lowering produces an
fmul/ffma of the input so we can optimize code like sin(2*x).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 2 May 2021 17:16:17 +0000 (13:16 -0400)]
util/bitset: Add BITSET_COUNT helper
Expressible as a prefix sum but that's a bit unnatural, so add a
convenience helper.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrants <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10581>
Lionel Landwerlin [Mon, 19 Oct 2020 07:12:43 +0000 (10:12 +0300)]
anv: implement VK_KHR_fragment_shading_rate
Available on Gen11+.
v2: Order shading rate in correct order (Samuel)
v3: Move CPS_STATE emission to genX_state.c
v4: Don't override various output structures (Jason)
v5: Rebase on top master (Lionel)
v6: Fix invalid VkPhysicalDeviceFragmentShadingRatePropertiesKHR
(min|max)FragmentShadingRateAttachmentTexelSize values (Ken)
Drop #endif comment
v7: Limit extension to Gfx11+ (Lionel)
Support conservative raster (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Jason Ekstrand [Fri, 5 Feb 2021 14:11:01 +0000 (08:11 -0600)]
intel/fs: Stop using brw_dp_read/write_desc in Gen7+ only code
Those helpers exist primarily to sort out some of the weirdness around
Gen4-6 dataport access. On Gen5 and earlier, everything was called
"dataport" and, instead of the SFID we have today there was a "target
cache" parameter in the descriptor. There are also some bits that moved
around on various gens depending on read vs. write. Starting with Gen6,
most things which target one of the data cache SFIDs should use
brw_dp_desc() instead.
v2: Drop backward comment (Ken)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Jason Ekstrand [Fri, 5 Feb 2021 14:09:47 +0000 (08:09 -0600)]
intel/eu: SVB writes only happen on Gen6
It's a Gen6 XFB thing. It's never used for anything else so there's no
point in having a target cache switch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 29 Oct 2020 13:17:16 +0000 (15:17 +0200)]
intel/compiler: add restrictions related to coarse pixel shading
v2: Update to BITSET_TEST()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Tue, 9 Feb 2021 11:20:17 +0000 (13:20 +0200)]
intel/compiler: add coarse pixel offset on Gfx12.5+
Gfx12.5 has a slightly different code path.
v2: Document the oddness
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 29 Oct 2020 13:10:59 +0000 (15:10 +0200)]
intel/compiler: add support for fragment coordinate with coarse pixels
v2: Drop new internal opcodes (Jason)
Simplify code (Jason)
v3: Add Z computation for coarse pixels
v4: Document things a little
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 29 Oct 2020 13:19:30 +0000 (15:19 +0200)]
intel/compiler: add support for fragment shading rate variable
v2: Drop old register type initializers (Jason)
Simplify instruction snippet (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 22 Oct 2020 10:23:06 +0000 (13:23 +0300)]
intel/compiler: handle coarse pixel in render target writes descriptors
v2: Use the new inst->ex_desc field (Jason)
v3: Drop CPS LoD compensation from sampler messages (Lionel)
v4: Drop useless uses_rate_shading (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 22 Oct 2020 10:25:33 +0000 (13:25 +0300)]
intel/compiler: use existing helpers to pull bits of descriptors
v2: Use new RT descriptor helper
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 4 Feb 2021 09:49:29 +0000 (11:49 +0200)]
intel/compiler: rework message descriptors for render targets
Render target message descriptors are slightly different from the
dataport ones. In particular the msg_type field is on bits 14:17 for
RT while bits 14:18 for DP.
v2: Drop unused send_commit_msg field in brw_fb_write_desc() (Ken)
v3: Rebase on top renaming (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Fri, 30 Oct 2020 15:41:02 +0000 (17:41 +0200)]
intel/compiler: make sure we keep the lowest dispatch limit
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Wed, 21 Oct 2020 12:26:06 +0000 (15:26 +0300)]
intel/decoder: decode CPS_STATE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Fri, 16 Oct 2020 13:11:53 +0000 (16:11 +0300)]
intel/genxml: Add coarse pixel shading instructions
v2: Add Gen12.5
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Wed, 21 Oct 2020 08:40:49 +0000 (11:40 +0300)]
intel/dev: printout correct subslice/dualsubslice name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Rob Clark [Sat, 1 May 2021 18:32:10 +0000 (11:32 -0700)]
freedreno: Fix TC last_fence optimization
Grabbing the fence value in fd_fence_repopulate() without waiting on
fd_submit_fence::ready doesn't work with async flushes, since we are
waiting for the first flush to complete (ie. we don't have the kernel-
side fence value yet). Just simplify it and make the "repopulated"
fence delagate to the original fence.
Fixes:
e9a9ac6f77f ("freedreno/drm: Async submit support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4726
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10567>
Rob Clark [Sat, 1 May 2021 17:57:40 +0000 (10:57 -0700)]
freedreno/drm: Initialize control->fence
Don't rely on getting a zero'd out buffer, we could hit the bo-cache.
Fixes:
7dabd624649 ("freedreno/drm: Userspace fences")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10567>
Vasily Khoruzhick [Sun, 2 May 2021 05:45:30 +0000 (22:45 -0700)]
lima: switch resource to linear layout if there's to many full updates
Overwriting entire resource multiple times indicates streaming and in this
case it's more efficient to use linear layout to avoid expensive linear->tiled
conversions.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10572>
Vinson Lee [Sat, 1 May 2021 20:08:51 +0000 (13:08 -0700)]
glx: Fix macOS build.
In file included from ../src/glx/apple/apple_glx_context.c:49:
../src/glx/glxclient.h:56:10: fatal error: 'loader.h' file not found
^~~~~~~~~~
Fixes:
1cb664c15cb3 ("glx: s/dri_message/glx_message/")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4702
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10568>
Bastian Beranek [Sat, 1 May 2021 07:52:01 +0000 (09:52 +0200)]
glx: Assign unique serial number to GLXBadFBConfig error
Since commit
f39fd3dce72 a new GLX error is issued in case context creation
fails. This broke wine on certain hardware: While wine installs an error handler
to ignore this kind of error, it does not function because it expects the
dpy->request serial number of the error to be incremented since the installation
of the handler.
Workaround this by artificially increasing the request number. This also
guarantees a unique serial number for the error.
Fixes:
f39fd3dce72eaef59ab39a23b75030ef9efc2a40
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3969
Signed-off-by: Bastian Beranek <bastian.beischer@rwth-aachen.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10565>
Ilia Mirkin [Thu, 25 Mar 2021 01:16:35 +0000 (21:16 -0400)]
nv50: add indirect compute support
There's no hardware support for anything indirect, so just read the
parameters out.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Sun, 21 Mar 2021 03:40:00 +0000 (23:40 -0400)]
nv50: add support for doing membars
This requires an address that's safe to read from.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Sat, 20 Mar 2021 00:10:24 +0000 (20:10 -0400)]
nv50: add remapping of buffers/images into unified space
This allows us to use up to 15 images or buffers (but not both). GL
supports the concept of combined resource maximums though.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Tue, 2 Mar 2021 05:18:07 +0000 (00:18 -0500)]
nv50: add compute invocations counter
This is a purely software counter alongside the other hardware counters
for ease of use and consistency. However we have to make room for it in
the allocated query space. Use this opportunity to make the nv50 queries
work like the nvc0 ones in terms of space allocation.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Tue, 2 Mar 2021 00:19:23 +0000 (19:19 -0500)]
nv50/ir: add lowering for shared atomics
This is best-effort for pre-nva0 ... works with a single invocation,
i.e. no locking.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Thu, 25 Feb 2021 03:23:48 +0000 (22:23 -0500)]
nv50/ir: add surface op lowering
This handles BUFQ, SUQ, as well as all the various texture types and
formats, driven by data supplied by the driver (and shader itself).
TODO:
- 2d linear surfaces
- format via key for writeonly
These will be included in a later change. ES3.1 doesn't require
writeonly, and it's very hard to generate a 2d linear surface.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Tue, 2 Mar 2021 23:54:37 +0000 (18:54 -0500)]
nv50: pass surface/buffer parameters to shader via aux buffer
These are needed to implement things like imageSize() as well as feed
data into lowering logic for various access types not handled by the
hardware.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Wed, 10 Mar 2021 04:59:31 +0000 (23:59 -0500)]
nv50/ir: optimize shift of 0 bits
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Wed, 3 Mar 2021 23:52:13 +0000 (18:52 -0500)]
nv50/ir: wipe any info about memory when seeing a locking op
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Thu, 25 Feb 2021 03:23:08 +0000 (22:23 -0500)]
nv50/ir: mark ATOM as having 3 arguments
Otherwise the final argument doesn't get emitted for CAS in the nv50
emitter.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Thu, 25 Feb 2021 03:17:40 +0000 (22:17 -0500)]
nv50/ir: "zero" register does not work with g[] memory
Evidence suggests that having it anywhere, even as a regular e.g. atom
argument, causes issues.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Mon, 12 Apr 2021 22:15:04 +0000 (18:15 -0400)]
nv50/ir: refine limitation on load/store loading offsets, include atomics
Note that shared memory loads can actually do offsets. The restrictions
vary by generation, this will be added in a later change.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Sun, 11 Apr 2021 21:54:32 +0000 (17:54 -0400)]
nv50/ir: offset accesses to shared memory
Ideally this should include the size of the inputs as well. This will be
updated when we add support for kernels which take actual inputs.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Marek Olšák [Thu, 22 Apr 2021 04:11:18 +0000 (00:11 -0400)]
gallium+(u_threaded,r300,r600,radeonsi): move transfer offset into pipe_transfer
Let's use the 4 bytes of unused padding usefully in pipe_transfer.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
Marek Olšák [Thu, 22 Apr 2021 03:40:51 +0000 (23:40 -0400)]
gallium: remove 4 bytes from pipe_transfer
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
Marek Olšák [Thu, 22 Apr 2021 03:40:26 +0000 (23:40 -0400)]
gallium: renumber PIPE_MAP_* enums to remove holes
We could change the type into 16 bits if needed.
PB_USAGE flags need to match PIPE_MAP flags due to static assertions.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
Rob Clark [Sat, 1 May 2021 15:44:25 +0000 (08:44 -0700)]
freedreno/ci: Update piglit skips/fails
Add spec@arb_pixel_buffer_object@texsubimage cube_map_array pbo to a530
fails for the same reason as spec@arb_texture_cube_map_array@texsubimage cube_map_array
(it is sometimes triggering gpu hangs that cause other flakes).
And remove two a630 xfails that started showing up as UnexpectedPass.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Sat, 1 May 2021 15:25:34 +0000 (08:25 -0700)]
freedreno/ci: Mark client_wait_sync_finish as flake
This one has shown up a couple times since fd/go-fast, I'm still trying
to reproduce/debug.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Thu, 29 Apr 2021 18:10:46 +0000 (11:10 -0700)]
freedreno: Flush resources harder
pctx->flush_resource() has the same expectations that the resource can
be shared with an external client as pctx->flush(), but without the
convenience of a fence to know *when* the resource must be visible to
that external client. So we need to ensure the batch is flushed all the
way to the kernel so that implicit-sync can do it's job.
Fixes:
e9a9ac6f77f ("freedreno/drm: Async submit support")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Thu, 29 Apr 2021 18:31:25 +0000 (11:31 -0700)]
freedreno/drm: Allow FD_BO_PREP_FLUSH without _NOSYNC
This provides the upper layer (gallium, etc) a way to ensure that
rendering involving the bo has been flushed all the way to the kernel.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Thu, 29 Apr 2021 16:02:09 +0000 (09:02 -0700)]
freedreno: Remove samples-per-tex tracking
Looks like this was unused, and only served to segfault when unbinding
textures.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
projects / platform / upstream / mesa.git / log