review.tizen.org Git - platform/upstream/mesa.git/log

gallium/ntt: Drop comment about needing loop label setup.

BRK/CONT don't take a label, as shown by tgsi_opcode_tmp.h and the lack of
any users of a label on those instructions in tree. I can't find any user
of ENDLOOP's label. Additionally, GLSL-to-TGSI apparently never set up
the BGNLOOP label, so even nvfx's usage probably wants us to not set it.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>

gallium/ntt: Add support for emitting TXF_LZ.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>

gallium/ntt: Emit sample index when necessary for image load/store.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>

gallium/ntt: Emit SSBO buffer declarations.

This doesn't set the atomic flag the way the old TGSI path used to,
leaving us with a possible delta in caching modes on nv50 tgsi.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>

gallium/ntt: Drop XXX comment about supporting carry opcodes.

The GLSL-to-NIR path didn't do carry, so we don't need to.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>

ci: Disable the freedreno farm, which went down last night.

We're debugging it now, but let merges flow until then.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8395>

nv50: fake enough resume support pre-nva0 to pass gles3 requirements

GLES3 supports pause/resume of xfb. However since there's no geometry
shader support in ES3, it's a lot easier to figure out the offsets to
use. This makes it work for the dEQP tests at least.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8346>

nv50: only support 4 components in separate xfb mode

This is consistent with what the blob reports.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8346>

virgl: fix modifier truncation

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8372>

radv/winsys: set has_packed_math_16bit in null winsys

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8392>

microsoft/compiler: do not lower away 64-bit ffma

In DXIL, the FMA instruction only supports 64-bit operations. However,
back when we implemented support for this, there were only a single
switch for lowering all ffma instructions, so we couldn't easily use it.

But now that there's separate flags to lower ffma on 16, 32 and 64 bit,
we can lower 16 and 32 bit ffmas, and leave 64 bit ffmas alone.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8349>

microsoft/compiler: correct dxil fma opcode

When I originally added the FFMA opcode here, I added the FMAD opcode
instead of the FMA opcode. The reason for this is that it works on
32-bit values as well, so that seemed like a better fit.

But that's not correct, as the FMA opcode isn't a fused operation, so
let's correct the opcode.

This isn't currently in use, because we currently lower away all ffma
opcodes on the NIR level, but that's about to change.

While we're at it, let's also update the opcode name to match the DXIL
documentation.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8349>

zink: disable render_condition_enable during blit

We don't support stencil-exports yet, and even when we will, we might
not support it on all hardware. So we really need an alternative plan
here, even when render_condition_enable is true.

Fixing this properly is much more involved, and depends on reworking
render-condition along the lines that we do in !7746 to support pausing
and resuming properly first. So let's do the minimal thing, which is to
allow this to work in cases where no render-condition is active.

Fixes: 767f70dfe13 ("gallium/util: fix util_can_blit_via_copy_region for conditional rendering")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4056
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8379>

radv: only set BO metadata for the first plane

To properly support multi-planar images, we don't want to set metadata
on anything other than the first plane. To achieve this radv currently
checks for the image TILING and assumes LINEAR means it's not the first
plane.

However this doesn't account for images with a single LINEAR plane. We
still want to set metadata on those, e.g. to properly set the scanout
bit in the tiling flags.

Instead of checking for LINEAR, check if the offset is zero. Only the
first plane has a zero offset on AMD.

This mirrors the radeonsi logic [1].

While at it, move the metadata declaration into the if block.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/blob/6fecdc6dda6da15d616a31900508214c81cd256e/src/gallium/drivers/radeonsi/si_texture.c#L710

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8086>

zink: clamp shader input/output max values

some vulkan drivers (e.g., amdvlk) advertise absolutely huge values here,
resulting in bitmask overflows everywhere since gallium assumes a max of
32 for vertex inputs and nir uses 64bit types for others

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8318>

radv: support SpvCapabilitySparseResidency

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

radv: implement is_sparse_texels_resident and sparse_residency_code_and

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

ac/nir: implement sparse image/texture loads

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

ac/nir: implement nir_op_vec5

Since sparse fetch/load uses vec5 destinations, it may be possible that we
encounter nir_op_vec5.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

aco: form sparse load clauses

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

aco: implement sparse image loads

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

aco: implement sparse texture fetches

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

aco: implement nir_op_vec5

Since sparse fetch/load uses vec5 destinations, it may be possible that we
encounter nir_op_vec5.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

aco: move MIMG VDATA to its own operand

We will want both a VDATA operand and a sampler for some TFE/LWE MIMG
instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

aco: fix MIMG_instruction::lwe comment

The ISA docs were inconsistent about what this flag does, but that seems
fixed in the RDNA doc.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>

aco: fix unreachable() for uniform 8/16-bit nir_op_mov from VGPR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: d20a752c0de ("aco: use Builder::copy more")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8380>

ci: Add *ignore_scheduled_pipelines to mesa/gallium rules templates

These are currently not used directly, but maybe this can prevent copy
and paste accidents.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8360>

ci: Rule out scheduled pipelines in .windows-build-rules

The lack of this broke scheduled pipelines, because they attempted
to create a meson-windows-vs2019 job, which couldn't work (because the
windows_build_vs2019 job doesn't exist in scheduled pipelines).

Fixes: 84c8a35aa2ca "CI: Add Windows source dependency map"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8360>

util: Disable memstream for Apple builds

Not all SDK versions support open_memstream. Maybe some other day.

Fixes: af8d488ea5e ("util,ac,aco,radv: Cross-platform memstream API")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8269>

radv: fix performance regression by restoring TC-compat HTILE in GENERAL

This fixes a performance regression for games (eg. Youngblood) that
declare all images as concurrent. This is likely buggy for compute
queues but this just restores the previous behaviour for now.

Fixes: f4f096805b0 ("radv: fix TC-compat HTILE images with DST_OPTIMAL on the compute queue")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8351>

radv: fix enabling TC-compat HTILE in GENERAL for writes on GFX10+

It wasn't expected to also enable inside render loops.

Fixes: 4bb92d9145f ("radv: enable TC-compat HTILE in GENERAL on GFX10+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8351>

radv: configure the texture descriptor for TC-compat CMASK on GFX10+

This was missing, it can be enabled with RADV_PERFTEST=tccompatcmask.
Note that this feature is still experimental.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8350>

r300: Fix typos.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8296>

gallium/ntt: lower uniforms to ubo

NTT doesn't handle uniforms, and requires them to have been lowered to
UBOs. But for drivers that don't set
nir_shader_compiler_options::lower_uniforms_to_ubo to true, this won't
have happened yet. Neither Zink nor V3D sets this option, and in the
case of Zink this isn't trivial to change.

So let's lower uniforms to UBOs in this case in NTT instead.

Fixes: 03c60762f57 ("gallium/ntt: Fix load_ubo_vec4 buffer index setup.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4047
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8365>

iris: Blit stencil according to aspect_mask

With this change, stencil picks up the fix for 3D texture blits
introduced with commit 382451ff9d7b.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8340>

iris: Use single-aspect formats more in iris_blit

In order to handle blitting the stencil aspect of a depth-stencil
resource, use aspect-specific pipe formats in the aspect_mask loop.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8340>

iris: Blit non-stencil according to aspect_mask

When blitting just the stencil aspect, the source and destination
resources are prepared/setup twice. Move the unconditional resource
setup into the aspect_mask loop to avoid this.

In addition, use the aspect provided by the loop instead of the mask
provided by the info parameter.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8340>

iris: Loop through an aspect mask in iris_blit

Enables dropping the stencil-specific blit later on.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8340>

iris: Increase use of pipe_resources in iris_blit

Allows the affected code to avoid being moved into a while loop later
on.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8340>

iris: Use texture preparation helper in iris_blit

Use iris_resource_prepare_texture in iris_blit to avoid partial resolves
for sRGB <-> linear texture views. This affects a trace of L4D2.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8340>

iris: Move depth-format assertion out of iris_blit

Instead of having a depth-specific assertion in a generic portion of
iris_blit, move it into the depth-specific cases of
iris_resource_texture_aux_usage. Since iris_blit calls that function,
the test still occurs.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8340>

iris: Don't prepare depth for stencil-aspect blits

Before this change, iris_blit would prepare the depth buffer in a
depth-stencil resource even when only the stencil aspect was used for the
blit. Use the aspect mask to prepare the correct resource.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8340>

mesa: Don't make building tests conditional on building DRI drivers

These tests should work, and be built, even if you're only building
gallium drivers.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8353>

mesa: Fix array-format-to-format table on big-endian

The table constructor and the table lookup were doing different things
for big-endian. This fixes MesaFormatsTest.FormatFromFormatAndType and
MesaFormatsTest.FormatMatchesFormatAndType failing to round-trip for
GL_RGBA / GL_SHORT, which we're not currently running in CI for s390x,
but which a subsequent commit will enable.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8353>

tests: Fix memory leaks in DispatchSanity

Needed to pass asan CI.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8353>

radv/llvm,aco: always split typed vertex buffer loads on GFX6 and GFX10+

To avoid any alignment issues that triggers memory violations and
eventually a GPU. This can happen if the stride (static or dynamic)
is unaligned and also if the VBO offset is aligned to scalar
(eg. stride is 8 and VBO offset is 2 for R16G16B16A16_SNORM).

The AMD Windows driver also always splits typed vertex fetches.

fossils-db (Sienna Cichlid):
Totals from 56508 (40.54% of 139391) affected shaders:
SGPRs: 2643545 -> 2664516 (+0.79%); split: -0.19%, +0.98%
VGPRs: 2007472 -> 1995408 (-0.60%); split: -0.74%, +0.13%
CodeSize: 70596372 -> 73913312 (+4.70%); split: -0.00%, +4.70%
MaxWaves: 772653 -> 774916 (+0.29%); split: +0.37%, -0.08%
Instrs: 14074162 -> 14567072 (+3.50%); split: -0.00%, +3.51%
Cycles: 69281276 -> 71253252 (+2.85%); split: -0.00%, +2.85%
VMEM: 22047039 -> 25554196 (+15.91%); split: +17.20%, -1.29%
SMEM: 4120370 -> 4360820 (+5.84%); split: +7.41%, -1.58%
VClause: 416913 -> 438361 (+5.14%); split: -1.86%, +7.01%
SClause: 536739 -> 542637 (+1.10%); split: -0.33%, +1.43%
Copies: 977194 -> 970015 (-0.73%); split: -2.43%, +1.69%
Branches: 241205 -> 241193 (-0.00%); split: -0.06%, +0.06%
PreVGPRs: 1505645 -> 1505379 (-0.02%)

This fixes GPU hangs with bin/draw-vertices from Piglit on GFX10+
with Zink.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8363>

aco: fix creating the dest vector when 16-bit vertex fetches are splitted

Compute the number of components of the destination vector from the
bitsize when eg. a 16-bit vec2 vertex fetches is splitted. This is
because the dst will be a v1, so the p_create_vector should be created
from two v2b fro both sizes to match.

This prevents a regression from the next change which will split
typed vertex buffer loads on GFX6 and GFX10+.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8363>

docs/release-calendar.rsv: Remove spaces

The generated entries don't have spaces, and the csv parser doesn't
like that some rows do and others don't have spaces.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8356>

docs: Add calendar entries for 21.0 release candidates.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8356>

nir,radv: add and use nir_vectorize_tess_levels()

fossil-db (Sienna):
Totals from 1342 (0.97% of 138791) affected shaders:
CodeSize: 3287996 -> 3269572 (-0.56%); split: -0.56%, +0.00%
Instrs: 629896 -> 628191 (-0.27%); split: -0.31%, +0.04%
Cycles: 2619244 -> 2612424 (-0.26%); split: -0.30%, +0.04%
VMEM: 388807 -> 389273 (+0.12%); split: +0.14%, -0.02%
SMEM: 90655 -> 90700 (+0.05%); split: +0.06%, -0.01%
VClause: 21831 -> 21812 (-0.09%)
PreVGPRs: 44155 -> 44058 (-0.22%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>

radv: vectorize shader I/O

Fixes code size regressions after enabling TCS/TES for ACO.

fossil-db (Sienna):
Totals from 2588 (1.86% of 138791) affected shaders:
SGPRs: 109950 -> 108480 (-1.34%); split: -1.43%, +0.09%
VGPRs: 107764 -> 112060 (+3.99%); split: -0.03%, +4.02%
CodeSize: 5957760 -> 5321656 (-10.68%)
MaxWaves: 31718 -> 30358 (-4.29%); split: +0.03%, -4.32%
Instrs: 1116300 -> 1029000 (-7.82%)
Cycles: 4600344 -> 4251072 (-7.59%)
VMEM: 980024 -> 812978 (-17.05%); split: +1.14%, -18.18%
SMEM: 275458 -> 258227 (-6.26%); split: +2.34%, -8.60%
VClause: 42925 -> 30533 (-28.87%); split: -31.02%, +2.15%
SClause: 31554 -> 31362 (-0.61%); split: -1.79%, +1.18%
Branches: 15689 -> 15697 (+0.05%)
PreVGPRs: 80399 -> 83953 (+4.42%); split: -0.00%, +4.42%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>

nir/load_store_vectorize: add data as callback args

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>

nir: add nir_load_store_vectorize_options

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>

nir/load_store_vectorize: don't ignore subgroup memory barriers

Not sure why I thought this was correct, but we should consider them for
optimization purposes.

Fixes: ce9205c03bd ('nir: add a load/store vectorization pass')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>

v3d: reinterpret stencil data as uint texture in stencil blit path

There is a path to blit stencil buffers reinterpreting the stencil data
as an RGBA8888 or R8 float texture.

This works fine except for the case when the stencil buffer is
multisampled, and the blit operation needs to resolve it: an average of
the samples is done, which is incorrect, as only one sample must be
used.

This can be observed n the piglit test
`ext_framebuffer_multisample-unaligned-blit 2 stencil downsample -auto
-fbo`, specifically in the triangles border.

To avoid this averaging, let's reinterpret the stencil data as RGBA8888
or R8 uint texture.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8361>

radv: workaround games which assume full subgroups if cswave32 is enabled

This assumption becomes incorrect with RADV_PERFTEST=cswave32.

Games include Detroit: Become Human and Doom Eternal.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7918>

nir: gather whether a compute shader uses non-quad subgroup intrinsics

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7918>

radv: implement CREATE_REQUIRE_FULL_SUBGROUPS_BIT with cswave32

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7918>

wsi/x11: Treat IMMEDIATE present mode the same as MAILBOX for Xwayland

Two main reasons:

As described in the previous commit, sending buffers to the Wayland
compositor as quickly as possible effectively results in mailbox
behaviour.

Also, doing the same as for MAILBOX present mode provides the following
benefits:

* We use more images in the swapchain, which avoids stalls on the client
  side if the Wayland compositor directly uses the client buffers for
  scanout.

* We wait for fences to signal before submitting a new buffer, which
  avoids missing frames in the Wayland compositor due to fences not
  signalling in time for a flip.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3673
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>

wsi/x11: Use PresentOptionAsync for MAILBOX present mode with Xwayland

This allows Xwayland to forward buffers to the Wayland compositor ASAP
for fullscreen / undecorated windows, which in turn allows true mailbox
behaviour in the Wayland compositor.

Without this, Xwayland has to emulate the mailbox behaviour itself,
which it cannot do as well as the Wayland compositor by design.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>

wsi/x11: Detect Xwayland

The following commits will introduce different behaviour for Xwayland.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>

wsi/x11: Always link against xcb-xrandr

The next commit will make use of it even without
VK_USE_PLATFORM_XLIB_XRANDR_EXT.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>

wsi/x11: Set recognizable name for WSI swapchain queue thread

This makes it easier to recognize the thread e.g. in a debugger.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>

radeonsi: implement SQTT support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

radeonsi: add radeon_set_uconfig_reg_seq_perfctr

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

ac/sqtt: move radv_get_expected_buffer_size to ac

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

ac/sqtt: move ac_is_thread_trace_complete to ac

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

ac/sqtt: move rgp/sqtt def to ac

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

ac/radv: move radv_rgp.c to ac

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

ac/radv: move sqtt structs and helpers to amd/common

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

ac/sqtt: add ac_thread_trace_data

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

radeonsi: pass radeon_cmdbuf to si_cp_dma_wait_for_idle

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

radeonsi: pass radeon_cmdbuf to emit_cache_flush

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>

gv100/ir: Use system wide atomics

Increase the scope of atomic operations from GPU to system. This is
required for support of SVM to ensure atomic access is maintained for
memory buffers that are not local to the current GPU.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7955>

gv100/ir: Make emitATOM consistent with emitRED

GV100 code generation uses ATOM instructions for compare-and-swap and
RED instructions for other atomic operations. Make the scope consistent
for both types of operations.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7955>

radeonsi: remove si_gs_prolog_bits::gfx9_prev_is_vs

It didn't do anything useful. GS doesn't use the other user SGPRs.
If we decrease the number of user SGPRs we declare for the GS prolog,
we can remove gfx9_prev_is_vs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8344>

radeonsi: fix hang caused by for loop with exec=0 in LS and ES

LLVM expects that exec != 0 when entering loops and generates this code
that becomes an infinite loop if exec == 0:

BB5_1:
    vcc_lo = (inverted terminating condition)
    s_and_b32 vcc_lo, exec_lo, vcc_lo
    s_cbranch_vccnz BB5_3    // jump if vcc != 0 (break statement)
    // ... loop body ...
    s_branch BB5_1
BB5_3:

For non-monolithic VS before TCS, VS before GS, and TES before GS,
we set exec = (thread enabledmask), which sets 0 for HS-only and GS-only
waves, causing the infinite loop condition above.

Fix it as follows:
- set exec = ~0 at the beginning
- wrap the whole shader (LS and ES) in a conditional block, so that HS-only
  and GS-only waves jump over it and never enter such a loop

The TES before GS hang can be reproduced by gfxbench:
    testfw_app --gfx egl -w 1920 -h 1080 --gl_api gles -t gl_tess

Fixes: 68d6d097f15 - radeonsi/gfx9: add GFX9 and VEGA10 enums

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8344>

bin/gen_calendar_entries: Add support for making a release

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>

bin/gen_calendar_entries: Add support for extending a release

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>

bin: Add script for manipulating the release calendar

Currently it only handles creating entries for a new rc.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>

docs: store the release-calendar information in csv (and fix tests)

Restructured text (and markdown) is painful to programatically
manipulate, most python parsers are geared towards writing markdown and
generating html. I'd like to move the calendar updates to being
scripted, as such using csv to store them will be convenient. This also
allows us to simplify our scripting that manipulates the table
considerably.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>

freedreno: Add missing dep on u_tracepoints.

Fixes: a02dcb970fff ("freedreno: Add GPU tracepoints")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8355>

freedreno: Mark a615/a618 as also lacking Z24_UINT_S8_UINT support.

Rob says it's also the case on 618, and presumably 615 as well then, so
make it take the same path as a630.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>

freedreno: Disable UBWC on z24s8 on a630.

Stencil texture sampling (such as what we have to do for BlitFramebuffer)
is broken with UBWC enabled. We can't just take the
fd_resource_uncompress() path, because that's a blit just like
BlitFramebuffer.

Fixes failure in dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8,
but also the uncaught rendering fails of 4_samples.stencil_index8 and
depth24_stencil8.

Prior to "911ce374caf0 freedreno/a6xx: Fix MSAA clear" we would usually
pass and sometimes flake fail on this test occasionally, thus it being
listed as a flake (though the rendering was actually broken). Since that
commit, though, we consistently fail on a pixel of the broken rendering,
and thus this was brought to my attention by the #freedreno-ci channel
spam.

Rob took a look at the performance impact of this, and the worst was maybe
up to .5% fps hit on trex.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>

freedreno/a6xx: Fix z24s8 non-ubwc blits on a630.

Taken from the logic in turnip (though they have the format table have
8888_unorm and override to z24s8_as_rgba for blits in the ubwc case)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>

freedreno/a6xx: Move the IBO pipe2tex down to where it's used.

For the texture path, the pipe2tex happens in fd6_tex_const_0().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>

turnip: Move the limited_z24s8 flag to the shared device info.

I want to do the same logic in freedreno, so use the same flag. On
suggestion by robclark, rename it to what it specifically means.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>

kmsro: sync Android.mk GALLIUM_TARGET_DRIVERS

Sync Android.mk GALLIUM_TARGET_DRIVERS names from kmsro meson.build,
notably adding the missing mediatek, meson and rockchip display drivers
names.

It also fixes the imx name into imx-drm as referenced in meson.build
and src/gallium/targets/dri/target.c

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7443>

docs: use a single cell for the branch number

Fixes: 94c6511757254da6c3b6 ("docs: add release schedule for 20.3")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7950>

vtn: support SpvCapabilitySparseResidency

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>

nir/lower_tex: fix lower_tg4_offsets with sparse fetches

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>

nir: add sparse_residency_code_and

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>

nir,spirv: implement SpvOpImageSparseTexelsResident

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>

nir,spirv: add sparse image loads

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>

nir,spirv: add sparse texture fetches

Like SPIR-V and GL_ARB_sparse_texture2, these return a residency code. It
is placed in the destination after the rest of the result. If it's zero,
then the texel is resident. Otherwise, it's not resident.

Besides the larger destination and the residency code, sparse fetches
work the same as normal fetches.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>

nir: allow 5 component vectors

These will be useful for sparse texture instructions and image load
intrinsics.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>

nir/tests: fix callback for load/store vectorizer tests

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>

nir/opt_vectorize: fix call to filter function

Due to the typo, it could happen that instructions
got further vectorized than intended.

Fixes: 8eaf9c61d17370d3f272ca39256de58231c02127 ('nir/opt_vectorize: don't hash filtered instructions')
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8352>

freedreno/afuc: Replace readfile with os_read_file.

Tested afuc-disasm produced same output.

$ ./builddir/src/freedreno/afuc/afuc-disasm -g 6 src/freedreno/.gitlab-ci/reference/afuc_test.fw > /tmp/afuc_test.asm
$ diff ./src/freedreno/.gitlab-ci/reference/afuc_test.asm /tmp/afuc_test.asm
$ echo $?
0

Suggested-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8290>