Simon Pilgrim [Wed, 2 May 2018 18:48:23 +0000 (18:48 +0000)]
[X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM and YMM/ZMM scheduler classes
llvm-svn: 331386
Alexey Bataev [Wed, 2 May 2018 18:44:10 +0000 (18:44 +0000)]
[OPENMP] Analyze the type of the mapped entity instead of its base.
If the mapped entity is a data member, we erroneously checked the type
of its base rather than the type of the mapped entity itself.
llvm-svn: 331385
Martin Storsjo [Wed, 2 May 2018 18:24:37 +0000 (18:24 +0000)]
[COFF, ARM64] Hook up a few remaining relocations
Differential Revision: https://reviews.llvm.org/D46355
llvm-svn: 331384
Farhana Aleen [Wed, 2 May 2018 18:16:39 +0000 (18:16 +0000)]
[AMDGPU] A trivial fix for a buildbot failure caused by "commit
224a839fcbbead221f872cd32a1dd0c308d37299".
Author: FarhanaAleen
llvm-svn: 331383
Petr Hosek [Wed, 2 May 2018 18:08:47 +0000 (18:08 +0000)]
[sanitizer] Fix Fuchsia ReadBinaryName not to crash when uninitialized
If the sanitizer runtime is loaded in a binary that doesn't really
support it, then __sanitizer_startup_hook will never have been
called to initialize StoredArgv. This case can't be supported, but
its failure mode shouldn't be to crash in sanitizer_common internals.
Patch By: mcgrathr
Differential Revision: https://reviews.llvm.org/D46344
llvm-svn: 331382
Daniel Sanders [Wed, 2 May 2018 17:59:16 +0000 (17:59 +0000)]
[reassociate] Fix excessive revisits when processing long chains of reassociatable instructions.
Summary:
Some of our internal testing detected a major compile time regression which I've
tracked down to:
r278938 - Revert "Reassociate: Reprocess RedoInsts after each inst".
It appears that processing long chains of reassociatable instructions causes
non-linear (potentially exponential) growth in the number of times an
instruction is revisited. For example, the included test revisits instructions
220 times in a 20-instruction test.
It appears that r278938 reversed the order instructions were visited and that
this is preventing scheduled revisits from being cancelled as a result of
visiting the instructions naturally during normal processing. However, simply
reversing the order also harmed the generated code. Upon closer inspection, it
was discovered that revisits occurred in the opposite order to the first pass
(Thanks to escha for spotting that).
This patch makes the revisit order consistent with the first pass which allows
more revisits to be cancelled. This does appear to have a small impact on the
generated code in few cases but it significantly reduces compile-time.
After this patch, our internal test that was most affected by the regression
dropped from ~2 million revisits to ~4k resulting in Reassociate having 0.46%
of the runtime it had before (99.54% improvement).
Here's the summaries reported by lnt for the LLVM test-suite with --benchmarking-only:
| metric | geomean before patch | geomean after patch | delta |
| ----- | ----- | ----- | ----- |
| compile time | 0.1956 | 0.1261 | -35.54% |
| execution time | 0.3240 | 0.3237 | - |
| code size | 7365.4459 | 7365.6079 | - |
The results have a few wins and losses on compile-time, mostly in the +/- 2.5% range. There was one outlier though:
| Performance Regressions - compile_time | Δ | Previous | Current |
| MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 9.82% | 2.0473 | 2.2483 |
Reviewers: javed.absar, dberlin
Reviewed By: dberlin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45734
llvm-svn: 331381
Simon Pilgrim [Wed, 2 May 2018 17:58:50 +0000 (17:58 +0000)]
[X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes with more common default values
llvm-svn: 331380
Volodymyr Sapsai [Wed, 2 May 2018 17:56:45 +0000 (17:56 +0000)]
Emit an error when mixing <stdatomic.h> and <atomic>
Atomics in C and C++ are incompatible at the moment and mixing the
headers can result in confusing error messages.
Emit an error explicitly telling about the incompatibility. Introduce
the macro `__ALLOW_STDC_ATOMICS_IN_CXX__` that allows to choose in C++
between C atomics and C++ atomics.
rdar://problem/
27435938
Reviewers: rsmith, EricWF, mclow.lists
Reviewed By: mclow.lists
Subscribers: jkorous-apple, christof, bumblebritches57, JonChesterfield, smeenai, cfe-commits
Differential Revision: https://reviews.llvm.org/D45470
llvm-svn: 331379
Volodymyr Sapsai [Wed, 2 May 2018 17:50:43 +0000 (17:50 +0000)]
Emit an error when mixing <stdatomic.h> and <atomic>
Atomics in C and C++ are incompatible at the moment and mixing the
headers can result in confusing error messages.
Emit an error explicitly telling about the incompatibility. Introduce
the macro `__ALLOW_STDC_ATOMICS_IN_CXX__` that allows to choose in C++
between C atomics and C++ atomics.
rdar://problem/
27435938
Reviewers: rsmith, EricWF, mclow.lists
Reviewed By: mclow.lists
Subscribers: jkorous-apple, christof, bumblebritches57, JonChesterfield, smeenai, cfe-commits
Differential Revision: https://reviews.llvm.org/D45470
llvm-svn: 331378
Alexey Bataev [Wed, 2 May 2018 17:39:00 +0000 (17:39 +0000)]
[OPENMP] Do not emit warning for implicitly declared target functions.
Since upcoming OpenMP 5.0 functions can be mapped implicitly as declare
target and we should not emit warnings for such functions.
llvm-svn: 331377
Krzysztof Parzyszek [Wed, 2 May 2018 17:20:22 +0000 (17:20 +0000)]
Add assertion to padding size calculation, NFC
The size of an object cannot be less than the emitted size of all the
contained elements. This would cause an overflow in padding size
calculation. Add an assert to catch this.
Patch by Suyog Sarda.
llvm-svn: 331376
Adrian Prantl [Wed, 2 May 2018 17:11:43 +0000 (17:11 +0000)]
Silence compiler warning.
llvm-svn: 331375
Pavel Labath [Wed, 2 May 2018 17:00:33 +0000 (17:00 +0000)]
Fix gdb-remote qMemoryRegionInfo unit tests for xml-enabled builds
In case we are building with xml enabled, the GetMemoryRegionInfo
function will send extra packets to query te extended memory map, which
the tests were not expecting.
Add an expectation for this to the test. Right now, it's just a basic
one which pretends we don't support the extension, however, it would be
also interesting the add a test which verifies the extension-enabled
case.
I also noticed that the test does a pretty lousy job of validating the
returned memory region info, so I add a couple of extra assertions to
improve that.
llvm-svn: 331374
Adrian Prantl [Wed, 2 May 2018 16:55:16 +0000 (16:55 +0000)]
Enable AUTOBRIEF in doxygen configuration.
This brings the LLDB configuration closer to LLVM's and removes visual
clutter in the source code by removing the @brief commands from
comments.
This patch also reflows the paragraphs in all doxygen comments.
See also https://reviews.llvm.org/D46290.
Differential Revision: https://reviews.llvm.org/D46321
llvm-svn: 331373
Alexey Bataev [Wed, 2 May 2018 16:52:07 +0000 (16:52 +0000)]
[OPENMP] Enable c++ exceptions outside of the target constructs iff they are
enabled for the host.
If the compilation for the host enables C++ exceptions, but they are not
supported by the device, we still need to allow the code with the
exception handling constructs outside of the target regions.
llvm-svn: 331372
Farhana Aleen [Wed, 2 May 2018 16:48:52 +0000 (16:48 +0000)]
Revert "[AMDGPU] performAddCombine should run after DAG is legalized."
This reverts commit
6b97d2995566b4dddd6bf0d75579ff44501d4494.
llvm-svn: 331371
Jessica Paquette [Wed, 2 May 2018 16:42:51 +0000 (16:42 +0000)]
Add -foutline option to enable the MachineOutliner in AArch64
Since we've been working on productizing the MachineOutliner in AArch64, it
makes sense to provide a more user-friendly way to enable it.
This allows users of AArch64 to enable the outliner using -foutline instead
of -mllvm -enable-machine-outliner. Other, less mature implementations (e.g,
x86-64) can still enable the pass using the -mllvm option.
Also add a test to make sure it works.
llvm-svn: 331370
Simon Pilgrim [Wed, 2 May 2018 16:25:41 +0000 (16:25 +0000)]
[X86] Convert most remaining XOP uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
llvm-svn: 331369
Farhana Aleen [Wed, 2 May 2018 16:24:10 +0000 (16:24 +0000)]
[AMDGPU] performAddCombine should run after DAG is legalized.
Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization
in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with
illegal types.
Author: FarhanaAleen
Reviewed By: rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D46337
llvm-svn: 331368
Simon Pilgrim [Wed, 2 May 2018 16:16:24 +0000 (16:16 +0000)]
Fix line-endings. NFCI.
llvm-svn: 331367
Jan Vesely [Wed, 2 May 2018 16:06:52 +0000 (16:06 +0000)]
clc_sqrt: Reuse unary_decl.inc
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Aaron Watry <awatry@gmail.com>
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 331366
Alexey Bataev [Wed, 2 May 2018 15:45:28 +0000 (15:45 +0000)]
[OPENMP] Support C++ member functions in the device constructs.
Added correct emission of the C++ member functions for the device
function when they are used in the device constructs.
llvm-svn: 331365
Philip Pfaffe [Wed, 2 May 2018 15:27:32 +0000 (15:27 +0000)]
Pass compiler arguments in the create_ll.sh script
Summary:
Occasionally you need an include or similar things to be configured
when making a new testcase. Allow passing these to the script and down to the
compiler calls.
Reviewers: grosser, Meinersbur, bollu
Reviewed By: Meinersbur
Subscribers: bollu, llvm-commits, pollydev
Differential Revision: https://reviews.llvm.org/D46359
llvm-svn: 331364
Philip Pfaffe [Wed, 2 May 2018 14:55:39 +0000 (14:55 +0000)]
Revert "[polly] [ScopInfo] Don't pre-compute the name of the Scop's region."
This reverts commit
0f9dc03765dc301fff7a52e2a0e1dd3e5f3130c5, r328666.
The change introduced a use-after-free, caused by the temporary name string
being destroyed after converting it to a StringRef.
llvm-svn: 331363
Clement Courbet [Wed, 2 May 2018 14:35:48 +0000 (14:35 +0000)]
Re-land rL331357 "[X86] Fix scheduling info for VMPSADBWYrmi."
Without the rebase mess.
https://reviews.llvm.org/D46356
llvm-svn: 331362
Malcolm Parsons [Wed, 2 May 2018 14:26:12 +0000 (14:26 +0000)]
[analyzer] Fix filename in cross-file HTML report
Summary:
The filename is currently taken from the start of the path, while the
line and column are taken from the end of the path.
This didn't matter until cross-file path reporting was added.
Reviewers: george.karpenkov, dcoughlin, vlad.tsyrklevich
Reviewed By: george.karpenkov, vlad.tsyrklevich
Subscribers: xazax.hun, szepet, a.sidorin, cfe-commits
Differential Revision: https://reviews.llvm.org/D45611
llvm-svn: 331361
Simon Pilgrim [Wed, 2 May 2018 14:25:32 +0000 (14:25 +0000)]
[X86] Cleanup WriteFMul scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.
llvm-svn: 331360
Simon Pilgrim [Wed, 2 May 2018 14:22:30 +0000 (14:22 +0000)]
Fix '32-bit shift implicitly converted to 64 bits' warning by using APInt::setBit instead.
llvm-svn: 331359
Alexey Bataev [Wed, 2 May 2018 14:20:50 +0000 (14:20 +0000)]
[OPENMP] Emit names of the globals depending on target.
Some symbols are not allowed to be used as names on some targets. Patch
ries to unify the emission of the names of LLVM globals so they could be
used on different targets.
llvm-svn: 331358
Clement Courbet [Wed, 2 May 2018 13:54:38 +0000 (13:54 +0000)]
Revert rL331355 "[X86] Fix scheduling info for VMPSADBWYrmi."
It contains unrelated changes.
llvm-svn: 331357
Clement Courbet [Wed, 2 May 2018 13:46:14 +0000 (13:46 +0000)]
[X86] Fix scheduling info for (V?)SQRTPDm on silvermont.
https://reviews.llvm.org/D46356
llvm-svn: 331356
Clement Courbet [Wed, 2 May 2018 13:40:48 +0000 (13:40 +0000)]
[X86] Fix scheduling info for VMPSADBWYrmi.
https://reviews.llvm.org/D46356
llvm-svn: 331355
Clement Courbet [Wed, 2 May 2018 13:37:28 +0000 (13:37 +0000)]
[MIPS] Fix DIV/DIVU scheduling classes.
https://reviews.llvm.org/D46356.
llvm-svn: 331354
Simon Pilgrim [Wed, 2 May 2018 13:32:56 +0000 (13:32 +0000)]
[X86] Convert most remaining AVX512 uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
We've dealt with the majority already.
llvm-svn: 331353
Sander de Smalen [Wed, 2 May 2018 13:32:39 +0000 (13:32 +0000)]
[AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D46270
llvm-svn: 331352
Simon Tatham [Wed, 2 May 2018 13:17:26 +0000 (13:17 +0000)]
[TableGen] Don't quote variable name when printing !foreach.
An input !foreach expression such as !foreach(a, lst, !add(a, 1))
would be re-emitted by llvm-tblgen -print-records with the first
argument in quotes, giving !foreach("a", lst, !add(a, 1)), which isn't
valid TableGen input syntax.
Reviewers: nhaehnle
Reviewed By: nhaehnle
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46352
llvm-svn: 331351
Pavel Labath [Wed, 2 May 2018 13:14:18 +0000 (13:14 +0000)]
Predicate.h: remove unused functions
The functions are unused, their comments are out of date with the
implementation, and the implementation is out of date with the rest of the code
base (it uses seconds(0) to mean infinite wait, whereas elsewhere we use the
Timeout class).
llvm-svn: 331350
Sander de Smalen [Wed, 2 May 2018 13:00:30 +0000 (13:00 +0000)]
[AArch64][SVE] Asm: Support for scatter ST1 store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46248
llvm-svn: 331349
Simon Dardis [Wed, 2 May 2018 12:35:29 +0000 (12:35 +0000)]
Revert "[mips] Correct the predicates of sign extension instructions"
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.
This reverts r331346.
llvm-svn: 331348
Simon Pilgrim [Wed, 2 May 2018 12:27:54 +0000 (12:27 +0000)]
[X86] Convert most remaining uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
We've dealt with the majority already.
llvm-svn: 331347
Simon Dardis [Wed, 2 May 2018 12:25:33 +0000 (12:25 +0000)]
[mips] Correct the predicates of sign extension instructions
And eliminate the duplication of those instructions for microMIPS32r6.
llvm-svn: 331346
Henry Wong [Wed, 2 May 2018 12:11:22 +0000 (12:11 +0000)]
[analyzer] Add `TaintBugVisitor` to the ArrayBoundV2, DivideZero and VLASize.
Summary: Add `TaintBugVisitor` to the ArrayBoundV2, DivideZero, VLASize to be able to indicate where the taint information originated from.
Reviewers: NoQ, george.karpenkov, xazax.hun, a.sidorin
Reviewed By: NoQ
Subscribers: szepet, rnkovacs, cfe-commits, MTC
Differential Revision: https://reviews.llvm.org/D46007
llvm-svn: 331345
Peter Szecsi [Wed, 2 May 2018 11:52:54 +0000 (11:52 +0000)]
[ASTImporter] Fix isa cast assert
Do early return if we can't import the found decl for a member expr.
This follows the pre-existing scheme, e.g with E->getMemberDecl().
E->getFoundDecl().getDecl() can be null when a member expression does
not involve lookup. It may involve a lookup in case of a using directive
which refers to a member function in a base class template.
We faced this assert during the CTU analysis of google::protobuf v3.5.2.
We tried hard to synthesize a minimal test example both by hand and by
executing creduce on multiple files. Unfortunately, we were unable to reduce
to such a minimal example, yet. Nevertheless, this fix solved the problem in
protobuf.
To reproduce the error one must execute the analyzer with
-Xclang -analyzer-config -Xclang experimental-enable-naive-ctu-analysis=true -Xclang -analyzer-config -Xclang ctu-dir=/path/to/ctu_dir
Patch by Gabor Marton!
Differential Revision: https://reviews.llvm.org/D46019
llvm-svn: 331344
Sander de Smalen [Wed, 2 May 2018 11:48:49 +0000 (11:48 +0000)]
[AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D46269
llvm-svn: 331343
Florian Hahn [Wed, 2 May 2018 10:53:04 +0000 (10:53 +0000)]
[LoopInterchange] Update some loops to use range base for loops (NFC).
llvm-svn: 331342
Simon Dardis [Wed, 2 May 2018 09:55:49 +0000 (09:55 +0000)]
[mips] Correct the predicates for shifts.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D46123
llvm-svn: 331341
Simon Pilgrim [Wed, 2 May 2018 09:18:49 +0000 (09:18 +0000)]
[X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.
Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY.
llvm-svn: 331340
Sander de Smalen [Wed, 2 May 2018 08:49:08 +0000 (08:49 +0000)]
[AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46250
llvm-svn: 331339
Piotr Padlewski [Wed, 2 May 2018 08:22:07 +0000 (08:22 +0000)]
Mark invariant.group.barrier as inaccessiblememonly
It turned out that readonly argmemonly is not enough.
store 42, %p
%b = barrier(%p)
store 43, %b
the first store is dead, but because barrier was marked as
reading argument memory, it was considered alive. With
inaccessiblememonly it doesn't read the argument, but
it also can't be CSEd.
based on: https://reviews.llvm.org/D32006
llvm-svn: 331338
Bjorn Pettersson [Wed, 2 May 2018 06:56:38 +0000 (06:56 +0000)]
[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)
Summary:
This is a follow up to rL331182. A PHI node can be split up into
several MIR PHI nodes when being selected. When there is a
dbg.value intrinsic that uses the result of such a PHI node we
need to select several DBG_VALUE instructions, with fragment
expressions, in order to do a correct selection.
Reviewers: rnk, aprantl, vsk
Reviewed By: vsk
Subscribers: mattd, llvm-commits, JDevlieghere, aprantl, gbedwell, rnk
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D46329
llvm-svn: 331337
Matt Morehouse [Wed, 2 May 2018 02:55:28 +0000 (02:55 +0000)]
[libFuzzer] Don't short-circuit from CrashCallback.
Short-circuiting causes tests to fail on Mac since libFuzzer crashes
rather than exiting with an error code when an unexpected signal
happens.
llvm-svn: 331324
Richard Smith [Wed, 2 May 2018 02:43:22 +0000 (02:43 +0000)]
Update lldb to match clang r331244 (addition of char8_t).
Also fix misclassification of char16_t and char32_t: these are unsigned types,
not signed types.
llvm-svn: 331323
Bruno Cardoso Lopes [Wed, 2 May 2018 02:25:03 +0000 (02:25 +0000)]
[Modules] Allow @import to reach submodules in private module maps
A @import targeting a top level module from a private module map file
(@import Foo_Private), would fail if there's any submodule declaration
around (module Foo.SomeSub) in the same private module map.
This happens because compileModuleImpl, when building Foo_Private, will
start with the private module map and will not parse the public one,
which leads to unsuccessful parsing of Foo.SomeSub, since top level Foo
was never parsed.
Declaring other submodules in the private module map is not common and
should usually be avoided, but it shouldn't fail to build. Canonicalize
compileModuleImpl to always look at the public module first, so that all
necessary information is available when parsing the private one.
rdar://problem/
39822328
llvm-svn: 331322
Dean Michael Berris [Wed, 2 May 2018 00:43:17 +0000 (00:43 +0000)]
[XRay][tools] Rename llvm-xray filenames from .cc -> .cpp (NFC)
Summary:
This brings the filenames in accordance to the style guide and LLVM
conventions for C++ filenames.
As suggested by rnk@ in D46068.
Reviewers: rnk
Subscribers: mgorny, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D46301
llvm-svn: 331321
Sam Clegg [Wed, 2 May 2018 00:10:28 +0000 (00:10 +0000)]
Fix release build breakage
This function was added in rL331220 but wasn't
testing in release configurations.
llvm-svn: 331320
Volodymyr Sapsai [Tue, 1 May 2018 23:59:33 +0000 (23:59 +0000)]
Track skipped files in dependency scanning.
It's possible for a header to be a symlink to another header. In this
case both will be represented by clang::FileEntry with the same UID and
they'll use the same clang::HeaderFileInfo.
If you include both headers and use some single-inclusion mechanism
like a header guard or #import, one header will get a FileChanged
callback, and another FileSkipped.
So that we get an accurate dependency file, we therefore need to also
implement the FileSkipped callback in dependency scanning.
Patch by Pete Cooper.
Reviewers: bruno, pete
Reviewed By: bruno
Subscribers: cfe-commits, jkorous, vsapsai
Differential Revision: https://reviews.llvm.org/D30881
llvm-svn: 331319
Douglas Yung [Tue, 1 May 2018 23:32:09 +0000 (23:32 +0000)]
This test fails if there is no integrated assembler, so change the -c option to -S as it is not important to the test and allows it to pass when there is no integrated assembler.
llvm-svn: 331318
Sam Clegg [Tue, 1 May 2018 23:28:27 +0000 (23:28 +0000)]
[WebAssembly] Fix debug printing of symbol types
The Info.Kind field is a uint8_t which the OS was
trying to print as an ascii char.
llvm-svn: 331317
Matt Davis [Tue, 1 May 2018 23:04:01 +0000 (23:04 +0000)]
[llvm-mca] Lift the logic of the RetireControlUnit from the Dispatch translation unit into its own translation unit. NFC
The logic remains the same. Eventually, I see the RCU acting as its own separate stage in the instruction pipeline.
Differential Revision: https://reviews.llvm.org/D46331
llvm-svn: 331316
Jason Molenda [Tue, 1 May 2018 22:49:01 +0000 (22:49 +0000)]
Fix the .experimental. settings feature so that we don't return an error
if an experimental setting has been removed/is missing.
Add tests for the .experimental. settings behaviors -- that they correctly
forward through to the real setting if it has become a real setting,
that they don't generate errors when a settig has been removed.
As Pavel notes in https://reviews.llvm.org/D45348, the way I'm suppressing
errors in the setting is not completely correct - if any of the setting
path components include "experimental", a missing setting would be declared
a non-error. So
settings set target.experimental.setting-that-does-not-exist true
would not generate an error, which is correct. But as Pavel notes,
settings set setting-does-not-exist.experimental.run-stopped true
should generate an error because the unknown name occurs before the
"experimental". The amount of change to do this correctly hasn't
thrilled me, so I'm leaving this as-is for now.
<rdar://problem/
39223054>
Differential Revision: https://reviews.llvm.org/D45348
llvm-svn: 331315
Farhana Aleen [Tue, 1 May 2018 21:41:12 +0000 (21:41 +0000)]
[AMDGPU] Support horizontal vectorization.
Author: FarhanaAleen
Reviewed By: rampitec, arsenm
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D46213
llvm-svn: 331313
David Bolvansky [Tue, 1 May 2018 21:35:32 +0000 (21:35 +0000)]
[CFLGraph][NFC] Simplify/reorder switch in visitConstantExpr
Reviewers: hfinkel, efriedma, spatel, dsanders, Danil, rjmccall
Reviewed By: rjmccall
Subscribers: dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D46259
llvm-svn: 331312
Sanjay Patel [Tue, 1 May 2018 21:02:09 +0000 (21:02 +0000)]
[AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compare
and (or (lshr X, C), ...), 1 --> (X & C') != 0
I initially thought about implementing the minimal pattern in instcombine as mentioned here:
https://bugs.llvm.org/show_bug.cgi?id=37098#c6
...but we need to do better to catch the more general sequence from the motivating test
(more than 2 bits in the compare). And a test-suite run with statistics showed that this
pattern only happened 2 times currently. It would potentially happen more often if
reassociation worked better (D45842), but it's probably still not too frequent?
This is small enough that I didn't see a need to create a whole new class/file within
AggressiveInstCombine. There are likely other relatively small matchers like what was
discussed in D44266 that would slide under foldUnusualPatterns() (name suggestions welcome).
We could potentially also consolidate matchers for ctpop, bswap, etc under here.
Differential Revision: https://reviews.llvm.org/D45986
llvm-svn: 331311
Matt Morehouse [Tue, 1 May 2018 21:01:53 +0000 (21:01 +0000)]
[libFuzzer] Report at most one crash per input.
Summary:
Fixes https://github.com/google/sanitizers/issues/788/, a deadlock
caused by multiple crashes happening at the same time. Before printing
a crash report, we now test and set an atomic flag. If the flag was
already set, the crash handler returns immediately.
Reviewers: kcc
Reviewed By: kcc
Subscribers: llvm-commits, kubamracek
Differential Revision: https://reviews.llvm.org/D46277
llvm-svn: 331310
Sanjay Patel [Tue, 1 May 2018 20:55:03 +0000 (20:55 +0000)]
[AggressiveInstCombine] add more bitfield test patterns; NFC
Add another baseline for D45986 and a pattern that won't be
matched with that patch.
llvm-svn: 331309
Sanjay Patel [Tue, 1 May 2018 20:53:44 +0000 (20:53 +0000)]
[PhaseOrdering] add tests for bittest patterns from bitfields; NFC
As mentioned in D45986, there's a potential ordering dependency
between instcombine and aggressive-instcombine for detecting these,
so I'm adding a few tests to confirm that the expected folds occur
using -O3 (because aggressive-instcombine only runs at -O3 currently).
llvm-svn: 331308
Jessica Paquette [Tue, 1 May 2018 20:49:42 +0000 (20:49 +0000)]
Create a MachineBasicBlock for created IR-level BasicBlock
While running the lit tests for the most recent version of D45916
(https://reviews.llvm.org/D45916), I found that a couple tests for this pass
suddenly started segfaulting. Since the outliner wasn't actually doing anything
to the code in either of these tests I got curious.
I found that the pass doesn’t completely create the machine-level constructs
necessary to actually add a MachineFunction and MachineBasicBlock to the
module. This patch adds in those missing bits. After this, adding the
outliner before this pass won’t cause it to segfault.
You can recreate this behaviour by adding the MachineOutliner directly before
the pass and having it return false immediately.
https://reviews.llvm.org/D46330
llvm-svn: 331307
Shoaib Meenai [Tue, 1 May 2018 20:45:25 +0000 (20:45 +0000)]
[libclang] Fix the type of 'int (Foo);'
libclang exposes the type of 'int (Foo);' (a global variable of type int
called Foo) as CXType_Unexposed. This is because Clang represents Foo's
type as ParenType{BuiltinType{Int}}, and libclang does not handle
ParenType.
Make libclang return CXType_Int as the type of 'int (Foo);' by
unwrapping ParenType transparently.
Patch by Matt Glazar.
Differential Revision: https://reviews.llvm.org/D45713
llvm-svn: 331306
Shoaib Meenai [Tue, 1 May 2018 20:38:05 +0000 (20:38 +0000)]
[ARM] Remove redundant #if in test. NFC
Both sides of this #if #include the same file. Drop the #if, leaving only the #include.
Patch by Matt Glazar.
Differential Revision: https://reviews.llvm.org/D45779
llvm-svn: 331305
Eli Friedman [Tue, 1 May 2018 20:00:14 +0000 (20:00 +0000)]
[AArch64] Add more tests for 64-bit immediate lowering.
This adds a some more tests, and adds some notes to tests which are using
a suboptimal lowering.
The constants with suboptimal lowerings seem to be relatively rare in
practice, but it might be a fun project to work on improvements.
llvm-svn: 331304
Vedant Kumar [Tue, 1 May 2018 19:51:15 +0000 (19:51 +0000)]
[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)
The logic for this combine is almost identical to the logic for a
(sext (sextload x)) combine.
This commit factors out the logic so it can be shared by both combines,
and corrects the SDLoc assigned in the zext version of the combine.
Prior to this patch, for the given test case, we would apply the
location associated with the udiv instruction to instructions which
perform the load.
Part of: llvm.org/PR37262
llvm-svn: 331303
Vedant Kumar [Tue, 1 May 2018 19:51:15 +0000 (19:51 +0000)]
[DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N)
Prior to this patch, for the given test case, we would apply the
location associated with the sdiv instruction to instructions which
perform the load.
Part of: llvm.org/PR37262.
Differential Revision: https://reviews.llvm.org/D46222
llvm-svn: 331302
Vedant Kumar [Tue, 1 May 2018 19:29:15 +0000 (19:29 +0000)]
[DAGCombiner] Change the SDLoc on split extloads (2/N)
In DAGCombiner, we try to simplify this pattern:
([s|z]ext (load ...))
Conceptually, a new extload which is created while splitting the load
should have the same debug location as the load.
Making this change affects the IROrder of the new load, causing some
test case churn.
In practice, the new location is never different from the location of
the [s|z]ext, at least not during check-llvm or a stage2 build.
Part of: llvm.org/PR37262
Differential Revision: https://reviews.llvm.org/D46156
llvm-svn: 331301
Vedant Kumar [Tue, 1 May 2018 19:26:15 +0000 (19:26 +0000)]
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
Setting the right SDLoc on a newly-created zextload fixes a line table
bug which resulted in non-linear stepping behavior.
Several backend tests contained CHECK lines which relied on the IROrder
inherited from the wrong SDLoc. This patch breaks that dependence where
feasbile and regenerates test cases where not.
In some cases, changing a node's IROrder may alter register allocation
and spill behavior. This can affect performance. I have chosen not to
prevent this by applying a "known good" IROrder to SDLocs, as this may
hide a more general bug in the scheduler, or cause regressions on other
test inputs.
rdar://
33755881, Part of: llvm.org/PR37262
Differential Revision: https://reviews.llvm.org/D45995
llvm-svn: 331300
Richard Smith [Tue, 1 May 2018 18:50:15 +0000 (18:50 +0000)]
Fix bogus MSVC char8_t mangling.
This appears to have been caused by a bad automatic svn merge with r330225
attaching the 'case' label to the wrong block of code. :(
llvm-svn: 331299
Konstantin Zhuravlyov [Tue, 1 May 2018 18:47:48 +0000 (18:47 +0000)]
AMDGPU: Remove remnants of gfx901 (it was deprecated some time ago)
llvm-svn: 331298
Zinovy Nis [Tue, 1 May 2018 18:46:32 +0000 (18:46 +0000)]
[clang-tidy][modernize-raw-string-literal] Don't replace upper ASCII with raw literals
It's useless and not safe to replace UTF-8 encoded with escaped ASCII to raw UTF-8 chars:
"\xE2\x98\x83" ---> <snowman>
So don't do it.
llvm-svn: 331297
Saleem Abdulrasool [Tue, 1 May 2018 18:40:42 +0000 (18:40 +0000)]
Driver: fix an assertion with `-print-prog-name=`
Fix an assertion when -print-prog-name= is invoked without parameter.
Returns an empty string.
Patch by Christian Bruel!
llvm-svn: 331296
Roman Lebedev [Tue, 1 May 2018 18:40:15 +0000 (18:40 +0000)]
[compiler-rt][X86][AMD][Bulldozer] Fix Bulldozer Model 2 detection.
Summary:
The compiler-rt side of D46314
I have discovered an issue by accident.
```
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 8
On-line CPU(s) list: 0-7
Thread(s) per core: 2
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: AuthenticAMD
CPU family: 21
Model: 2
Model name: AMD FX(tm)-8350 Eight-Core Processor
Stepping: 0
CPU MHz: 3584.018
CPU max MHz: 4000.0000
CPU min MHz: 1400.0000
BogoMIPS: 8027.22
Virtualization: AMD-V
L1d cache: 16K
L1i cache: 64K
L2 cache: 2048K
L3 cache: 8192K
NUMA node0 CPU(s): 0-7
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb cpb hw_pstate vmmcall bmi1 arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold
```
So this is model-2 bulldozer AMD CPU.
GCC agrees:
```
$ echo | gcc -E - -march=native -###
<...>
/usr/lib/gcc/x86_64-linux-gnu/7/cc1 -E -quiet -imultiarch x86_64-linux-gnu - "-march=bdver2" -mmmx -mno-3dnow -msse -msse2 -msse3 -mssse3 -msse4a -mcx16 -msahf -mno-movbe -maes -mno-sha -mpclmul -mpopcnt -mabm -mlwp -mfma -mfma4 -mxop -mbmi -mno-sgx -mno-bmi2 -mtbm -mavx -mno-avx2 -msse4.2 -msse4.1 -mlzcnt -mno-rtm -mno-hle -mno-rdrnd -mf16c -mno-fsgsbase -mno-rdseed -mprfchw -mno-adx -mfxsr -mxsave -mno-xsaveopt -mno-avx512f -mno-avx512er -mno-avx512cd -mno-avx512pf -mno-prefetchwt1 -mno-clflushopt -mno-xsavec -mno-xsaves -mno-avx512dq -mno-avx512bw -mno-avx512vl -mno-avx512ifma -mno-avx512vbmi -mno-avx5124fmaps -mno-avx5124vnniw -mno-clwb -mno-mwaitx -mno-clzero -mno-pku -mno-rdpid --param "l1-cache-size=16" --param "l1-cache-line-size=64" --param "l2-cache-size=2048" "-mtune=bdver2"
<...>
```
But clang does not: (look for `bdver1`)
```
$ echo | clang -E - -march=native -###
clang version 7.0.0- (trunk)
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir: /usr/local/bin
"/usr/lib/llvm-7/bin/clang" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-E" "-disable-free" "-disable-llvm-verifier" "-discard-value-names" "-main-file-name" "-" "-mrelocation-model" "static" "-mthread-model" "posix" "-mdisable-fp-elim" "-fmath-errno" "-masm-verbose" "-mconstructor-aliases" "-munwind-tables" "-fuse-init-array" "-target-cpu" "bdver1" "-target-feature" "+sse2" "-target-feature" "+cx16" "-target-feature" "+sahf" "-target-feature" "+tbm" "-target-feature" "-avx512ifma" "-target-feature" "-sha" "-target-feature" "-gfni" "-target-feature" "+fma4" "-target-feature" "-vpclmulqdq" "-target-feature" "+prfchw" "-target-feature" "-bmi2" "-target-feature" "-cldemote" "-target-feature" "-fsgsbase" "-target-feature" "-xsavec" "-target-feature" "+popcnt" "-target-feature" "+aes" "-target-feature" "-avx512bitalg" "-target-feature" "-xsaves" "-target-feature" "-avx512er" "-target-feature" "-avx512vnni" "-target-feature" "-avx512vpopcntdq" "-target-feature" "-clwb" "-target-feature" "-avx512f" "-target-feature" "-clzero" "-target-feature" "-pku" "-target-feature" "+mmx" "-target-feature" "+lwp" "-target-feature" "-rdpid" "-target-feature" "+xop" "-target-feature" "-rdseed" "-target-feature" "-waitpkg" "-target-feature" "-ibt" "-target-feature" "+sse4a" "-target-feature" "-avx512bw" "-target-feature" "-clflushopt" "-target-feature" "+xsave" "-target-feature" "-avx512vbmi2" "-target-feature" "-avx512vl" "-target-feature" "-avx512cd" "-target-feature" "+avx" "-target-feature" "-vaes" "-target-feature" "-rtm" "-target-feature" "+fma" "-target-feature" "+bmi" "-target-feature" "-rdrnd" "-target-feature" "-mwaitx" "-target-feature" "+sse4.1" "-target-feature" "+sse4.2" "-target-feature" "-avx2" "-target-feature" "-wbnoinvd" "-target-feature" "+sse" "-target-feature" "+lzcnt" "-target-feature" "+pclmul" "-target-feature" "-prefetchwt1" "-target-feature" "+f16c" "-target-feature" "+ssse3" "-target-feature" "-sgx" "-target-feature" "-shstk" "-target-feature" "+cmov" "-target-feature" "-avx512vbmi" "-target-feature" "-movbe" "-target-feature" "-xsaveopt" "-target-feature" "-avx512dq" "-target-feature" "-adx" "-target-feature" "-avx512pf" "-target-feature" "+sse3" "-dwarf-column-info" "-debugger-tuning=gdb" "-resource-dir" "/usr/lib/llvm-7/lib/clang/7.0.0" "-internal-isystem" "/usr/local/include" "-internal-isystem" "/usr/lib/llvm-7/lib/clang/7.0.0/include" "-internal-externc-isystem" "/usr/include/x86_64-linux-gnu" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-fdebug-compilation-dir" "/build/llvm-build-Clang-release" "-ferror-limit" "19" "-fmessage-length" "271" "-fobjc-runtime=gcc" "-fdiagnostics-show-option" "-fcolor-diagnostics" "-o" "-" "-x" "c" "-"
```
So clang, unlike gcc, considers this to be `bdver1`.
After some digging, i've come across `getAMDProcessorTypeAndSubtype()` in `Host.cpp`.
I have added the following debug printf after the call to that function in `sys::getHostCPUName()`:
```
errs() << "Family " << Family << " Model " << Model << " Type " << Type "\n";
```
Which produced:
```
Family 21 Model 2 Type 5
```
Which matches the `lscpu` output.
As it was pointed in the review by @craig.topper:
>>! In D46314#1084123, @craig.topper wrote:
> I dont' think this is right. Here is what I found on wikipedia. https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures.
>
> AMD Bulldozer Family 15h - the successor of 10h/K10. Bulldozer is designed for processors in the 10 to 220W category, implementing XOP, FMA4 and CVT16 instruction sets. Orochi was the first design which implemented it. For Bulldozer, CPUID model numbers are 00h and 01h.
> AMD Piledriver Family 15h (2nd-gen) - successor to Bulldozer. CPUID model numbers are 02h (earliest "Vishera" Piledrivers) and 10h-1Fh.
> AMD Steamroller Family 15h (3rd-gen) - third-generation Bulldozer derived core. CPUID model numbers are 30h-3Fh.
> AMD Excavator Family 15h (4th-gen) - fourth-generation Bulldozer derived core. CPUID model numbers are 60h-6Fh, later updated revisions have model numbers 70h-7Fh.
>
>
> So there's a weird exception where model 2 should go with 0x10-0x1f.
Though It does not help that the code can't be tested at the moment.
With this logical change, the `bdver2` is properly detected.
```
$ echo | /build/llvm-build-Clang-release/bin/clang -E - -march=native -###
clang version 7.0.0 (trunk 331249) (llvm/trunk 331256)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /build/llvm-build-Clang-release/bin
"/build/llvm-build-Clang-release/bin/clang-7" "-cc1" "-triple" "x86_64-unknown-linux-gnu" "-E" "-disable-free" "-main-file-name" "-" "-mrelocation-model" "static" "-mthread-model" "posix" "-mdisable-fp-elim" "-fmath-errno" "-masm-verbose" "-mconstructor-aliases" "-munwind-tables" "-fuse-init-array" "-target-cpu" "bdver2" "-target-feature" "+sse2" "-target-feature" "+cx16" "-target-feature" "+sahf" "-target-feature" "+tbm" "-target-feature" "-avx512ifma" "-target-feature" "-sha" "-target-feature" "-gfni" "-target-feature" "+fma4" "-target-feature" "-vpclmulqdq" "-target-feature" "+prfchw" "-target-feature" "-bmi2" "-target-feature" "-cldemote" "-target-feature" "-fsgsbase" "-target-feature" "-xsavec" "-target-feature" "+popcnt" "-target-feature" "+aes" "-target-feature" "-avx512bitalg" "-target-feature" "-movdiri" "-target-feature" "-xsaves" "-target-feature" "-avx512er" "-target-feature" "-avx512vnni" "-target-feature" "-avx512vpopcntdq" "-target-feature" "-clwb" "-target-feature" "-avx512f" "-target-feature" "-clzero" "-target-feature" "-pku" "-target-feature" "+mmx" "-target-feature" "+lwp" "-target-feature" "-rdpid" "-target-feature" "+xop" "-target-feature" "-rdseed" "-target-feature" "-waitpkg" "-target-feature" "-movdir64b" "-target-feature" "-ibt" "-target-feature" "+sse4a" "-target-feature" "-avx512bw" "-target-feature" "-clflushopt" "-target-feature" "+xsave" "-target-feature" "-avx512vbmi2" "-target-feature" "-avx512vl" "-target-feature" "-avx512cd" "-target-feature" "+avx" "-target-feature" "-vaes" "-target-feature" "-rtm" "-target-feature" "+fma" "-target-feature" "+bmi" "-target-feature" "-rdrnd" "-target-feature" "-mwaitx" "-target-feature" "+sse4.1" "-target-feature" "+sse4.2" "-target-feature" "-avx2" "-target-feature" "-wbnoinvd" "-target-feature" "+sse" "-target-feature" "+lzcnt" "-target-feature" "+pclmul" "-target-feature" "-prefetchwt1" "-target-feature" "+f16c" "-target-feature" "+ssse3" "-target-feature" "-sgx" "-target-feature" "-shstk" "-target-feature" "+cmov" "-target-feature" "-avx512vbmi" "-target-feature" "-movbe" "-target-feature" "-xsaveopt" "-target-feature" "-avx512dq" "-target-feature" "-adx" "-target-feature" "-avx512pf" "-target-feature" "+sse3" "-dwarf-column-info" "-debugger-tuning=gdb" "-resource-dir" "/build/llvm-build-Clang-release/lib/clang/7.0.0" "-internal-isystem" "/usr/local/include" "-internal-isystem" "/build/llvm-build-Clang-release/lib/clang/7.0.0/include" "-internal-externc-isystem" "/usr/include/x86_64-linux-gnu" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-fdebug-compilation-dir" "/build/llvm-build-Clang-release" "-ferror-limit" "19" "-fmessage-length" "271" "-fobjc-runtime=gcc" "-fdiagnostics-show-option" "-fcolor-diagnostics" "-o" "-" "-x" "c" "-"
```
Reviewers: craig.topper, asbirlea, rnk, GGanesh, andreadb
Reviewed By: craig.topper
Subscribers: sdardis, dberris, aprantl, arichardson, JDevlieghere, #sanitizers, llvm-commits, cfe-commits, craig.topper
Differential Revision: https://reviews.llvm.org/D46323
llvm-svn: 331295
Roman Lebedev [Tue, 1 May 2018 18:39:31 +0000 (18:39 +0000)]
[X86][AMD][Bulldozer] Fix Bulldozer Model 2 detection.
Summary:
I have discovered an issue by accident.
```
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 8
On-line CPU(s) list: 0-7
Thread(s) per core: 2
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: AuthenticAMD
CPU family: 21
Model: 2
Model name: AMD FX(tm)-8350 Eight-Core Processor
Stepping: 0
CPU MHz: 3584.018
CPU max MHz: 4000.0000
CPU min MHz: 1400.0000
BogoMIPS: 8027.22
Virtualization: AMD-V
L1d cache: 16K
L1i cache: 64K
L2 cache: 2048K
L3 cache: 8192K
NUMA node0 CPU(s): 0-7
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb cpb hw_pstate vmmcall bmi1 arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold
```
So this is model-2 bulldozer AMD CPU.
GCC agrees:
```
$ echo | gcc -E - -march=native -###
<...>
/usr/lib/gcc/x86_64-linux-gnu/7/cc1 -E -quiet -imultiarch x86_64-linux-gnu - "-march=bdver2" -mmmx -mno-3dnow -msse -msse2 -msse3 -mssse3 -msse4a -mcx16 -msahf -mno-movbe -maes -mno-sha -mpclmul -mpopcnt -mabm -mlwp -mfma -mfma4 -mxop -mbmi -mno-sgx -mno-bmi2 -mtbm -mavx -mno-avx2 -msse4.2 -msse4.1 -mlzcnt -mno-rtm -mno-hle -mno-rdrnd -mf16c -mno-fsgsbase -mno-rdseed -mprfchw -mno-adx -mfxsr -mxsave -mno-xsaveopt -mno-avx512f -mno-avx512er -mno-avx512cd -mno-avx512pf -mno-prefetchwt1 -mno-clflushopt -mno-xsavec -mno-xsaves -mno-avx512dq -mno-avx512bw -mno-avx512vl -mno-avx512ifma -mno-avx512vbmi -mno-avx5124fmaps -mno-avx5124vnniw -mno-clwb -mno-mwaitx -mno-clzero -mno-pku -mno-rdpid --param "l1-cache-size=16" --param "l1-cache-line-size=64" --param "l2-cache-size=2048" "-mtune=bdver2"
<...>
```
But clang does not: (look for `bdver1`)
```
$ echo | clang -E - -march=native -###
clang version 7.0.0- (trunk)
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir: /usr/local/bin
"/usr/lib/llvm-7/bin/clang" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-E" "-disable-free" "-disable-llvm-verifier" "-discard-value-names" "-main-file-name" "-" "-mrelocation-model" "static" "-mthread-model" "posix" "-mdisable-fp-elim" "-fmath-errno" "-masm-verbose" "-mconstructor-aliases" "-munwind-tables" "-fuse-init-array" "-target-cpu" "bdver1" "-target-feature" "+sse2" "-target-feature" "+cx16" "-target-feature" "+sahf" "-target-feature" "+tbm" "-target-feature" "-avx512ifma" "-target-feature" "-sha" "-target-feature" "-gfni" "-target-feature" "+fma4" "-target-feature" "-vpclmulqdq" "-target-feature" "+prfchw" "-target-feature" "-bmi2" "-target-feature" "-cldemote" "-target-feature" "-fsgsbase" "-target-feature" "-xsavec" "-target-feature" "+popcnt" "-target-feature" "+aes" "-target-feature" "-avx512bitalg" "-target-feature" "-xsaves" "-target-feature" "-avx512er" "-target-feature" "-avx512vnni" "-target-feature" "-avx512vpopcntdq" "-target-feature" "-clwb" "-target-feature" "-avx512f" "-target-feature" "-clzero" "-target-feature" "-pku" "-target-feature" "+mmx" "-target-feature" "+lwp" "-target-feature" "-rdpid" "-target-feature" "+xop" "-target-feature" "-rdseed" "-target-feature" "-waitpkg" "-target-feature" "-ibt" "-target-feature" "+sse4a" "-target-feature" "-avx512bw" "-target-feature" "-clflushopt" "-target-feature" "+xsave" "-target-feature" "-avx512vbmi2" "-target-feature" "-avx512vl" "-target-feature" "-avx512cd" "-target-feature" "+avx" "-target-feature" "-vaes" "-target-feature" "-rtm" "-target-feature" "+fma" "-target-feature" "+bmi" "-target-feature" "-rdrnd" "-target-feature" "-mwaitx" "-target-feature" "+sse4.1" "-target-feature" "+sse4.2" "-target-feature" "-avx2" "-target-feature" "-wbnoinvd" "-target-feature" "+sse" "-target-feature" "+lzcnt" "-target-feature" "+pclmul" "-target-feature" "-prefetchwt1" "-target-feature" "+f16c" "-target-feature" "+ssse3" "-target-feature" "-sgx" "-target-feature" "-shstk" "-target-feature" "+cmov" "-target-feature" "-avx512vbmi" "-target-feature" "-movbe" "-target-feature" "-xsaveopt" "-target-feature" "-avx512dq" "-target-feature" "-adx" "-target-feature" "-avx512pf" "-target-feature" "+sse3" "-dwarf-column-info" "-debugger-tuning=gdb" "-resource-dir" "/usr/lib/llvm-7/lib/clang/7.0.0" "-internal-isystem" "/usr/local/include" "-internal-isystem" "/usr/lib/llvm-7/lib/clang/7.0.0/include" "-internal-externc-isystem" "/usr/include/x86_64-linux-gnu" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-fdebug-compilation-dir" "/build/llvm-build-Clang-release" "-ferror-limit" "19" "-fmessage-length" "271" "-fobjc-runtime=gcc" "-fdiagnostics-show-option" "-fcolor-diagnostics" "-o" "-" "-x" "c" "-"
```
So clang, unlike gcc, considers this to be `bdver1`.
After some digging, i've come across `getAMDProcessorTypeAndSubtype()` in `Host.cpp`.
I have added the following debug printf after the call to that function in `sys::getHostCPUName()`:
```
errs() << "Family " << Family << " Model " << Model << " Type " << Type "\n";
```
Which produced:
```
Family 21 Model 2 Type 5
```
Which matches the `lscpu` output.
As it was pointed in the review by @craig.topper:
>>! In D46314#1084123, @craig.topper wrote:
> I dont' think this is right. Here is what I found on wikipedia. https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures.
>
> AMD Bulldozer Family 15h - the successor of 10h/K10. Bulldozer is designed for processors in the 10 to 220W category, implementing XOP, FMA4 and CVT16 instruction sets. Orochi was the first design which implemented it. For Bulldozer, CPUID model numbers are 00h and 01h.
> AMD Piledriver Family 15h (2nd-gen) - successor to Bulldozer. CPUID model numbers are 02h (earliest "Vishera" Piledrivers) and 10h-1Fh.
> AMD Steamroller Family 15h (3rd-gen) - third-generation Bulldozer derived core. CPUID model numbers are 30h-3Fh.
> AMD Excavator Family 15h (4th-gen) - fourth-generation Bulldozer derived core. CPUID model numbers are 60h-6Fh, later updated revisions have model numbers 70h-7Fh.
>
>
> So there's a weird exception where model 2 should go with 0x10-0x1f.
Though It does not help that the code can't be tested at the moment.
With this logical change, the `bdver2` is properly detected.
```
$ echo | /build/llvm-build-Clang-release/bin/clang -E - -march=native -###
clang version 7.0.0 (trunk 331249) (llvm/trunk 331256)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /build/llvm-build-Clang-release/bin
"/build/llvm-build-Clang-release/bin/clang-7" "-cc1" "-triple" "x86_64-unknown-linux-gnu" "-E" "-disable-free" "-main-file-name" "-" "-mrelocation-model" "static" "-mthread-model" "posix" "-mdisable-fp-elim" "-fmath-errno" "-masm-verbose" "-mconstructor-aliases" "-munwind-tables" "-fuse-init-array" "-target-cpu" "bdver2" "-target-feature" "+sse2" "-target-feature" "+cx16" "-target-feature" "+sahf" "-target-feature" "+tbm" "-target-feature" "-avx512ifma" "-target-feature" "-sha" "-target-feature" "-gfni" "-target-feature" "+fma4" "-target-feature" "-vpclmulqdq" "-target-feature" "+prfchw" "-target-feature" "-bmi2" "-target-feature" "-cldemote" "-target-feature" "-fsgsbase" "-target-feature" "-xsavec" "-target-feature" "+popcnt" "-target-feature" "+aes" "-target-feature" "-avx512bitalg" "-target-feature" "-movdiri" "-target-feature" "-xsaves" "-target-feature" "-avx512er" "-target-feature" "-avx512vnni" "-target-feature" "-avx512vpopcntdq" "-target-feature" "-clwb" "-target-feature" "-avx512f" "-target-feature" "-clzero" "-target-feature" "-pku" "-target-feature" "+mmx" "-target-feature" "+lwp" "-target-feature" "-rdpid" "-target-feature" "+xop" "-target-feature" "-rdseed" "-target-feature" "-waitpkg" "-target-feature" "-movdir64b" "-target-feature" "-ibt" "-target-feature" "+sse4a" "-target-feature" "-avx512bw" "-target-feature" "-clflushopt" "-target-feature" "+xsave" "-target-feature" "-avx512vbmi2" "-target-feature" "-avx512vl" "-target-feature" "-avx512cd" "-target-feature" "+avx" "-target-feature" "-vaes" "-target-feature" "-rtm" "-target-feature" "+fma" "-target-feature" "+bmi" "-target-feature" "-rdrnd" "-target-feature" "-mwaitx" "-target-feature" "+sse4.1" "-target-feature" "+sse4.2" "-target-feature" "-avx2" "-target-feature" "-wbnoinvd" "-target-feature" "+sse" "-target-feature" "+lzcnt" "-target-feature" "+pclmul" "-target-feature" "-prefetchwt1" "-target-feature" "+f16c" "-target-feature" "+ssse3" "-target-feature" "-sgx" "-target-feature" "-shstk" "-target-feature" "+cmov" "-target-feature" "-avx512vbmi" "-target-feature" "-movbe" "-target-feature" "-xsaveopt" "-target-feature" "-avx512dq" "-target-feature" "-adx" "-target-feature" "-avx512pf" "-target-feature" "+sse3" "-dwarf-column-info" "-debugger-tuning=gdb" "-resource-dir" "/build/llvm-build-Clang-release/lib/clang/7.0.0" "-internal-isystem" "/usr/local/include" "-internal-isystem" "/build/llvm-build-Clang-release/lib/clang/7.0.0/include" "-internal-externc-isystem" "/usr/include/x86_64-linux-gnu" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-fdebug-compilation-dir" "/build/llvm-build-Clang-release" "-ferror-limit" "19" "-fmessage-length" "271" "-fobjc-runtime=gcc" "-fdiagnostics-show-option" "-fcolor-diagnostics" "-o" "-" "-x" "c" "-"
```
Reviewers: craig.topper, GBuella, RKSimon, asbirlea, echristo, bkramer, spatel, andreadb, GGanesh
Reviewed By: craig.topper
Subscribers: sdardis, aprantl, arichardson, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D46314
llvm-svn: 331294
Simon Pilgrim [Tue, 1 May 2018 18:22:53 +0000 (18:22 +0000)]
[X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM scheduler classes
llvm-svn: 331293
Danil Malyshev [Tue, 1 May 2018 18:14:36 +0000 (18:14 +0000)]
Update existed CodeGen TBAA tests
Reviewers: hfinkel, kosarev, rjmccall
Reviewed By: rjmccall
Differential Revision: https://reviews.llvm.org/D44616
llvm-svn: 331292
David Blaikie [Tue, 1 May 2018 18:08:45 +0000 (18:08 +0000)]
llvm-symbolizer: Handle function definitions nested within other functions
LLVM always puts function definition DIEs at the top level, but under
some circumstances GCC does not (at least in this case with member
functions of a function-local type).
To ensure that doesn't appear as though the local type's member function
is unduly inlined within the outer function - ensure the inline
discovery DIE parent walk stops at the first DW_TAG_subprogram.
llvm-svn: 331291
Simon Pilgrim [Tue, 1 May 2018 18:06:07 +0000 (18:06 +0000)]
[X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt into XMM and YMM/ZMM scheduler classes
llvm-svn: 331290
Wei Mi [Tue, 1 May 2018 17:19:25 +0000 (17:19 +0000)]
Use no-op opt run to eliminate the difference in bb pred comment, per chandler's suggestion. It is better than using sed on portability.
llvm-svn: 331286
Jonas Devlieghere [Tue, 1 May 2018 17:08:09 +0000 (17:08 +0000)]
Revert "[lit] Replace generator expressions in lit.site.cfg"
Using GENERATE breaks generators that support multiple configurations,
e.g. MSVC. Reverting for now until we find a better solution.
llvm-svn: 331285
Konstantin Zhuravlyov [Tue, 1 May 2018 17:05:44 +0000 (17:05 +0000)]
AMDGPU: Add missing gfx904 tests
llvm-svn: 331284
Simon Pilgrim [Tue, 1 May 2018 16:50:16 +0000 (16:50 +0000)]
[X86] Split WriteFCmp into XMM and YMM/ZMM scheduler classes
Removes more WriteFCmp InstRW overrides
llvm-svn: 331283
Saleem Abdulrasool [Tue, 1 May 2018 16:46:05 +0000 (16:46 +0000)]
Support: assume `std::is_final` with MSVC
According to MSDN, Visual Studio 2015 included support for
std::is_final. Additionally, a bug in the Visual Studio compiler results
in the incorrect definition of __cplusplus. Due to the conditions in the
else case not holding either, we end up with no definition of
LLVM_IS_FINAL when building with MSVC. This has not yet been a problem
with LLVM/clang, however, the uses of LLVM_IS_FINAL is more prevalent in
swift, which uses the ADT library and causes issues when building lldb
with Visual Studio.
Workaround the issue by always assuming that the definition of
std::is_final is available with Visual Studio. Since we currently
require VS 2015+ for building LLVM, this condition should always hold
for the users in LLVM/clang (and for swift).
llvm-svn: 331282
Daniel Neilson [Tue, 1 May 2018 16:40:45 +0000 (16:40 +0000)]
[LV] Move test/Transforms/LoopVectorize/pr23997.ll
Summary:
This fixes a build break with r331269.
test/Transforms/LoopVectorize/pr23997.ll
should be in:
test/Transforms/LoopVectorize/X86/pr23997.ll
llvm-svn: 331281
Wei Mi [Tue, 1 May 2018 16:37:27 +0000 (16:37 +0000)]
Fix the sed command in test which doesn't work well on BSD.
llvm-svn: 331280
Sam Clegg [Tue, 1 May 2018 16:35:16 +0000 (16:35 +0000)]
[WebAssembly] llvm-readobj: display symbols names in relocations
Differential Revision: https://reviews.llvm.org/D46296
llvm-svn: 331279
Konstantin Zhuravlyov [Tue, 1 May 2018 16:34:29 +0000 (16:34 +0000)]
AMDGPU/NFC: Use enum values for first/last machs instead of numbers
llvm-svn: 331278
Jonas Devlieghere [Tue, 1 May 2018 16:19:48 +0000 (16:19 +0000)]
[lit] Replace generator expressions in lit.site.cfg
The lit site configuration for the test suite can contain generator
expressions such as $<TARGET_FILE:debugserver> that need to be
substituted.
llvm-svn: 331277
Simon Pilgrim [Tue, 1 May 2018 16:13:42 +0000 (16:13 +0000)]
[X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classes
Removes more WriteFAdd InstRW overrides
llvm-svn: 331276
Adrian Prantl [Tue, 1 May 2018 16:10:38 +0000 (16:10 +0000)]
Remove @brief commands from doxygen comments, too.
This is a follow-up to r331272.
We've been running doxygen with the autobrief option for a couple of
years now. This makes the \brief markers into our comments
redundant. Since they are a visual distraction and we don't want to
encourage more \brief markers in new code either, this patch removes
them all.
Patch produced by
for i in $(git grep -l '\@brief'); do perl -pi -e 's/\@brief //g' $i & done
https://reviews.llvm.org/D46290
llvm-svn: 331275
Matthew Simpson [Tue, 1 May 2018 15:59:26 +0000 (15:59 +0000)]
[SLP] Add additional test for transposable binary operations with reuse
llvm-svn: 331274
Simon Pilgrim [Tue, 1 May 2018 15:57:17 +0000 (15:57 +0000)]
[X86] Convert all uses of WriteFAdd to X86SchedWriteWidths.
In preparation of splitting WriteFAdd by vector width.
llvm-svn: 331273
Adrian Prantl [Tue, 1 May 2018 15:54:18 +0000 (15:54 +0000)]
Remove \brief commands from doxygen comments.
We've been running doxygen with the autobrief option for a couple of
years now. This makes the \brief markers into our comments
redundant. Since they are a visual distraction and we don't want to
encourage more \brief markers in new code either, this patch removes
them all.
Patch produced by
for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done
Differential Revision: https://reviews.llvm.org/D46290
llvm-svn: 331272
Sanjay Patel [Tue, 1 May 2018 15:43:36 +0000 (15:43 +0000)]
[DAG] add test to show FMF mismatch between IR and DAG; NFC
D45710 proposes to change this, but we have no test coverage
for the first step in this process.
llvm-svn: 331271