Arnd Bergmann [Tue, 22 Nov 2022 21:57:53 +0000 (22:57 +0100)]
Merge tag 'riscv-dt-for-v6.2-mw0' of https://git./linux/kernel/git/conor/linux into soc/dt
RISC-V DeviceTrees for v6.2
dt-bindings:
- new compatibles to support the StarFive VisionFive & thead CPU cores
- a fix for the PolarFire SoC's pwm binding, merged through my tree as
suggested by the PWM maintainers
Microchip:
- Non-urgent fix for the node address not matches the reg in a way that
the checkers don't complain about
- Add GPIO controlled LEDs for Icicle
- Support for the "CCC" clocks in the FPGA fabric. Previously these
used fixed-frequency clocks in the dt, but if which CCC is in use is
known, as in the v2022.09 Icicle Kit Reference Design, the rates can
be read dynamically. It's an "is known" as it *can* be set via
constraints in the FPGA tooling but does not have to be.
- A fix for the Icicle's pwm-cells
- Removal of some unused PCI clocks
StarFive:
- Addition of the VisionFive DT, which has been a long time coming!
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
riscv: dts: microchip: remove unused pcie clocks
riscv: dts: microchip: remove pcie node from the sev kit
riscv: dts: microchip: fix the icicle's #pwm-cells
dt-bindings: pwm: fix microchip corePWM's pwm-cells
riscv: dts: starfive: Add StarFive VisionFive V1 device tree
riscv: dts: starfive: Add common DT for JH7100 based boards
dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board
riscv: dts: microchip: fix memory node unit address for icicle
riscv: dts: microchip: icicle: Add GPIO controlled LEDs
riscv: dts: microchip: add the mpfs' fabric clock control
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:56:08 +0000 (11:56 +0100)]
Merge tag 'renesas-arm-dt-for-v6.2-tag2' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas ARM DT updates for v6.2 (take two)
- Timer (TMU and CMT) and quad Cortex-A76 CPU topology support for
the R-Car V4H SoC,
- Watchdog, L2 cache, and system controller support for the RZ/V2M
SoC on the RZ/V2M Evaluation Kit 2.0,
- Ethernet Switch and SERDES supports for the R-Car S4-8 SoC and the
Spider development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDES
arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
arm64: dts: renesas: r9a09g011: Add system controller node
arm64: dts: renesas: r8a779g0: Add CA76 operating points
arm64: dts: renesas: r8a779g0: Add CPU core clocks
arm64: dts: renesas: r8a779g0: Add CPUIdle support
arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
arm64: dts: renesas: r8a779g0: Add L3 cache controller
arm64: dts: renesas: r9a09g011: Add L2 Cache node
arm64: dts: renesas: rzv2mevk2: Enable watchdog
arm64: dts: renesas: r9a09g011: Add watchdog node
arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0
arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes
arm64: dts: renesas: r9a09g011: Fix I2C SoC specific strings
arm64: dts: renesas: rzg2l: Add missing cache-level properties
arm64: dts: renesas: r8a779g0: Add CMT node
arm64: dts: renesas: r9a09g011: Fix unit address format error
arm64: dts: renesas: white-hawk-cpu: Sort RWDT entry correctly
arm64: dts: renesas: r8a779g0: Add TMU nodes
arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
...
Link: https://lore.kernel.org/r/cover.1668788921.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:53:45 +0000 (11:53 +0100)]
Merge tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas RISC-V DT updates for v6.2
- Add initial support for the Renesas RZ/Five SoC and the Renesas
RZ/Five SMARC EVK development board.
* tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
MAINTAINERS: Add entry for Renesas RISC-V
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Link: https://lore.kernel.org/r/cover.1668788930.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:53:09 +0000 (11:53 +0100)]
Merge tag 'renesas-dt-bindings-for-v6.2-tag2' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.2 (take two)
- Document support for the Andes Technology AX45MP RISC-V CPU Core, as
used on the Renesas RZ/Five SoC,
- Document support for the Renesas RZ/V2M System Configuration.
* tag 'renesas-dt-bindings-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: riscv: Sort the CPU core list alphabetically
Link: https://lore.kernel.org/r/cover.1668788927.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:44:13 +0000 (11:44 +0100)]
Merge tag 'stm32-dt-for-v6.2-1' of git://git./linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.2, round 1
Highlights:
----------
- MPU:
- ST boards:
- Add MCP23017 IO expander support on stm32mp135f-dk board.
- Add stm32g0 support for USB typeC on stm32mp135f-dk
- Add USB (EHCI / OTG) on stm32mp135f-dk
- Add ADC support on stm32mp135f-dk
- Add USB2514B onboard hub on stm32mp157c-ev1
- DH:
- Fix severals Yaml DT validation issues
* tag 'stm32-dt-for-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (28 commits)
ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench board
ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk
ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13
ARM: dts: stm32: enable USB OTG in dual role mode on stm32mp135f-dk
ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13
ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk
ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk
ARM: dts: stm32: add fixed regulators to support usb on stm32mp135f-dk
ARM: dts: stm32: add USB OTG HS support on stm32mp131
ARM: dts: stm32: add UBSH EHCI and OHCI support on stm32mp131
ARM: dts: stm32: add USBPHYC and dual USB HS PHY support on stm32mp131
ARM: dts: stm32: add PWR fixed regulators on stm32mp131
ARM: dts: stm32: Fix AV96 WLAN regulator gpio property
ARM: dts: stm32: add adc support on stm32mp135f-dk
ARM: dts: stm32: add dummy vdd_adc regulator on stm32mp135f-dk
ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk
ARM: dts: stm32: add adc support to stm32mp13
ARM: dts: stm32: Drop MMCI interrupt-names
ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1
ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1
...
Link: https://lore.kernel.org/r/3235e5be-d89f-f76c-5e25-5d1210feb857@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:43:39 +0000 (11:43 +0100)]
Merge tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi into soc/dt
ARM64: DT: HiSilicon ARM64 DT updates for 6.2
- Add missing cache-level properties
* tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi:
arm64: dts: Update cache properties for hisilicon
Link: https://lore.kernel.org/r/63744D38.9010700@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:40:29 +0000 (11:40 +0100)]
Merge tag 'imx-dt64-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree update for 6.2:
- New device trees for i.MX8MM based Cloos PHG and WB15 SoM/EVK.
- A set of tqma8mpql/mba8mpxl changes, adding USB Host, PCIe, PWM fan
support.
- Rename DTB overlay source files from .dts to .dtso.
- A series from Frank Li to add USB, ADC, FlexSPI, LPSPI support for
i.MX8DXL.
- A couple of librem5-devkit changes, switching LED to use PWM and using
function and color properties for LED.
- Enable wakeup-source for USB PHY for i.MX8MM/N EVK.
- A set of random changes from Marcel Ziswiler to improve i.MX8M based
Verdin device trees.
- A series from Marek Vasut to update Data Modul i.MX8M Mini eDM SBC and
DH electronics i.MX8M Plus DHCOM, modeling PMIC to SNVS RTC clock
path, dropping QCA clk_out setup, adding bluetooth UART, etc.
- A bunch of changes from Peng Fan to add LPSPI, TPM etc for i.MX93,
update i.MX8MP/N EVK with UART, I2C addition.
- Update cache properties per DeviceTree Specification v0.3.
- Add gpio-ranges property for i.MX8DXL and i.MX8Q LSIO Subsystem.
- Misc small and random changes.
* tag 'imx-dt64-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (60 commits)
arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso
arm64: dts: imx8mm-evk: add vcc supply for pca6416
arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
arm64: dts: imx8mn-evk: enable uart1
arm64: dts: imx8mn-evk: add i2c gpio recovery settings
arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
arm64: dts: imx8mp-evk: enable I2C2 node
arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
arm64: dts: imx8mp-evk: enable uart1/3 ports
ARM64: dts: imx8mp-evk: add pwm support
arm64: dts: imx8mp: add mlmix power domain
arm64: dts: imx8mq: fix dtschema warning for imx7-csi
arm64: dts: Update cache properties for freescale
arm64: dts: imx8mm-phg: Add initial board support
arm64: dts: imx8qxp-ss-lsio: add gpio-ranges property
arm64: dts: imx8qm-ss-lsio: add gpio-ranges property
arm64: dts: imx8dxl-ss-lsio: add gpio-ranges property
arm64: dts: imx8dxl_evk: add lpspi0 support
arm64: dts: imx8dxl: add lpspi support
...
Link: https://lore.kernel.org/r/20221119125733.32719-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:08:01 +0000 (11:08 +0100)]
Merge tag 'imx-dt-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm device tree update for 6.2:
- New device tree for Kobo Aura 2 E-Boot reader which is built on i.MX6SL
SoC.
- Enable backlight and boost support for imx6sl-tolino-shine2hd.
- Enable CYTTSP5 touchscreen support for E60K02.
- Enable Silergy SY7636A EPD PMIC on imx7d-remarkable2 epaper tablet.
- Add watchdog property 'fsl,suspend-in-wait' for i.MX6UL Phytec Phycore
SoM to avoid watchdog triggering in 'freeze' low power mode.
- Correct the polarity of AT86RF233 reset line for vf610-zii-dev-rev-c
board.
- A bunch of Colibri device tree updates from Marcel Ziswiler and Philippe
Schenker, correct USBH_PEN property, remove spurious debounce property,
add USB dual-role switching, and some cosmetic change.
- Other small and random changes.
* tag 'imx-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: colibri-imx6ull: Enable dual-role switching
ARM: dts: imx: e60k02: Add touchscreen
ARM: dts: imx6qdl-sabre: Add mmc aliases
ARM: dts: imx6ul/ull: suspend i.MX6UL watchdog in wait mode
ARM: dts: imx7d-remarkable2: Enable silergy,sy7636a
ARM: dts: imx6sl-tolino-shine2hd: Add backlight boost
ARM: dts: imx6sl-tolino-shine2hd: Add backlight
ARM: dts: colibri-imx7: fix confusing naming
ARM: dts: colibri-imx6ull: add -hog to gpio hogs
ARM: dts: colibri-imx6ull: enable default peripherals
ARM: dts: colibri-imx6ull: keep peripherals disabled
ARM: dts: ls1021: correct indentation
ARM: dts: vf610-zii-dev-rev-c: fix polarity of at86rf233 reset line
ARM: dts: imx7-colibri: remove spurious debounce property
ARM: dts: colibri-imx6: specify usbh_pen gpio being active-low
ARM: dts: colibri-imx6: move vbus-supply to module level device tree
ARM: dts: colibri-imx6: usb dual-role switching
ARM: dts: imx: Add devicetree for Kobo Aura 2
Link: https://lore.kernel.org/r/20221119125733.32719-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:06:42 +0000 (11:06 +0100)]
Merge tag 'imx-bindings-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX dt-bindings update for 6.2:
- New vendor prefix for Cloos and InnoComm.
- New compatible for Cloos PHG board, InnoComm WB15 EVK and Kobo Aura 2.
- Improve snvs-lpgpr bindings schema regarding i.MX8M SNVS LPGRP
compatible strings.
- Improve fsl-imx-cspi bindings schema for i.MX8MP ECSPI.
- Add bindings schema for i.MX8M ANATOP device.
- Update SCU firmware resource ID header by syncing with the latest
available SCFW kit version 1.13.0.
* tag 'imx-bindings-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: fsl: Add an entry for Cloos PHG board
dt-bindings: vendor-prefixes: Add an entry for Cloos
dt-bindings: nvmem: snvs-lpgpr: Fix i.MX8M compatible strings
dt-bindings: spi: fsl-imx-cspi: update i.MX8MP binding
dt-bindings: arm: fsl: add compatible string for Kobo Aura 2
dt-bindings: clock: add i.MX8M Anatop
dt-bindings: arm: fsl: Add InnoComm WB15 EVK
dt-bindings: vendor-prefixes: Add prefix for InnoComm
dt-bindings: firmware: imx: sync with SCFW kit v1.13.0
Link: https://lore.kernel.org/r/20221119125733.32719-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:01:48 +0000 (11:01 +0100)]
Merge branch 'dt/dtbo-rename' of git://git./linux/kernel/git/robh/linux into soc/dt
* 'dt/dtbo-rename' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
kbuild: Cleanup DT Overlay intermediate files as appropriate
staging: pi433: overlay: Rename overlay source file from .dts to .dtso
of: overlay: rename overlay source files from .dts to .dtso
kbuild: Allow DTB overlays to built into .dtbo.S files
kbuild: Allow DTB overlays to built from .dtso named source files
Link: https://lore.kernel.org/r/20221118211103.GA1334449-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:57:29 +0000 (10:57 +0100)]
Merge tag 'sunxi-dt-for-6.2-1' of https://git./linux/kernel/git/sunxi/linux into soc/dt
- Added H616 USB node
- Enabled bluetooth on Pinebook A64
- Added f1c100s PWM, I2C, CIR and LRADC nodes
- Added USB HCI0 PHYs property to H3/H5
* tag 'sunxi-dt-for-6.2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0
ARM: dts: suniv: f1c100s: add LRADC node
ARM: dts: suniv: f1c100s: add CIR DT node
dt-bindings: media: IR: Add F1C100s IR compatible string
ARM: dts: suniv: f1c100s: add I2C DT nodes
ARM: dts: suniv: f1c100s: add PWM node
dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
arm64: dts: allwinner: a64: enable Bluetooth on Pinebook
arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
arm64: dts: allwinner: h616: Add USB nodes
dt-bindings: usb: Add H616 compatible string
ARM: dts: axp22x/axp809: Add GPIO controller nodes
ARM: dts: axp803/axp81x: Drop GPIO LDO pinctrl nodes
Link: https://lore.kernel.org/r/Y3fuAosinWbrj+Dy@jernej-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:56:43 +0000 (10:56 +0100)]
Merge tag 'at91-dt-6.2-2' of https://git./linux/kernel/git/at91/linux into soc/dt
AT91 DT for 6.2 #2
It contains:
- one typo fix for a SAMA7G5 pin; the pin is not used anywhere in the
device trees.
* tag 'at91-dt-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sama7g5: fix signal name of pin PD8
Link: https://lore.kernel.org/r/20221118131214.301678-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kunihiko Hayashi [Thu, 17 Nov 2022 16:32:19 +0000 (01:32 +0900)]
ARM: dts: uniphier: Add Pro5 board support
Initial version of devicetree sources for Pro5 EPCORE and ProEX boards.
These boards have UART, I2C, USB, eMMC and PCI endpoint in common.
Pro5 EPCORE board is a kind of Pro5 reference board with PCIe endpoint
card edge connector.
ProEX board shares peripherals with Linux and other systems, and some
of these ports are available in Linux.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221117163219.3673-3-hayashi.kunihiko@socionext.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kunihiko Hayashi [Thu, 17 Nov 2022 16:32:18 +0000 (01:32 +0900)]
dt-bindings: arm: uniphier: Add Pro5 boards
Add compatible string for Pro5 EP-Core board and ProEX board support.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221117163219.3673-2-hayashi.kunihiko@socionext.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:53:52 +0000 (10:53 +0100)]
Merge tag 'samsung-dt64-6.2' of https://git./linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.2
Correct pin drive strength macros (names) and values used on Tesla FSD
SoC.
* tag 'samsung-dt64-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: fsd: fix drive strength values as per FSD HW UM
arm64: dts: fsd: fix drive strength macros as per FSD HW UM
Link: https://lore.kernel.org/r/20221116093010.18515-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Aakarsh Jain [Wed, 16 Nov 2022 09:30:09 +0000 (10:30 +0100)]
ARM: dts: exynos: Add new SoC specific compatible string for Exynos3250 SoC
Exynos3250 and Exynos5420 are using same compatible string for MFC codec
device but they have different clock hierarchy and complexity. Add new
compatible string followed by mfc-v7 fallback for Exynos3250 SoC.
Suggested-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Aakarsh Jain <aakarsh.jain@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Link: https://lore.kernel.org/r/20221114115024.69591-4-aakarsh.jain@samsung.com
Link: https://lore.kernel.org/r/20221116093010.18515-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Conor Dooley [Sun, 20 Nov 2022 11:12:13 +0000 (11:12 +0000)]
Merge branch 'riscv-thead_c9xx' into riscv-dt-for-next
The bouffalolabs stuff is going to need the thead,c906 compatible too,
so there is no point waiting the D1 stuff to land for it.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Samuel Holland [Mon, 15 Aug 2022 05:08:05 +0000 (00:08 -0500)]
dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C906 core is used in the Allwinner D1 SoC.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Andrew Davis [Mon, 24 Oct 2022 17:34:31 +0000 (12:34 -0500)]
arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso
DTB Overlays (.dtbo) can now be built from source files with the
extension (.dtso). This makes it clear what is the content of the files
and differentiates them from base DTB source files.
Convert the DTB overlay source files in the arm64/freescale directory.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shawn Guo [Sat, 19 Nov 2022 06:29:30 +0000 (14:29 +0800)]
Merge remote-tracking branch 'robh/dt/dtbo-rename' into imx/dt64
Adrian Alonso [Thu, 17 Nov 2022 09:54:03 +0000 (17:54 +0800)]
arm64: dts: imx8mm-evk: add vcc supply for pca6416
pca6146 requires vcc-supply to work on i.MX8MM-EVK board.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Haibo Chen [Thu, 17 Nov 2022 09:54:02 +0000 (17:54 +0800)]
arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
Some SD Card controller and power circuitry has increased capacitance,
so the usual toggling of regulator to power the card off and on
is insufficient.
According to SD spec, for sd card power reset operation, the sd card
supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
next time power back the sd card supply voltage to 3.3v, sd card can't
support SD3.0 mode again.
This patch add the off-on-delay-us, make sure the sd power reset behavior
is align with the specification. Without this patch, when do quick system
suspend/resume test, some sd card can't work at SD3.0 mode after system
resume back.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:54:01 +0000 (17:54 +0800)]
arm64: dts: imx8mn-evk: enable uart1
Enable uart1 for BT usage
Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:54:00 +0000 (17:54 +0800)]
arm64: dts: imx8mn-evk: add i2c gpio recovery settings
Add I2C gpio recovery iomuxc settings
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:59 +0000 (17:53 +0800)]
arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
Some SD Card controller and power circuitry has increased capacitance,
so the usual toggling of regulator to power the card off and on
is insufficient.
According to SD spec, for sd card power reset operation, the sd card
supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
next time power back the sd card supply voltage to 3.3v, sd card can't
support SD3.0 mode again.
This patch add the off-on-delay-us, make sure the sd power reset behavior
is align with the specification. Without this patch, when do quick system
suspend/resume test, some sd card can't work at SD3.0 mode after system
resume back.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:58 +0000 (17:53 +0800)]
arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The nxp,dvs-run-voltage
and nxp,dvs-standby-voltage need set for BUCK1, not BUCK2.
BUCK2 is for A53, which is handled by DVFS, so no need dvs property.
nxp,dvs-run-voltage is not needed, since bootloader must configure
voltage to make system boot well.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:57 +0000 (17:53 +0800)]
arm64: dts: imx8mp-evk: enable I2C2 node
Enable I2C node for i.MX8MP-EVK
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Han Xu [Thu, 17 Nov 2022 09:53:56 +0000 (17:53 +0800)]
arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
enable fspi nor on imx8mp evk dts
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:55 +0000 (17:53 +0800)]
arm64: dts: imx8mp-evk: enable uart1/3 ports
Enable uart1/3 ports for evk board.
Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Clark Wang [Thu, 17 Nov 2022 09:53:54 +0000 (17:53 +0800)]
ARM64: dts: imx8mp-evk: add pwm support
Enable pwm1/2/4 support.
Enable pwm1 on pin GPIO1_IO01 for DSI_BL_PWM
pwm2 on pin GPIO1_IO11 for LVDS_BL_PWM
pwm4 on pin SAI5_RXFS for J21-32
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:52 +0000 (17:53 +0800)]
arm64: dts: imx8mp: add mlmix power domain
Add mlmix power domain
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Philippe Schenker [Tue, 15 Nov 2022 18:05:54 +0000 (19:05 +0100)]
ARM: dts: colibri-imx6ull: Enable dual-role switching
The Colibri standard provides a GPIO called USBC_DET to switch from
USB Host to USB Device and back. Make use of this GPIO by adding it
with usb-connector framework.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Martin Kepplinger [Fri, 9 Sep 2022 08:39:40 +0000 (10:39 +0200)]
arm64: dts: imx8mq: fix dtschema warning for imx7-csi
According to dtschema for the csi bridge, compatible is an enum and
only one must be used. Fixing this removes the following warning:
compatible: 'oneOf' conditional failed, one must be fixed
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Andrew Davis [Mon, 14 Nov 2022 20:59:39 +0000 (14:59 -0600)]
kbuild: Cleanup DT Overlay intermediate files as appropriate
%.dtbo.o and %.dtbo.S files are used to build-in DT Overlay. They should
should not be removed by Make or the kernel will be needlessly rebuilt.
These should be removed by "clean" and ignored by git like other
intermediate files.
Reported-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Fixes:
941214a512d8 ("kbuild: Allow DTB overlays to built into .dtbo.S files")
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20221114205939.27994-1-afd@ti.com
Signed-off-by: Rob Herring <robh@kernel.org>
Yoshihiro Shimoda [Fri, 18 Nov 2022 12:09:52 +0000 (21:09 +0900)]
arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDES
Enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221118120953.1186392-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda [Fri, 18 Nov 2022 12:09:51 +0000 (21:09 +0900)]
arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221118120953.1186392-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Tue, 15 Nov 2022 10:51:35 +0000 (10:51 +0000)]
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
Enable CANFD and I2C on RZ/Five SMARC EVK.
Note, these blocks are enabled in RZ/G2UL SMARC EVK DTSI [0] hence
deleting these disabled nodes from RZ/Five SMARC EVK DTSI enables them
here too as we include [0] in RZ/Five SMARC EVK DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Tue, 15 Nov 2022 10:51:34 +0000 (10:51 +0000)]
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM:
- ADC
- OPP
- Thermal Zones
- TSU
Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence
deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them
here too as we include [0] in RZ/Five SMARC SoM DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Wed, 16 Nov 2022 10:21:40 +0000 (10:21 +0000)]
arm64: dts: renesas: r9a09g011: Add system controller node
Add system controller node to RZ/V2M SoC dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221116102140.852889-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:04 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add CA76 operating points
Add operating points for running the Cortex-A76 CPU cores on R-Car V4H
at various speeds, up to the Normal (1.7 GHz) performance mode.
Based on a patch in the BSP by Tho Vu.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/8afb32f5dc123ebf2b941703483152ff0992191d.1668429870.git.geert+renesas@glider.be
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:03 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add CPU core clocks
Describe the clocks for the four Cortex-A76 CPU cores.
CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/aa6e9ae21e451ebd40d54d986bd0296571128d5b.1668429870.git.geert+renesas@glider.be
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:02 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add CPUIdle support
Support CPUIdle for ARM Cortex-A76 on R-Car V4H.
Based on patches in the BSP by Tho Vu and Vincent Bryce.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f6d4076983eb45cf23595a045747f28cbdcdf4e6.1668429870.git.geert+renesas@glider.be
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:01 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU
topology and PSCI support for enabling CPU cores.
R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters.
Based on a patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ccb55458bd87f8ba70d28c61bcc254f22184824c.1668429870.git.geert+renesas@glider.be
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:00 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.
Extracted from a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
Conor Dooley [Tue, 15 Nov 2022 15:25:47 +0000 (15:25 +0000)]
riscv: dts: microchip: remove unused pcie clocks
The PCIe root port in the designs that ship with the PolarBerry and
M100PFSEVP are connected via one, not two Fabric Interface Controllers
(FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks from
the dt node.
The same clock provides both, so this is harmless but inaccurate.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Conor Dooley [Tue, 15 Nov 2022 15:25:46 +0000 (15:25 +0000)]
riscv: dts: microchip: remove pcie node from the sev kit
The SEV kit reference design does not hook up the PCIe root port to the
core complex including it is misleading.
The entry is a re-use mistake - I was not aware of this when I moved
the PCIe node out of mpfs.dtsi so that individual bistreams could
connect it to different fics etc.
The node is disabled, so there should be no functional change here.
Fixes:
978a17d1a688 ("riscv: dts: microchip: add sevkit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Phil Edworthy [Wed, 16 Nov 2022 10:21:38 +0000 (10:21 +0000)]
dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
Add DT binding documentation for System Configuration (SYS) found on
RZ/V2M SoC's.
SYS block contains the SYS_VERSION register which can be used to retrieve
SoC version information.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221116102140.852889-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Mihai Sain [Thu, 17 Nov 2022 13:30:18 +0000 (15:30 +0200)]
ARM: dts: at91: sama7g5: fix signal name of pin PD8
The signal name of pin PD8 with function D is A22_NANDCLE
as it is defined in the datasheet.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
[claudiu.beznea: rebased on top of 6.1-rc1, removed fixes tag]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20221114151035.2926-1-mihai.sain@microchip.com
Marek Vasut [Thu, 27 Oct 2022 18:38:26 +0000 (20:38 +0200)]
ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench board
Replace "mdio0" node with "mdio" to match mdio.yaml DT schema.
Fixes:
c8ce0dd75515b ("ARM: dts: stm32: Add DHCOR based Testbench board")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Amelie Delaunay [Mon, 24 Oct 2022 09:46:48 +0000 (11:46 +0200)]
ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk
MCP23017 is an IO expander offering 16 input/output port expander with
interrupt output.
On stm32mp135f-dk, only INTA is routed (on PG12), but MCP23017 can mirror
the bank B interrupts on INTA, that's why the property microchip,irq-mirror
is used.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Amelie Delaunay [Mon, 24 Oct 2022 09:46:47 +0000 (11:46 +0200)]
ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13
MCP23017 interrupt line (routed on PG12) requires to be pulled-up.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Andre Przywara [Thu, 10 Nov 2022 00:55:07 +0000 (00:55 +0000)]
ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0
As many other Allwinner SoCs from the last years, the first USB host
controller pair in the Allwinner H3 and H5 chips share a USB PHY with
the MUSB OTG controller. This is probably the reason why we didn't have
a "phys" property in those host controller nodes.
This works fine as long as the MUSB controller driver is loaded, as this
takes care of the proper PHY setup, including the muxing between MUSB
and the HCI.
However this requires the MUSB driver to be enabled and loaded, and also
upsets U-Boot, which cannot use a HCI port without a "phys" property.
Similar to what we did in commit
cc72570747e4 ("arm64: dts: allwinner:
A64: properly connect USB PHY to port 0"), add the "phys" property to
the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file.
This is not only the proper description of the hardware, but also avoids
a nasty error message in U-Boot triggered by a recent patch. (The port
never worked in host mode, but the error was suppressed due to a bug.)
When using the MUSB port in OTG mode, this also fixes host mode
switching, so people can use OTG adapters to connect a USB device to
port 0.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221110005507.19464-1-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 7 Nov 2022 00:54:30 +0000 (00:54 +0000)]
ARM: dts: suniv: f1c100s: add LRADC node
The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.
Add the DT node describing the base address and interrupt. As in the
older SoCs, there is no explicit reset or clock gate, also there is a
dedicated, non-multiplexed pin, so need for more properties.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-8-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 7 Nov 2022 00:54:29 +0000 (00:54 +0000)]
ARM: dts: suniv: f1c100s: add CIR DT node
The CIR (infrared receiver) controller in the Allwinner F1C100s series
of SoCs is compatible to the ones used in other Allwinner SoCs.
Add the DT node describing the resources of the controller.
There are multiple possible pinmuxes, but none as them seem to be an
obvious choice, so refrain from adding any pincontroller subnodes for
now.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-7-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 7 Nov 2022 00:54:28 +0000 (00:54 +0000)]
dt-bindings: media: IR: Add F1C100s IR compatible string
The CIR controller in the Allwinner F1C100s series of SoCs is compatible
to the ones used in other Allwinner SoCs.
Add the respective compatible name to the existing IR binding, and pair
it with the A31 fallback compatible string.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221107005433.11079-6-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 7 Nov 2022 00:54:26 +0000 (00:54 +0000)]
ARM: dts: suniv: f1c100s: add I2C DT nodes
The Allwinner F1C100s series of SoCs contain three I2C controllers
compatible to the ones used in other Allwinner SoCs.
Add the DT nodes describing the resources of the controllers.
At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
include those pins already, to simplify referencing them later.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-4-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 7 Nov 2022 00:54:25 +0000 (00:54 +0000)]
ARM: dts: suniv: f1c100s: add PWM node
The Allwinner F1C100s family of SoCs contain a PWM controller compatible
to the one used in the A20 chip.
Add the DT node so that any users can simply enable it in their board
DT.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-3-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 7 Nov 2022 00:54:24 +0000 (00:54 +0000)]
dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
The PWM controller in the Allwinner F1C100s series of SoCs is the same
as in the A20 SoCs, so allow using that as the fallback name.
Join the V3s compatible string in an enum on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20221107005433.11079-2-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Biju Das [Thu, 10 Nov 2022 16:09:31 +0000 (16:09 +0000)]
arm64: dts: renesas: r9a09g011: Add L2 Cache node
The Cortex-A53 processor on RZ/V2M has 512 KB L2 Cache.
Add L2 Cache node to SoC dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221110160931.101539-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fabrizio Castro [Thu, 3 Nov 2022 22:39:56 +0000 (22:39 +0000)]
arm64: dts: renesas: rzv2mevk2: Enable watchdog
Enable the watchdog so that we can reboot the system.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20221103223956.50575-4-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fabrizio Castro [Thu, 3 Nov 2022 22:39:55 +0000 (22:39 +0000)]
arm64: dts: renesas: r9a09g011: Add watchdog node
The r9a09g011 (a.k.a. RZ/V2M) comes with two watchdog IPs,
but Linux is only allowed one.
Add a node for the watchdog allowed to Linux to the SoC
specific dtsi.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20221103223956.50575-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Pierre Gondois [Mon, 7 Nov 2022 15:57:02 +0000 (16:57 +0100)]
arm64: dts: Update cache properties for hisilicon
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Pierre Gondois [Mon, 7 Nov 2022 15:57:01 +0000 (16:57 +0100)]
arm64: dts: Update cache properties for freescale
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chester Lin <clin@suse.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Conor Dooley [Mon, 14 Nov 2022 22:20:43 +0000 (22:20 +0000)]
Merge branch 'riscv-visionfive_v1' into riscv-dt-for-next
The VisionFive DT somehow never actually made it upstream, and is
largely shared with the BeagleV. Better late than never.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Conor Dooley [Fri, 7 Oct 2022 11:35:11 +0000 (12:35 +0100)]
riscv: dts: microchip: fix the icicle's #pwm-cells
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
blindly overridden by the (out of tree) driver anyway. The core can
support inverted operation, so update the entry to correctly report its
capabilities.
Fixes:
72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit")
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Arnd Bergmann [Thu, 27 Oct 2022 16:09:46 +0000 (18:09 +0200)]
Merge tag 'ux500-dts-for-v6.2' of git://git./linux/kernel/git/linusw/linux-nomadik into arm/dt
Some Ux500 DTS updates for v6.2:
- Some cleanups from Krzysztof for the SPI nodes.
- Fix up the NFC chip in Janice.
- Drop a bogus power domain regulator that isn't used for
the crypto blocks. (We use proper power domains now.)
- Add GPS to the Kyle.
* tag 'ux500-dts-for-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ux500: Add GPS to the Kyle
ARM: dts: DBx500 cryp and hash uses power domain
ARM: dts: ux500: Fix up the Janice NFC chip
ARM: dts: ste: ux500: align SPI node name with dtschema
Link: https://lore.kernel.org/r/CACRpkdaXmmZWsGdTG5tqNragkoefcTeUHjR+ZwNyNaa0S7s-7Q@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 27 Oct 2022 16:11:02 +0000 (18:11 +0200)]
Merge tag 'asahi-soc-dt-6.2' of https://github.com/AsahiLinux/linux into arm/dt
Apple SoC DT updates for 6.2.
This includes new device trees for Apple M1 Pro/Max/Ultra SoCs and the
devices that contain them, as well as some audio-related changes.
* tag 'asahi-soc-dt-6.2' of https://github.com/AsahiLinux/linux:
arm64: dts: apple: Add ADMAC resets on t8103/t600x
dt-bindings: dma: apple,admac: Add reset
arm64: dts: apple: t600x: Add MCA and its support
arm64: dts: apple: t8103: Add MCA and its support
arm64: dts: apple: t8103: Add AUDIO_P parent to the SIO_ADMA power domain
arm64: dts: apple: Add J375 devicetrees
arm64: dts: apple: Add J314 and J316 devicetrees
arm64: dts: apple: Add initial t6000/t6001/t6002 DTs
arm64: dts: apple: Fix j45x model years
dt-bindings: arm: apple: Add t6001/t6002 Mac Studio compatibles
dt-bindings: apple,aic2: Add CPU PMU per-cpu pseudo-interrupts
dt-bindings: iommu: dart: add t6000 compatible
Link: https://lore.kernel.org/r/dea10860-2870-3a9e-fa51-21e493b1573a@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kory Maincent [Wed, 2 Nov 2022 17:10:09 +0000 (18:10 +0100)]
arm: dts: spear600: Add ssp controller nodes
The SPEAr600 has three Synchronous serial port to enables synchronous
serial communication with slave or master peripherals (SPI). Lets add these
nodes to be able to use them.
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kory Maincent [Wed, 2 Nov 2022 17:10:06 +0000 (18:10 +0100)]
arm: dts: spear600: Fix clcd interrupt
Interrupt 12 of the Interrupt controller belongs to the SMI controller,
the right one for the display controller is the interrupt 13.
Fixes:
8113ba917dfa ("ARM: SPEAr: DT: Update device nodes")
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 14 Nov 2022 14:34:40 +0000 (15:34 +0100)]
Merge tag 'at91-dt-6.2' of https://git./linux/kernel/git/at91/linux into soc/dt
AT91 DT for 6.2
It contains:
- interrupt support for ethernet PHYs on pcb8290 board
- thermal management support for SAMA7G5 by adding OTP controller
(that keeps temperature sensor calibration data), proper ADC
bindings and describing thermal zones
- securam node from SAMA7G5 is now described with generic name (sram)
- remove of status = "okay" from SAM9X60-EK regulators
* tag 'at91-dt-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sam9x60ek: remove status = "okay" for regulators
ARM: dts: at91: sama7g5: use generic name for securam
ARM: dts: at91: sama7g5: add thermal zones node
ARM: dts: at91: sama7g5: add temperature sensor
ARM: dts: at91: sama7g5: add cells for temperature calibration
ARM: dts: at91: sama7g5: add io-channel-cells to adc node
ARM: dts: at91: sama7g5: add otpc node
ARM: dts: lan966x: Add interrupt support for PHYs on pcb8290
Link: https://lore.kernel.org/r/20221110115431.180908-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 14 Nov 2022 14:08:57 +0000 (15:08 +0100)]
Merge tag 'dt-cleanup-6.2' of https://git./linux/kernel/git/krzk/linux-dt into soc/dt
Minor improvements in ARM DTS for v6.2
1. Aspeed: fix qcom,dc-scm-v1-bmc compatible in the bindings.
2. Marvell: include bindings in maintainers entry.
3. Cleanup DTS according to bindings (panel endpoint unit address,
incorrect spi-max-frequency, generic node names).
4. Few indentation fixes.
* tag 'dt-cleanup-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
dt-bindings: arm: aspeed: adjust qcom,dc-scm-v1-bmc compatible after rename
ARM: dts: sunxi: correct indentation
ARM: dts: omap: correct indentation
ARM: dts: kirkwood: correct indentation
ARM: dts: armada: correct indentation
ARM: dts: ti: correct indentation
ARM: dts: aspeed: align SPI node name with dtschema
MAINTAINERS: ARM: marvell: include bindings
ARM: dts: sunplus: sp7021: drop incorrect spi-max-frequency
ARM: dts: am335x: drop panel endpoint unit address
Link: https://lore.kernel.org/r/20221110092111.18581-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 14 Nov 2022 14:00:55 +0000 (15:00 +0100)]
Merge tag 'renesas-dt-bindings-for-v6.2-tag1' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.2
- Move renesas.yaml from arm to soc, and document RZ/Five support.
* tag 'renesas-dt-bindings-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
Link: https://lore.kernel.org/r/cover.1667558749.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 14 Nov 2022 13:55:43 +0000 (14:55 +0100)]
Merge tag 'renesas-arm-dt-for-v6.2-tag1' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas ARM DT updates for v6.2
- DMA, SPI (MSIOF), external interrupt (INTC-EX), PWM (PWM and TPU),
SDHI, HyperFLASH/QSPI (RPC), and serial ((H)SCIF) support for the
R-Car V4H SoC,
- I/O expander, eMMC, and QSPI FLASH support for the White Hawk
development board,
- Preparatory work to share r9a07g043.dtsi between the ARM-based
RZ/G2UL (R9A07G043U) and the RISC-V-based RZ/Five (R9A07G043F) SoCs,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property
ARM: dts: renesas: Miscellaneous whitespace fixes
arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values
arm64: dts: renesas: r8a779g0: Add remaining HSCIF nodes
arm64: dts: renesas: r8a779g0: Add SCIF nodes
arm64: dts: renesas: white-hawk-cpu: Add QSPI FLASH support
arm64: dts: renesas: r8a779g0: Add RPC node
arm64: dts: renesas: white-hawk-cpu: Add eMMC support
arm64: dts: renesas: r8a779g0: Add SDHI node
arm64: dts: renesas: rzg2l: Drop WDT2 nodes
arm64: dts: renesas: r8a779g0: Add TPU device node
arm64: dts: renesas: r8a779g0: Add PWM device nodes
arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock
arm64: dts: renesas: condor-common: Add missing bootargs
arm64: dts: renesas: white-hawk-cpu: Add PCA9654 I/O Expander
arm64: dts: renesas: r8a779g0: Add INTC-EX node
arm64: dts: renesas: r8a779g0: Add MSIOF nodes
arm64: dts: renesas: r8a779g0: Add DMA support
arm64: dts: renesas: rzg2ul-smarc: Move spi1 pinmux to carrier board DTSI
...
Link: https://lore.kernel.org/r/cover.1667558740.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fabio Estevam [Sun, 13 Nov 2022 12:44:59 +0000 (09:44 -0300)]
arm64: dts: imx8mm-phg: Add initial board support
Add the initial support for the i.MX8MM Cloos PHG board.
This board uses a imx8mm-tqma8mqml SoM from TQ-Group.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fabio Estevam [Sun, 13 Nov 2022 12:44:58 +0000 (09:44 -0300)]
dt-bindings: arm: fsl: Add an entry for Cloos PHG board
Add an entry for the i.MX8MM Cloos PHG board.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fabio Estevam [Sun, 13 Nov 2022 12:44:57 +0000 (09:44 -0300)]
dt-bindings: vendor-prefixes: Add an entry for Cloos
Carl Cloos Schweisstechnik GmbH develops, manufactures and delivers
welding industrial solutions:
https://www.cloos.de/de-en/
Add a vendor prefix entry for it.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shenwei Wang [Fri, 11 Nov 2022 15:50:16 +0000 (09:50 -0600)]
arm64: dts: imx8qxp-ss-lsio: add gpio-ranges property
add gpio-ranges property for imx8qxp soc.
This gpio-range is used to record which GPIOs correspond to which pins on
which pin controllers. The GPIO to PIN mapping will be referenced by the
pad wakeup function in GPIO-MXC driver.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shenwei Wang [Fri, 11 Nov 2022 15:50:15 +0000 (09:50 -0600)]
arm64: dts: imx8qm-ss-lsio: add gpio-ranges property
add gpio-ranges property for imx8qm soc.
This gpio-range is used to record which GPIOs correspond to which pins on
which pin controllers. The GPIO to PIN mapping will be referenced by the
pad wakeup function in GPIO-MXC driver.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shenwei Wang [Fri, 11 Nov 2022 15:50:14 +0000 (09:50 -0600)]
arm64: dts: imx8dxl-ss-lsio: add gpio-ranges property
add gpio-ranges property for imx8dxl soc.
This gpio-range is used to record which GPIOs correspond to which pins on
which pin controllers. The GPIO to PIN mapping will be referenced by the
pad wakeup function in GPIO-MXC driver.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Fri, 11 Nov 2022 15:47:42 +0000 (10:47 -0500)]
arm64: dts: imx8dxl_evk: add lpspi0 support
Enable lpspi0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Fri, 11 Nov 2022 15:47:41 +0000 (10:47 -0500)]
arm64: dts: imx8dxl: add lpspi support
Add lpspi0 lpspi1 lpspi2 lpspi3 node at common dma subsystem.
Change irq number for 8dxl.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Fri, 11 Nov 2022 15:47:40 +0000 (10:47 -0500)]
arm64: dts: imx8dxl_evk: add flexspi0 support
Enable flexspi0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Fri, 11 Nov 2022 15:47:39 +0000 (10:47 -0500)]
arm64: dts: imx8dxl: add flexspi0 support
Add flexspi0 node at common lsio subsystem.
Change flexspi0 irq number for imx8dxl.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Fri, 11 Nov 2022 15:47:38 +0000 (10:47 -0500)]
arm64: dts: imx8dxl_evk: add adc0 support
Enable adc0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Fri, 11 Nov 2022 15:47:37 +0000 (10:47 -0500)]
arm64: dts: imx8dxl: add adc0 support
Add adc0 and adc1 node at imx8 common dma subsystem.
imx8dxl have only adc0. Change irq number for adc0.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Andreas Kemnade [Fri, 4 Nov 2022 20:42:51 +0000 (21:42 +0100)]
ARM: dts: imx: e60k02: Add touchscreen
Add the touchscreen now, since the driver is available.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Detlev Casanova [Fri, 28 Oct 2022 14:18:11 +0000 (10:18 -0400)]
ARM: dts: imx6qdl-sabre: Add mmc aliases
If not specified, the mmc0 and mmc1 devices will be the devices
mmc@2190000 and mmc@2194000, which are in disabled state on the iMX.6
Sabrelite devices.
The actual SD card reader devices are the ones at mmc@2198000 and
mmc@219c000.
Set aliases to use the correct mmc devices order.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Mon, 7 Nov 2022 18:17:54 +0000 (10:17 -0800)]
arm64: dts: imx8m{m,n}-venice-gw7902: add gpio pins for new board revision
Add gpio pins present on new board revision:
* LTE modem support (imx8mm-gw7902 only)
- lte_pwr#
- lte_rst
- lte_int
* M2 power enable
- m2_pwr_en
* off-board 4.0V supply
- vdd_4p0_en
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Andrej Picej [Fri, 4 Nov 2022 07:03:58 +0000 (08:03 +0100)]
ARM: dts: imx6ul/ull: suspend i.MX6UL watchdog in wait mode
It was discovered that the watchdog triggers when the device is put into
"Suspend-To-Idle"/"freeze" low-power mode. Setting WDW bit disables
watchdog when the device is put into WAIT mode.
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Wed, 2 Nov 2022 22:25:43 +0000 (23:25 +0100)]
dt-bindings: nvmem: snvs-lpgpr: Fix i.MX8M compatible strings
The compatible strings for "fsl,imx8m*-snvs-lpgpr" always contain
the fallback "fsl,imx7d-snvs-lpgpr" compatible in DTs too, since
the fallback compatible is what the driver matches on, this way:
compatible = "fsl,imx8mm-snvs-lpgpr", "fsl,imx7d-snvs-lpgpr"
The older "fsl,imx7d-snvs-lpgpr" and "fsl,imx6*-snvs-lpgpr" used
only that single compatible string.
Document both options in the binding document.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Wed, 2 Nov 2022 21:19:03 +0000 (22:19 +0100)]
arm64: dts: imx8mm: Remove watchdog always-enabled property from eDM SBC
There is no such always-enabled property supported by gpio-watchdog
driver or described in its bindings, remove it.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Wed, 2 Nov 2022 19:31:02 +0000 (20:31 +0100)]
arm64: dts: imx8mm: imx8mn: imx8mp: imx8mq: Replace opp-xM with opp-x000000
Fix the following dtbs_check warning on all of i.MX8M variants:
"
opp-table: Unevaluated properties are not allowed ('opp-25M', 'opp-100M', 'opp-750M' were unexpected)
"
Using the following command:
"
$ sed -i '/opp-[0-9]\+M/ s@M {@000000 {@' arch/arm64/boot/dts/freescale/imx8m*
"
The Documentation/devicetree/bindings/opp/opp-v2-base.yaml expects the OPP
subnode names to be full frequency listings in Hz without unit suffixes.
Only the i.MX8M DTs are affected per "git grep 'opp-[0-9]\+M'", so fix them.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Wed, 2 Nov 2022 19:17:56 +0000 (20:17 +0100)]
arm64: dts: imx8mm-data-modul: Rename /watchdog-gpio to plain /watchdog
The DT bindings checker is confused by the -gpio node suffix,
drop it to fix the following warning:
"
imx8mm-data-modul-edm-sbc.dtb: /: watchdog-gpio: {'pinctrl-names': ['default'], 'pinctrl-0': [[104]], 'compatible': ['linux,wdt-gpio'], 'always-enabled': True, 'gpios': [[45, 8, 0]], 'hw_algo': ['level'], 'hw_margin_ms': [[1500]], 'status': ['disabled']} is not of type 'array'
"
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Wed, 2 Nov 2022 13:12:03 +0000 (14:12 +0100)]
arm64: dts: verdin-imx8mp: dahlia: mark usb_2 permanently attached
As both Dahlia and the Verdin Development Board have on-carrier
permanently attached USB hubs mark Verdin USB_2 as such.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Wed, 2 Nov 2022 13:12:02 +0000 (14:12 +0100)]
arm64: dts: verdin-imx8mp: add gpio usb-b connector
Add GPIO USB-B connector (gpio-usb-b-connector) functionality using
Verdin USB_1_ID.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Wed, 2 Nov 2022 13:12:01 +0000 (14:12 +0100)]
arm64: dts: verdin-imx8mp: disable usb port power control
Disable port power control on Verdin USB_1/2 as we use regular
fixed-regulators with Verdin USB_1/2_EN as enable GPIOs.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Wed, 2 Nov 2022 13:12:00 +0000 (14:12 +0100)]
arm64: dts: verdin-imx8mp: add usb_1 over-current detection
Add Verdin USB_1 over-current detection functionality via Verdin
USB_1_OC# (SODIMM 157) being active-low and removing its previous
gpio_hog3 mapping.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Wed, 2 Nov 2022 13:11:59 +0000 (14:11 +0100)]
arm64: dts: verdin-imx8mp: remove usb_2 over-current detection disabling
The disable-over-current property is only applicable for the
ci-hdrc-usb2 and dwc2 drivers while the i.MX 8M Plus integrates dwc3
IP. Therefore remove this property which does not really serve any
purpose here.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marcel Ziswiler [Wed, 2 Nov 2022 13:11:58 +0000 (14:11 +0100)]
arm64: dts: verdin-imx8mp: improve pinctrl for vbus-supplies
As we are using two fixed regulators for Verdin USB_1_EN (SODIMM 155)
and Verdin USB_2_EN (SODIMM 185), those should be muxed as GPIOs rather
than OTG_PWR.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Tue, 1 Nov 2022 09:06:42 +0000 (10:06 +0100)]
arm64: dts: mba8mpxl: Add PWM fan support
This adds the support for optional PWM fan 422J/2HP.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>