Simon Glass [Sun, 25 Sep 2016 00:19:54 +0000 (18:19 -0600)]
spl: Add a parameter to jump_to_image_linux()
Instead of using the global spl_image variable, pass the required struct in
as an argument.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 25 Sep 2016 00:19:53 +0000 (18:19 -0600)]
spl: Add a parameter to spl_parse_image_header()
Instead of using the global spl_image variable, pass the required struct in
as an argument.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 25 Sep 2016 00:19:52 +0000 (18:19 -0600)]
spl: Add a parameter to spl_set_header_raw_uboot()
Rather than act on the global variable, pass the required struct in as a
parameter.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 25 Sep 2016 00:19:51 +0000 (18:19 -0600)]
spl: Move spl_board_load_image() into a generic header
At present this is only used on ARM and sandbox, but it is just as
applicable to other architectures. Move the function prototype into the
generic SPL header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Alexandre Courbot [Fri, 30 Sep 2016 08:37:00 +0000 (17:37 +0900)]
serial: ns16550: Handle -ENOENT when requesting clock
When calling clk_get_by_index(), fall back to the legacy method of
getting the clock if -ENOENT is returned.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Fabio Estevam [Wed, 5 Oct 2016 18:00:58 +0000 (15:00 -0300)]
udoo: Add a README file
Add a README file to explain how to build and flash the SD card
for Udoo boards.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Albert ARIBAUD \(3ADEV\) [Mon, 26 Sep 2016 07:08:08 +0000 (09:08 +0200)]
pcm052: add new BK4r1 target based on PCM052 SoM
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\) [Mon, 26 Sep 2016 07:08:07 +0000 (09:08 +0200)]
pcm052: allow specifying onboard DDR size in configs
PCM052 SoMs may be equipped with various sizes of DDR.
Keep default of 256MB; new PCM052-based targets will
specify their actual DDR size.
Linux command line is auto-adjusted to DDR size.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\) [Mon, 26 Sep 2016 07:08:06 +0000 (09:08 +0200)]
tools: mkimage: add support for Vybrid image format
This format can be flashed directly at address 0 of
the NAND FLASH, as it contains all necessary headers.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\) [Mon, 26 Sep 2016 07:08:05 +0000 (09:08 +0200)]
pcm052: add 'm4go' command
Add the 'm4go' command to pcm052-based targets.
It loads scatter file images.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\) [Mon, 26 Sep 2016 07:08:04 +0000 (09:08 +0200)]
pcm052: remove target-specific dtb name from env
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\) [Mon, 26 Sep 2016 07:08:03 +0000 (09:08 +0200)]
pcm052: fix MTD partitioning
Merge 'spare' into 'bootloader' partition
Use same partition for ramdisk and rootfs boot scenarios.
Remove 'ramdisk' partition, use 'rootfs' for ramdisk
(ramdisk and nand boot scenarios are mutually exclusive).
Expand last partition to end of actual NAND size.
Adjust UBIFS rootfs boot kernel arguments.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Peng Fan [Wed, 28 Sep 2016 01:40:27 +0000 (09:40 +0800)]
imx: imx6ul: disable POR_B internal pull up
>From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Sun, 18 Sep 2016 08:28:28 +0000 (16:28 +0800)]
imx-common: enlarge mux width to 4
For i.MX6, the mux width is 4, not 3. So enlarge the width.
IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Stefan Agner [Thu, 15 Sep 2016 22:04:39 +0000 (15:04 -0700)]
imx: mx6: fix USB bmode to use reserved value
Currently the bmode "usb" uses BOOT_CFG1 to 0x01, -which means
BOOT_CFG1[7:4] is set to b0000. According to Table 8-7 Boot
Device Selection this is NOR/OneNAND and not Reserved.
Use 0x10 which leads to b0001, which is a Reserved boot device.
With that the SoC reliably falls back to the serial loader.
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Troy Kisky <troy.kisky@boundarydevices.com>
Peng Fan [Thu, 11 Aug 2016 06:02:57 +0000 (14:02 +0800)]
arm: imx: add i.MX6ULL 14x14 EVK board support
Add i.MX6ULL EVK board support:
Add device tree file, which is copied from NXP Linux.
Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
The uart iomux settings are still keeped in board file.
Boot Log:
U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)
CPU: Freescale i.MX6ULL rev1.0 at 396MHz
CPU: Commercial temperature grade (0C to 95C) at 15C
Reset cause: POR
Model: Freescale i.MX6 ULL 14x14 EVK Board
Board: MX6ULL 14x14 EVK
DRAM: 512 MiB
MMC: initialized IMX pinctrl driver
FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:56 +0000 (14:02 +0800)]
dm: mmc: intialize dev when probe
Need to initialize mmc->dev when probe, or will met
"dev_get_uclass_priv: null device", when `mmc dev 1`.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Peng Fan [Thu, 11 Aug 2016 06:02:55 +0000 (14:02 +0800)]
arm: dts: add device tree for i.MX6ULL
Add device tree for i.MX6ULL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:54 +0000 (14:02 +0800)]
dt-bindings: add i.mx6ul clock header
Add i.mx6ul clock header, copied from kernel commit (
29b4817d401).
i.MX6ULL reuse the file in Linux Kernel, so let's keep the same.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:53 +0000 (14:02 +0800)]
arm: dts: imx6ull: add pinctrl defines
Add pinctrl defines for NXP i.MX 6ULL.
Since i.MX6ULL reuses some definitions of i.MX6UL,
also add i.MX6UL pinctrl defines from linux kernel commit (
29b4817d401).
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:52 +0000 (14:02 +0800)]
pinctrl: imx6: support i.MX6ULL
There two iomuxc for i.MX6ULL. one iomuxc is compatible is i.MX6UL,
the other iomuxc is for SVNS usage, similar with the one in mx7.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Peng Fan [Thu, 11 Aug 2016 06:02:51 +0000 (14:02 +0800)]
imx: iomux: fix snvs usage for i.MX6ULL
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
Peng Fan [Thu, 11 Aug 2016 06:02:50 +0000 (14:02 +0800)]
imx: imx6ull: adjust the ldo 1.2v bandgap voltage
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop
MISC0 bit[6:4]) setting to 2b'110.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:49 +0000 (14:02 +0800)]
imx: mx6ull: Add AIPS3 initialization
Since the mx6ull adds the AIPS3, so enable its initialization.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:48 +0000 (14:02 +0800)]
imx: mx6ull: Update memory map address
Update memory map address for mx6ull.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:47 +0000 (14:02 +0800)]
imx: mx6ull: update clock settings and CCM register map
Update Clock settings and CCM register map for i.MX6ULL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:46 +0000 (14:02 +0800)]
imx: mx6ull: adjust POR_B setting for i.MX6ULL
Adjust POR_B settings on i.MX6ULL according to IC design
team's suggestion:
2'b00 : always PUP100K
2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL
2'b10 : always disable PUP100K
2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:45 +0000 (14:02 +0800)]
imx: mx6ull: misc soc update
Update misc SOC related settings for i.MX6ULL, such as FEC mac address,
cpu speed grading and mmdc channel mask clearing.
Also update s_init to skip pfd reset.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:44 +0000 (14:02 +0800)]
imx: mx6ul: using runtime check when configuring PMIC_STBY_REQ
Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here,
because this piece code is only for i.MX6UL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:43 +0000 (14:02 +0800)]
imx: mx6ull: skip setting ahb clock
Rom already initialized clock at 396M and 132M for arm core and ahb,
so skip setting them again in U-Boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:42 +0000 (14:02 +0800)]
imx: timer: update gpt driver for i.MX6ULL
The i.MX6ULL's GPT supportting taking OSC as clock source.
Add i.MX6ULL support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:41 +0000 (14:02 +0800)]
imx: ocotp: support i.MX6ULL
i.MX6ULL has two 128 bits fuse banks, bank 7 and bank 8,
while other banks use 256 bits. So we have to adjust the
word and bank index when accessing the bank 8.
When in command line `fuse read 8 0 1`, you can image
`fuse read 7 4 1` in the ocotp driver implementation for 6ULL.
When programming, we use word index, so need to fix bank7/8 programming
for i.mx6ull.
For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67.
But actully it should be (7 << 3 | 7) ---> 63.
So fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:40 +0000 (14:02 +0800)]
imx-common: introduce is_mx6ull
Introduce is_mx6ull macro.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Ye Li [Thu, 11 Aug 2016 06:02:39 +0000 (14:02 +0800)]
imx: mx6ull: add kconfig entry for MX6ULL
i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL.
If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULL
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:38 +0000 (14:02 +0800)]
imx: mx6ull: add mx6ull major cpu type
Add i.MX6ULL major cpu type.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 11 Aug 2016 06:02:37 +0000 (14:02 +0800)]
imx: mx6ull: add iomux header file
Add iomux header file for i.MX6ULL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Fri, 2 Sep 2016 20:16:45 +0000 (17:16 -0300)]
README.imx6: Fix Boundary Devices name
Correct name is "Boundary Devices".
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Soeren Moch [Thu, 22 Sep 2016 18:29:34 +0000 (20:29 +0200)]
board: tbs2910: Add CMD_PART
There is no stable mmcblk device numbering over different linux versions.
Enable CMD_PART to be able to query the UUID of the root filesystem partition.
So we can pass root=PARTUUID=XXX instead of root=/dev/mmcblkXpY in bootargs.
Leave the default environment as is for now to stay compatible with original
TBS settings.
Signed-off-by: Soeren Moch <smoch@web.de>
Ross Parker [Tue, 2 Aug 2016 08:08:07 +0000 (08:08 +0000)]
imx_watchdog: Do not assert WDOG_B on watchdog init
Currently the driver asserts WDOG_B by clearing WCR_WDA bit when
enabling the watchdog. Do not clear WCR_WDA.
Signed-off-by: Ross Parker <rossjparker@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Filip Brozovic [Wed, 14 Sep 2016 11:50:39 +0000 (13:50 +0200)]
imx: iomux-v3: fix pad setup on i.MX6DQP when CONFIG_MX6QDL is defined
The CPU detection macro is_mx6dq returns 0 on an i.MX6DQP, so we need to
check for it explicitly in order to correctly initialize the pads when
CONFIG_MX6QDL is defined.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Soeren Moch [Wed, 21 Sep 2016 11:16:21 +0000 (13:16 +0200)]
board: tbs2910: Fix BOOTMAPSZ
The linux kernel imx_v6_v7_defconfig sets the user/kernel memory split
to 3G/1G now (was 2G/2G before). We have to adapt the BOOTMAPSZ so that
the decompressor finds zImage and dtb in lowmem.
Signed-off-by: Soeren Moch <smoch@web.de>
Fabio Estevam [Mon, 26 Sep 2016 12:14:25 +0000 (09:14 -0300)]
mx6sabresd: Make SPL DDR configuration to match the DCD table
When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.
This causes stability issues like the ones reported at
7dbda25ecd6d7c
("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also:
http://lists.denx.de/pipermail/u-boot/2016-September/266355.html .
As the non-SPL code have been tested for long time and proves to be reliable,
let's configure the DDR in the exact same way as the non-SPL case.
The idea is simple: just use the DCD table and write directly to the DDR
registers.
Retrieved the DCD tables from:
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
and
board/freescale/mx6sabresd/mx6qp.cfg
(NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)
This method makes it easier for people converting from non-SPL to SPL code.
Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Mon, 12 Sep 2016 15:01:47 +0000 (12:01 -0300)]
wandboard: Remove videoargs script
The videoargs script is kernel version dependent and since wandboard
uses distro config, there is no need to handle videoargs locally.
In case such video related settings are needed, then the proper
location would be the distro extlinux.conf or boot.scr files.
So remove 'videoargs' script.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Mon, 12 Sep 2016 14:38:36 +0000 (11:38 -0300)]
wandboard: Fix hang when going into low frequency
A kernel hang is observed when running wandboard 3.14 kernel and
going to the lowest operational point of cpufreq:
# ifconfig eth0 down
# echo 1 > /sys/class/graphics/fb0/blank
The problem is caused by incorrect setting of the REFR field
of register MDREF. Setting it to 4 refresh commands per refresh
cycle fixes the hang.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tom Rini [Mon, 3 Oct 2016 13:28:13 +0000 (09:28 -0400)]
Prepare v2016.11-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 3 Oct 2016 13:09:29 +0000 (09:09 -0400)]
Merge git://git.denx.de/u-boot-rockchip
Andrew F. Davis [Tue, 30 Aug 2016 19:06:28 +0000 (14:06 -0500)]
ti_armv7_common: Disable Falcon Mode on HS devices
Authentication of images in Falcon Mode is not supported. Do not enable
SPL_OS_BOOT when TI_SECURE_DEVICE is enabled. This prevents attempting
to directly load kernel images which will fail, for security reasons,
on HS devices, the board is locked if a non-authenticatable image load
is attempted, so we disable attempting Falcon Mode.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:27 +0000 (14:06 -0500)]
config: Remove usage of CONFIG_STORAGE_EMMC
This config option seems to be unused and is probably vestigial.
Remove it.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:25 +0000 (14:06 -0500)]
ti: omap-common: Allow AM33xx devices to be built securely
Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high
security enabled models. Allow AM33xx devices to be built with
HS Device Type Support.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:24 +0000 (14:06 -0500)]
board: am33xx-hs: Allow post-processing of FIT image on AM33xx
When CONFIG_FIT_IMAGE_POST_PROCESS or CONFIG_SPL_FIT_IMAGE_POST_PROCESS
is enabled board_fit_image_post_process will be called, add this
function to am33xx boards when CONFIG_TI_SECURE_DEVICE is set to
verify the loaded image.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:23 +0000 (14:06 -0500)]
am33xx: config.mk: Fix option used to enable SPI SPL image type
The option SPL_SPI_SUPPORT is used to enable support in SPL for loading
images from SPI flash, it should not be used to determine the build type
of the SPL image itself. The ability to read images from SPI flash does
not imply the SPL will be booted from SPI flash.
Unconditionally build SPI flash compatible SPL images.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:22 +0000 (14:06 -0500)]
doc: Update info on using AM33xx secure devices from TI
Add a section describing the additional boot types used on AM33xx
secure devices.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:21 +0000 (14:06 -0500)]
am33xx: config.mk: Add support for additional secure boot image types
Depending on the boot media, different images are needed
for secure devices. The build generates u-boot*_HS_* files
as appropriate for the different boot modes.
For AM33xx devices additional image types are needed for
various SPL boot modes as the ROM checks for the name of
the boot mode in the file it loads.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:20 +0000 (14:06 -0500)]
Kconfig: Separate AM33XX SOC config from target board config
The config option AM33XX is used in several boards and should be
defined as a stand-alone option for this SOC. We break this out
from target boards that use this SoC and common headers then enable
AM33XX on in all the boards that used these targets to eliminate any
functional change with this patch.
This is similar to what has already been done in
9de852642cae ("arm: Kconfig: Add support for AM43xx SoC specific Kconfig")
and is done for the same reasons.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Daniel Allred [Fri, 2 Sep 2016 05:40:24 +0000 (00:40 -0500)]
ARM: omap5: add fdt secure dram reservation fixup
Adds a secure dram reservation fixup for secure
devices, when a region in the emif has been set aside
for secure world use. The size is defined by the
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE config option.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Daniel Allred [Fri, 2 Sep 2016 05:40:23 +0000 (00:40 -0500)]
ti_omap5_common: mark region of DRAM protected on HS parts
If the ending portion of the DRAM is reserved for secure
world use, then u-boot cannot use this memory for its relocation
purposes. To prevent issues, we mark this memory as PRAM and this
prevents it from being used by u-boot at all.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Daniel Allred [Fri, 2 Sep 2016 05:40:22 +0000 (00:40 -0500)]
ARM: DRA7: Add secure emif setup calls
After EMIF DRAM is configured, but before it is used,
calls are made on secure devices to reserve any configured
memory region needed by the secure world and then to lock the
EMIF firewall configuration. If any other firewall
configuration needs to be applied, it must happen before the
lock call.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Daniel Allred [Fri, 2 Sep 2016 05:40:21 +0000 (00:40 -0500)]
arm: omap5: secure API for EMIF memory reservations
Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Daniel Allred [Fri, 2 Sep 2016 05:40:20 +0000 (00:40 -0500)]
ti: omap5: Add Kconfig options for secure EMIF reservations
Adds start address and size config options for setting aside
a portion of the EMIF memory space for usage by security software
(like a secure OS/TEE). There are two sizes, a total size and a
protected size. The region is divided into protected (secure) and
unprotected (public) regions, that are contiguous and start at the
start address given. If the start address is zero, the intention
is that the region will be automatically placed at the end of the
available external DRAM space.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Jacob Chen [Mon, 19 Sep 2016 10:46:28 +0000 (18:46 +0800)]
rockchip: add boot-mode support for rk3288, rk3036
rockchip platform have a protocol to pass the the kernel reboot mode to bootloader
by some special registers when system reboot. In bootloader we should read it and take action.
We can only setup boot_mode in board_late_init becasue "setenv" need env setuped.
So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init"
to replace "board_late_init" in board file.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Jacob Chen [Mon, 19 Sep 2016 10:46:27 +0000 (18:46 +0800)]
rockchip: move common function from board-file to rk3036-board.c
To keep it same with 3288
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Jacob Chen [Mon, 19 Sep 2016 10:46:26 +0000 (18:46 +0800)]
rockchip: rename board.c to rk3288-board.c
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Jacob Chen [Mon, 19 Sep 2016 10:46:25 +0000 (18:46 +0800)]
rockchip: move partitons define from 3036-kylin to 3036-common
To keep it same with 3288.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Fri, 9 Sep 2016 13:44:50 +0000 (21:44 +0800)]
rockchip: miniarm: remove eMMC support
The latest rk3288-miniarm board doesn't have eMMC device, so remove it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:23 +0000 (15:57 +0800)]
config: evb-rk3399: enable pwm regulator
Enable the pwm regulator for evb-rk3399.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:22 +0000 (15:57 +0800)]
dts: evb-rk3399: add init voltage node for vdd-center
Add a regulator-init-microvolt for vdd_center regulator
so that we can get a init value for driver probe.
Not like pmic regulator, the PWM regulator do not have a
known default output value, so we would like to init the
regulator when driver probe.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:21 +0000 (15:57 +0800)]
Kconfig: rockchip: enable DM_PWM and DM_REGULATOR
Enable DM_PWM and DM_REGULATOR on rockchip SoCs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:20 +0000 (15:57 +0800)]
rockchip: evb_rk3399: init vdd_center regulator
Add vdd_center pwm regulator get_device to
enable this regulator.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:19 +0000 (15:57 +0800)]
power: regulator: add pwm regulator
add driver support for pwm regulator.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:18 +0000 (15:57 +0800)]
rockchip: rkpwm: fix the register sequence
Reference to kernel source code, rockchip pwm has three
type, we are using v2 for rk3288 and rk3399, so let's
update the register to sync with pwm_data_v2 in kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:17 +0000 (15:57 +0800)]
rockchip: rk3399: update PPLL and pmu_pclk frequency
Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
jacob2.chen [Mon, 29 Aug 2016 17:26:14 +0000 (01:26 +0800)]
rockchip: add usb mass storage feature support for rk3036
Enable ums feature for rk3036 boards, so that we can mount the mmc
device to PC.
Signed-off-by: jacob2.chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Sandy Patterson [Mon, 29 Aug 2016 11:31:17 +0000 (07:31 -0400)]
Enable ROCKCHIP_SPL_BACK_TO_BROM for rock2 board
Rock2 has been tested with back to brom feature. The tricky part is that
with this feature the default environment is inside u-boot, and it's
defined for every rk3288 board independetly. So I just changed it for
rock2 here if ROCKCHIP_SPL_BACK_TO_BROM.
Solve by moving environment after u-boot before 1M boundary
Signed-off-by: Sandy Patterson <apatterson@sightlogix.com>
Acked-by: Simon Glass <sjg@chromium.org>
Sandy Patterson [Mon, 29 Aug 2016 11:31:16 +0000 (07:31 -0400)]
Disable SPL_MMC_SUPPORT if ROCKCHIP_SPL_BACK_TO_BROM is enabled.
Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled.
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Sandy Patterson <apatterson@sightlogix.com>
Acked-by: Simon Glass <sjg@chromium.org>
Sandy Patterson [Wed, 10 Aug 2016 14:21:47 +0000 (10:21 -0400)]
rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabled
Move back_to_bootrom() call later in SPL init so that the console is
initialized and printouts happen.
Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console
output from the SPL init stages.
I wasn't sure exactly where this should happen, so if we are set to do
run spl_board_init, then go back to bootrom there after
preloader_console_init(). Otherwise fall back to old behavior of doing
it in board_init_f.
Signed-off-by: Sandy Patterson <apatterson@sightlogix.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Mon, 5 Sep 2016 01:39:58 +0000 (09:39 +0800)]
rockchip: rk3288: sdram: fix DDR address range
The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe000000~0xff000000. Actually, some IP
controller can't address to, so let's limit the available range.
This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe000000. So that DMAC didn't work sane.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Heiko Schocher [Mon, 29 Aug 2016 05:46:11 +0000 (07:46 +0200)]
net, macb: fix misaligned cache operation warning
when using tftp on the smartweb board, it prints a lot of
CACHE: Misaligned operation at range [
23b2e000,
23b2e100]
warnings ... fixed them.
Signed-off-by: Heiko Schocher <hs@denx.de>
Lokesh Vutla [Fri, 16 Sep 2016 04:47:53 +0000 (10:17 +0530)]
ti_armv7_keystone2: Update addr_mon variable
As boot monitor contains a mkimage header, it can be loaded at any location.
So, have a common addr_mon address across all keystone2 SoCs. And also
making sure that boot monitor is installed early during default boot to
avoid any overlapping with other images.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Fri, 16 Sep 2016 04:47:12 +0000 (10:17 +0530)]
ARM: keystone2: Add support for parsing monitor header
Given that boot monitor image is being generated to a specific target location
depending on the SoC and U-boot relies on addr_mon env variable to be aligned
with boot monitor target location. When ever the target address gets updated in
boot monitor, it is difficult to sync between u-boot and boot monitor and also
there is no way to update user that boot monitor image is updated.
To avoid this problem, boot monitor image is being generated with mkimage
header. Adding support in mon_install command for parsing this header.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Murali Karicheri [Thu, 15 Sep 2016 13:44:32 +0000 (19:14 +0530)]
keystone2: k2g: add env script to load firmware initramfs as part of boot flow
On K2G, the PCIe SerDes h/w is a re-use from other K2 devices and SerDes
driver requires a firmware image to initialize the SerDes h/w device.
This is firmware is part of the initramfs file that is loaded to memory
in u-boot and passed to kernel as in other K2 platforms. This patch
customize the u-boot env to have this done automatically when the K2G EVM
boots up. With this, a user may be able to boot the EVM with a standard
PCIe card at the x1 PCIe slot and release image and test PCIe devices
such as NIC, SATA etc.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Sat, 27 Aug 2016 11:49:16 +0000 (17:19 +0530)]
board: k2g: Enable ECC byte lane
Enable ECC byte lane for k2g-evm
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Sat, 27 Aug 2016 11:49:15 +0000 (17:19 +0530)]
board: ks2: Enable ECC using detected DDR size
EEC is being enabled based on the ddr size populated by SPD data.
But not all keystone platforms have SPD data to detect ddr3 size.
So, enable ECC using the detected DDR size.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Petr Kulhavy [Fri, 9 Sep 2016 08:27:18 +0000 (10:27 +0200)]
fastboot: move FASTBOOT_FLASH options into Kconfig
Move FASTBOOT_MBR_NAME and FASTBOOT_GPT_NAME into Kconfig.
Add dependency on the FASTBOOT_FLASH setting (also for FASTBOOT_MBR_NAME).
Remove the now redundant GPT_ENTRY_NAME.
Signed-off-by: Petr Kulhavy <brain@jikos.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Add FIXME about xxx_PARTITION needing to be in Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
Petr Kulhavy [Fri, 9 Sep 2016 08:27:17 +0000 (10:27 +0200)]
disk: part: refactor generic name creation for DOS and ISO
In both DOS and ISO partition tables the same code to create partition name
like "hda1" was repeated.
Code moved to into a new function part_set_generic_name() in part.c and optimized.
Added recognition of MMC and SD types, name is like "mmcsda1".
Signed-off-by: Petr Kulhavy <brain@jikos.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Petr Kulhavy [Fri, 9 Sep 2016 08:27:16 +0000 (10:27 +0200)]
fastboot: add support for writing MBR
Add special target "mbr" (otherwise configurable via CONFIG_FASTBOOT_MBR_NAME)
to write MBR partition table.
Partitions are now searched using the generic function which finds any
partiiton by name. For MBR the partition names hda1, sda1, etc. are used.
Signed-off-by: Petr Kulhavy <brain@jikos.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Petr Kulhavy [Fri, 9 Sep 2016 08:27:15 +0000 (10:27 +0200)]
disk: part: implement generic function part_get_info_by_name()
So far partition search by name has been supported only on the EFI partition
table. This patch extends the search to all partition tables.
Rename part_get_info_efi_by_name() to part_get_info_by_name(), move it from
part_efi.c into part.c and make it a generic function which traverses all part
drivers and searches all partitions (in the order given by the linked list).
For this a new variable struct part_driver.max_entries is added, which limits
the number of partitions searched. For EFI this was GPT_ENTRY_NUMBERS.
Similarly the limit is defined for DOS, ISO, MAC and AMIGA partition tables.
Signed-off-by: Petr Kulhavy <brain@jikos.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
Zubair Lutfullah Kakakhel [Fri, 9 Sep 2016 08:18:58 +0000 (09:18 +0100)]
bootm: fix passing argc to standalone apps
This bug appears in
b6396403 which makes u-boot unable to pass
arguments via bootm to a standalone application without this patch.
Steps to reproduce.
Compile a u-boot. Use mkimage to package the standalone hello_world.bin
file.
e.g. For the MIPS Boston platform
mkimage -n "hello" -A mips -O u-boot -C none -T standalone \
-a 0xffffffff80200000 -d hello_world.bin \
-ep 0xffffffff80200000 hello_out
Then tftp hello_out and run it using
boston # dhcp 192.168.154.45:hello_out
...
boston # bootm $loadaddr 123 321
Without the patch the following output is observed.
boston # bootm $loadaddr 123 321
Image Name: hello
Image Type: MIPS U-Boot Standalone Program (uncompressed)
Data Size: 1240 Bytes = 1.2 KiB
Load Address:
80200000
Entry Point:
80200000
Verifying Checksum ... OK
Loading Standalone Program ... OK
Example expects ABI version 8
Actual U-Boot ABI version 8
Hello World
argc = 0
argv[0] = "0xffffffff88000000"
With the patch, you see the following.
boston # bootm $loadaddr 123 321
Image Name: hello
Image Type: MIPS U-Boot Standalone Program (uncompressed)
Data Size: 1240 Bytes = 1.2 KiB
Load Address:
80200000
Entry Point:
80200000
Verifying Checksum ... OK
Loading Standalone Program ... OK
Example expects ABI version 8
Actual U-Boot ABI version 8
Hello World
argc = 3
argv[0] = "0xffffffff88000000"
argv[1] = "123"
argv[2] = "321"
argv[3] = "<NULL>"
Without the patch, the go command at the entry point seems to work.
boston # go 0xffffffff80200000 123 321
Example expects ABI version 8
Actual U-Boot ABI version 8
Hello World
argc = 3
argv[0] = "0xffffffff80200000"
argv[1] = "123"
argv[2] = "321"
argv[3] = "<NULL>"
Hit any key to exit ...
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Thu, 8 Sep 2016 09:47:36 +0000 (18:47 +0900)]
input: specify the default of I8042_KEYB in more correct manner
Creating multiple entries of "config FOO" often gives us bad
experiences. In this case, we should specify "default X86"
as platforms that want this keyboard by default.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Thu, 8 Sep 2016 09:47:35 +0000 (18:47 +0900)]
sandbox, x86: select DM_KEYBOARD instead of default y entry
Once we migrate to DM-based drivers, we cannot go back to legacy
ones, i.e. config options like DM_* are not user-configurable.
Make SANDBOX and X86 select DM_KEYBOARD like other platforms do.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 1 Oct 2016 01:59:11 +0000 (21:59 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-nds32
Tom Rini [Sat, 1 Oct 2016 01:58:44 +0000 (21:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
include/configs/dra7xx_evm.h
rick [Thu, 14 Apr 2016 06:32:27 +0000 (14:32 +0800)]
nds32: Support relocation.
Enable pie option for relocation.
Signed-off-by: rick <rick@andestech.com>
Cc: Andes <uboot@andestech.com>
Sriram Dash [Wed, 17 Aug 2016 06:17:54 +0000 (11:47 +0530)]
mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261
Apply the erratum A006261 for the following Socs:
P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1
Do not apply erratum A006261 for the following Socs:
T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081
Erratum A006261 is applicable for the following Socs:
P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1),
P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0),
P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1).
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sriram Dash [Wed, 17 Aug 2016 06:17:53 +0000 (11:47 +0530)]
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010
CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy
offset are set to enable the initial setting of Usb Phy for P1010.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sriram Dash [Wed, 17 Aug 2016 06:17:52 +0000 (11:47 +0530)]
mpc85xx: powerpc: usb: Modified the erratum A006261 according to endianness
Modifies erratum implementation due to the fact that P3041,
P5020, and P5040 are all big endian for the USB PHY registers, but
they were specified little endian.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sriram Dash [Fri, 23 Sep 2016 07:27:52 +0000 (12:57 +0530)]
drivers: usb: xhci-fsl: Implement Erratum A-010151 for FSL USB3 controller
Currently the controller by default enables the Receive Detect feature in P3
mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
detection in P3 mode.
Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
Detect feature is required.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Sriram Dash [Fri, 16 Sep 2016 11:42:16 +0000 (17:12 +0530)]
usb: fsl: Renaming fdt_fixup_erratum and fdt_fixup_usb_erratum
The functions fdt_fixup_erratum and fdt_fixup_usb_erratum are
fsl/nxp specific. So, make them explicit by renaming them
fsl_fdt_fixup_erratum and fsl_fdt_fixup_usb_erratum
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Sriram Dash [Fri, 16 Sep 2016 11:42:15 +0000 (17:12 +0530)]
usb: fsl: Rename fdt_fixup_dr_usb
The function fdt_fixup_dr_usb is specific to fsl/nxp. So,
make the function name explicit and rename fdt_fixup_dr_usb
into fsl_fdt_fixup_dr_usb.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Marcel Ziswiler [Wed, 14 Sep 2016 22:54:00 +0000 (00:54 +0200)]
apalis_t30: colibri_imx7: colibri_t30: fix ethernet functionality
Since commit
aa7a648747d8c704a9a81c9e493d386930724e9d
("net: Stop including NFS overhead in defragment max") the following
has been reproducibly observed while trying to transfer data over TFTP:
Load address: 0x80408000
Loading: EHCI timed out on TD - token=0x8008d80
T EHCI timed out on TD - token=0x88008d80
Rx: failed to receive: -5
This patch fixes this by lowering our TFTP block size to be within the
standard maximal de-fragmentation aka IP packet size again.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Sanchayan Maity [Tue, 9 Aug 2016 18:15:02 +0000 (23:45 +0530)]
configs: colibri_vf_defconfig: Enable USB driver model for Colibri Vybrid
Enable USB driver model for Toradex Colibri Vybrid modules.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>