peter klausler [Thu, 29 Jul 2021 19:02:45 +0000 (12:02 -0700)]
[flang] Implement runtime Assign()
Define an API for, and implement, runtime support for arbitrary
assignment of one descriptor's data to another, with full support for
(re)allocation of allocatables with finalization when necessary,
user-defined derived type assignment TBP calls, and intrinsic (default)
componentwise assignment of derived type instances with allocation of
automatic components. Also clean up API and implementation of
finalization/destruction using knowledge gained while studying
edge cases for assignment in the 2018 standard.
The look-up procedure for special procedure bindings in derived
types has been optimized from O(N) to O(1) since it will probably
matter more. This required some analysis in runtime derived type
description table construction in semantics and some changes to the
table schemata.
Executable Fortran tests have been developed; they'll be added
to the test base once they can be lowered and run by f18.
Differential Revision: https://reviews.llvm.org/D107678
Mark de Wever [Thu, 5 Aug 2021 19:34:52 +0000 (21:34 +0200)]
[libc++][doc] Improve contributor documentation.
Shorty before branching LLVM 13 a new CMake option was added. This
option `LIBCXX_ENABLE_INCOMPLETE_FEATURES` lacks the contributor
documentation. This patch rectifies that issue.
Differential Revision: https://reviews.llvm.org/D107596
Mark de Wever [Sun, 8 Aug 2021 09:02:07 +0000 (11:02 +0200)]
[libc++][NFC] Remove MSVC specific code.
Switching `__builtin_clzll` to `__libcpp_clz` should work on all
platforms and no longer require MSVC specific code.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D107709
Raphael Isemann [Mon, 9 Aug 2021 15:53:21 +0000 (17:53 +0200)]
[lldb][NFC] Remove never read member variable IOHandler::m_editing
The last read access to this variable was removed in 2015 in
4446487d71c52a925c04acfcae44dec8a8d62e00 .
Michał Górny [Mon, 9 Aug 2021 15:43:37 +0000 (17:43 +0200)]
[lldb] [test] Mark vFile tests as LLGS-specific
Robin Giese [Mon, 9 Aug 2021 15:16:12 +0000 (17:16 +0200)]
[lldb] Fix break introduced in 14735ca
The `File::OpenOptions` were renamed; this fixes up a callsite that breaks for
macOS builds. (See
https://github.com/llvm/llvm-project/commit/
14735cab655441ba45c4b88ad82f11267e5fe916)
Differential Revision: https://reviews.llvm.org/D107767
Ivan Zhechev [Mon, 9 Aug 2021 14:44:27 +0000 (15:44 +0100)]
[Flang] Ported test_symbols to Python
Due to unavailability of Flang testing on Windows, the shell scripts
are being ported to Python. The following changes are being made in
this patch: removed test_symbols.sh and common.sh, and ported them
to Python. Changes to the tests themselves so that they use the
python scripts instead of the shell script.
Reviewed By: Meinersbur, awarzynski, kiranchandramohan
Differential Revision: https://reviews.llvm.org/D107041
Mark Danial [Mon, 9 Aug 2021 14:24:22 +0000 (14:24 +0000)]
Update: clang/test/Profile/gcc-flag-compatibility.c to have -flto on AIX
Reviewed By: Whitney
Differential Revision: https://reviews.llvm.org/D106815
Kazu Hirata [Mon, 9 Aug 2021 14:27:04 +0000 (07:27 -0700)]
[DWARF] Remove findRange (NFC)
The last use was removed on Apr 15, 2019 in commit
f56a436891e998363bcc02ea09a58d38e0b39da3.
Guillaume Chatelet [Mon, 9 Aug 2021 14:05:22 +0000 (14:05 +0000)]
[libc] Update size distributions for memory benchmarks
All distributions have been updated using 7 days worth of data.
Bradley Smith [Thu, 5 Aug 2021 13:15:47 +0000 (13:15 +0000)]
[AArch64][SVE] Fix assertion failure when lowering fixed length gather/scatter
The patterns for fixed length gather/scatter with 32-bit offsets and
64-bit memory type are slightly different that the rest of the patterns,
as such the lowering needs to be slightly different to ensure the
correct types are used.
Differential Revision: https://reviews.llvm.org/D107576
Anton Afanasyev [Mon, 9 Aug 2021 10:01:09 +0000 (13:01 +0300)]
[Test] Precommit tests for PR50555
Paul Robinson [Mon, 9 Aug 2021 13:38:28 +0000 (06:38 -0700)]
Reapply "[lit] Have REQUIRES support the target triple"
This reverts commit
3229c971512404c512e041c3e88f22dbec2b650b.
With a2acac6 in place this should provide enough info to work out
any repeat of the failure in cross_ovver_uniform_dist.test.
Michał Górny [Mon, 9 Aug 2021 13:42:17 +0000 (15:42 +0200)]
[lldb] [test] Use Windows-friendly modes in vFile O_CREAT tests
Michał Górny [Mon, 9 Aug 2021 13:38:38 +0000 (15:38 +0200)]
[lldb] [test] Mark new vFile tests as XFAIL on Windows
Arthur O'Dwyer [Fri, 6 Aug 2021 18:35:03 +0000 (14:35 -0400)]
[libc++] [test] IWYU in <concepts> tests.
Sven van Haastregt [Mon, 9 Aug 2021 12:42:37 +0000 (13:42 +0100)]
[OpenCL] Add missing virtual destructor
Followup after
f9ffe61fb53f ("[OpenCL] Factor out
OpenCLBuiltinFileEmitterBase; NFC", 2021-08-09) introduced a
-Wnon-virtual-dtor warning.
Michał Górny [Mon, 9 Aug 2021 12:11:32 +0000 (14:11 +0200)]
[lldb] [test] Fix TestGdbRemotePlatformFile with non-022 umask
Paul Robinson [Mon, 9 Aug 2021 12:10:42 +0000 (05:10 -0700)]
Have compiler-rt/test/fuzzer report info to help diagnose a test issue
Jeremy Morse [Mon, 9 Aug 2021 11:40:21 +0000 (12:40 +0100)]
[DWARF] Revert sharing subprograms across CUs
This patch is a revert of
e08f205f5c2c. In that patch, DW_TAG_subprograms
were permitted to be referenced across CU boundaries, to improve stack
trace construction using call site information. Unfortunately, as
documented in PR48790, the way that subprograms are "owned" by dwarf units
is sufficiently complicated that subprograms end up in unexpected units,
invalidating cross-unit references.
There's no obvious way to easily fix this, and several attempts have
failed. Revert this to ensure correct DWARF is always emitted.
Three tests change in addition to the reversion, but they're all very
light alterations.
Differential Revision: https://reviews.llvm.org/D107076
Kim-Anh Tran [Mon, 9 Aug 2021 11:14:41 +0000 (13:14 +0200)]
[DWARF5] Fix offset check when using .debug_names
When going through the CU entries in the name index,
make sure to compare the name entry's CU
offset against the skeleton CU's offset.
Previously there would be a mismatch, since the
wrong offset was compared, and thus no suitable
entry was found.
Reviewed By: jankratochvil
Differential Revision: https://reviews.llvm.org/D106270
Sven van Haastregt [Mon, 9 Aug 2021 10:41:25 +0000 (11:41 +0100)]
[OpenCL] Factor out OpenCLBuiltinFileEmitterBase; NFC
Factor out functionality that can be shared with a header file emitter
that is to be added in the future.
Michał Górny [Wed, 4 Aug 2021 16:17:34 +0000 (18:17 +0200)]
[lldb] [gdb-remote] Use hexadecimal numbers in vFile packats for GDB compliance
Use hexadecimal numbers rather than decimal in various vFile packets
in order to fix compatibility with gdbserver. This also changes the few
custom LLDB packets -- while technically they do not have to be changed,
it is easier to use the same syntax consistently across LLDB.
Differential Revision: https://reviews.llvm.org/D107475
Michał Górny [Wed, 28 Jul 2021 18:37:52 +0000 (20:37 +0200)]
[lldb] [gdb-remote] Sync vFile:open mode constants with GDB
Sync the mode constants used to drive vFile:open requests with these
used by GDB and defined for the gdb remote protocol. This makes it
possible to use 'platform file open' after connecting to gdbremote
server (and to some degree to operate on the open file modulo other
incompatibilities).
Differential Revision: https://reviews.llvm.org/D106985
Michał Górny [Wed, 28 Jul 2021 18:07:03 +0000 (20:07 +0200)]
[lldb] [gdb-remote] Add eOpenOptionReadWrite for future gdb compat
Modify OpenOptions enum to open the future path into synchronizing
vFile:open bits with GDB. Currently, LLDB and GDB use different flag
models effectively making it impossible to match bits. Notably, LLDB
uses two bits to indicate read and write status, and uses union of both
for read/write. GDB uses a value of 0 for read-only, 1 for write-only
and 2 for read/write.
In order to future-proof the code for the GDB variant:
1. Add a distinct eOpenOptionReadWrite constant to be used instead
of (eOpenOptionRead | eOpenOptionWrite) when R/W access is required.
2. Rename eOpenOptionRead and eOpenOptionWrite to eOpenOptionReadOnly
and eOpenOptionWriteOnly respectively, to make it clear that they
do not mean to be combined and require update to all call sites.
3. Use the intersection of all three flags when matching against
the three possible values.
This commit does not change the actual bits used by LLDB.
Differential Revision: https://reviews.llvm.org/D106984
Alex Zinenko [Mon, 9 Aug 2021 09:07:54 +0000 (11:07 +0200)]
[mlir] support nD vector forms of shifts in std-to-llvm conversion
These ops were not ported to the nD vector conversion when it was introduced
and nobody needed them so far.
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D107750
Fraser Cormack [Wed, 4 Aug 2021 10:07:34 +0000 (11:07 +0100)]
[RISCV] Improve codegen for shuffles with LHS/RHS splats
Shuffles which are broken into separate halves reveal splats in which
a half is accessed via one index; such operations can be optimized to
use "vrgather.vi".
This optimization could be achieved by adding extra patterns to match
`vrgather_vv_vl` which uses a splat as an index operand, but this patch
instead identifies splat earlier. This way, future optimizations can
build on top of the data gathered here, e.g., to splat-gather dominant
indices and insert any leftovers.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D107449
Hsiangkai Wang [Tue, 3 Aug 2021 23:57:13 +0000 (07:57 +0800)]
[RISCV] Half-precision for vget/vset.
Differential Revision: https://reviews.llvm.org/D107433
Fraser Cormack [Tue, 3 Aug 2021 16:02:43 +0000 (17:02 +0100)]
[RISCV] Add tests covering shuffles which can be optimized
These shuffles all take the form of a "splat" of the LHS and/or RHS to
some degree, with one or two elements needing patched up afterwards. We
currently lower all of these to full LHS/RHS vector-index shuffles with
vrgather.vv.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D107447
Muhammad Omair Javaid [Mon, 9 Aug 2021 07:47:32 +0000 (12:47 +0500)]
[LLDB] Skip random fails on Arm/AArch64 Linux buildbot
Following tests fail on Arm/AArch64 randomly with timeouts:
TestMultilineNavigation.py
TestBatchMode.py
TestUnicode.py
TestGdbRemote_vContThreads.py
I am marking them as skipped until we find a away make to pass reliably.
Igor Kudrin [Mon, 9 Aug 2021 08:43:32 +0000 (15:43 +0700)]
[llvm-objcopy][ELF][NFC] Remove unneeded methods of Object
The patch removes mutable accessor methods for sections and segments.
As for now, const variants of them are not used because all callers have
mutable access to an instance of Object. On the other hand, they do not
actually modify the sets, so it looks better to keep only const ones.
Differential Revision: https://reviews.llvm.org/D107652
Martin Storsjö [Fri, 6 Aug 2021 06:22:11 +0000 (09:22 +0300)]
[profile] Build with -fms-extensions in MinGW mode
54902e00d1280785042e2c7ec71b25a949ade92c added a use of
/alternatename via a #pragma comment(linker); in MinGW mode, this
requires building with -fms-extensions. (This flag is added to
SANITIZER_COMMON_CFLAGS in the toplevel CMakeLists.txt.)
This avoids a warning when building in MinGW mode (about an unknown
pragma being ignored), and presumably also makes the code work as
intended.
Differential Revision: https://reviews.llvm.org/D107620
Martin Storsjö [Fri, 6 Aug 2021 06:19:25 +0000 (09:19 +0300)]
[InstrProfiling] Fix warnings when building for Windows
The Headers.CountersDelta field is an uint64_t, not a pointer,
so just cast to uint32_t to truncate it.
Differential Revision: https://reviews.llvm.org/D107619
Esme-Yi [Mon, 9 Aug 2021 08:36:39 +0000 (08:36 +0000)]
fix the error caused by D107333:
llvm/tools/llvm-readobj/XCOFFDumper.cpp:464:5: error:
call to member function 'printNumber' is ambiguous
W.printNumber("Length", StrTabSize);
Martin Storsjö [Fri, 6 Aug 2021 08:36:21 +0000 (11:36 +0300)]
[CMake] Improve GetHostTriple for Windows/ARM configurations
In MSVC mode, CMake provides CMAKE_C_COMPILER_ARCHITECTURE_ID,
which should be accurate for what the compiler produces. Keep
the old CMAKE_C_SIZEOF_VOID_P based fallback in case this
doesn't provide matches.
In GCC/MinGW mode, CMake doesn't provide that. As we're trying to
guess the default host architecture, use CMAKE_HOST_SYSTEM_PROCESSOR
in combination with the existing CMAKE_C_SIZEOF_VOID_P check to
estimate whether it's x86/x86_64/arm/aarch64.
Differential Revision: https://reviews.llvm.org/D107626
Luo, Yuanke [Sun, 8 Aug 2021 12:26:25 +0000 (20:26 +0800)]
[NFC] Fix the formula for reciprocal calculation.
Differential Revision: https://reviews.llvm.org/D107713
Christian Kühnel [Wed, 4 Aug 2021 14:26:37 +0000 (14:26 +0000)]
[doc] added section on generating the html doc
Added a new section on generating the html documentation
from the rst/md sources to our documentation.
Background: I wanted to check what my documenation
changes would look like on the website and had a hard
time finding how to do that. So I wanted to save other
folks the effort.
Differential Revision: https://reviews.llvm.org/D107460
David Green [Mon, 9 Aug 2021 07:24:28 +0000 (08:24 +0100)]
[ARM] Regenerate ARM neon-copy.ll test. NFC
This test didn't include all test check lines, thanks to .'s in function
names. It also changed the triple to hard float to make a more
interesting test for NEON code generation.
Min-Yih Hsu [Mon, 9 Aug 2021 07:04:20 +0000 (00:04 -0700)]
[M68k] Use separate asm operand class for different widths of address
This could help asm parser to pick the correct variant of instruction.
This patch also migrated all the control instructions MC tests.
Min-Yih Hsu [Sun, 8 Aug 2021 22:41:03 +0000 (15:41 -0700)]
[M68k][NFC] Coalesce render methods in different asm register op class
And assign RegClass (i.e. operand class for all GPR) as the super class
of ARegClass and DRegClass. Note that this is a NFC change because
actually we already had XRDReg to model either address or data register
operands (as well as test coverage for it). The new super class syntax
added here is just making the relations between three RegClass-es more
explicit.
Cullen Rhodes [Mon, 9 Aug 2021 06:52:47 +0000 (06:52 +0000)]
[AArch64] NFC: Remove DecodeVectorRegisterClass from disassembler
The decoder function and table are the same as FPR128, use that instead.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D107644
Esme-Yi [Mon, 9 Aug 2021 06:47:15 +0000 (06:47 +0000)]
[llvm-readobj][XCOFF] Print the length of the string table.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D107333
Pan, Tao [Mon, 9 Aug 2021 05:50:26 +0000 (13:50 +0800)]
Fix gcc build error after D105519
Same as
3bec7ed59e1b
Reviewed By: sbc100
Differential Revision: https://reviews.llvm.org/D107422
Simon Atanasyan [Sun, 8 Aug 2021 05:09:59 +0000 (08:09 +0300)]
[MC][ELF] Do not error on parsing .debug_* section directive for MIPS
MIPS .debug_* sections should have SHT_MIPS_DWARF section type to
distinguish among sections contain DWARF and ECOFF debug formats, but in
assembly files these sections have SHT_PROGBITS (@progbits) type. Now
assembler shows 'changed section type for ...' error when parsing
`.section .debug_*,"",@progbits` directive for MIPS targets.
The same problem exists for x86-64 target and this patch extends
workaround implemented in D76151. The patch adds one more case
when assembler ignores section types mismatch after `SwitchSection()`
call.
Differential Revision: https://reviews.llvm.org/D107707
Christudasan Devadasan [Mon, 9 Aug 2021 05:13:39 +0000 (01:13 -0400)]
Revert "SROA: Enhance speculateSelectInstLoads"
This reverts commit
ffc3fb665d0a0dccd64cc8c803ad8cc1a0d5dfa1.
Michael Liao [Mon, 9 Aug 2021 02:37:30 +0000 (22:37 -0400)]
[LowerMemIntrinsics] Typo fix.
Craig Topper [Mon, 9 Aug 2021 01:29:22 +0000 (18:29 -0700)]
[RISCV] Add optimizations for FMV_X_ANYEXTH similar to FMV_X_ANYEXTW_RV64.
This enables the fneg and fabs combines we have for FMV_X_ANYEXTW_RV64.
Craig Topper [Mon, 9 Aug 2021 01:18:53 +0000 (18:18 -0700)]
[RISCV] Remove -target-abi from half-bitmanip-dagcombines.ll.
This should be testing the custom ISD nodes we use for passing
half values in GPRs.
We should optimize these to integer operations, but we currently
don't.
Craig Topper [Sun, 8 Aug 2021 23:58:50 +0000 (16:58 -0700)]
[RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC
Previously we converted ISD condition codes to integers and stored
them directly in our MIR instructions. The ISD enum kind of belongs
to SelectionDAG so that seems like incorrect layering.
This patch instead uses a CondCode node on RISCV::SELECT_CC until
isel and then converts it from ISD encoding to a RISCV specific value.
This value can be converted to/from the RISCV branch opcodes in the
RISCV namespace.
My larger motivation is to possibly support a microarchitectural
feature of some CPUs where a short forward branch over a single
instruction can be predicated internally. This will require a new
pseudo instruction for select that needs to carry a branch condition
and live probably until RISCVExpandPseudos. At that point it can be
expanded to control flow without other instructions ending up in the
predicated basic block. Using an ISD encoding in RISCVExpandPseudos
doesn't seem like correct layering.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D107400
Craig Topper [Sun, 8 Aug 2021 22:57:39 +0000 (15:57 -0700)]
[RISCV] Move the $rs operand of PseudoStore from outs to ins. NFC
This is the data to be stored so it should be an input.
To keep operand order similar between loads and stores, move the temp
register to the first dest operand of floating point loads. Rework
the assembler code accordingly.
This doesn't have any functional effect because this Pseudo is only
used by the assembler which doesn't use ins/outs.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D107309
Min-Yih Hsu [Sun, 8 Aug 2021 21:20:46 +0000 (14:20 -0700)]
[M68k] Update disassembler test case following up ADD / ADDA changes
Update disassembler test case to reflect the changes on ADD/ADDA
instruction separation.
Sam McCall [Sun, 8 Aug 2021 19:04:53 +0000 (21:04 +0200)]
[clangd] Populate-switch triggers when the whole condition is selected.
This allows vscode to find it as a diagnostic quickfix for -Wswitch.
While here, group the code into chunks and add a couple more comments.
Kazu Hirata [Sun, 8 Aug 2021 15:57:32 +0000 (08:57 -0700)]
[DWARF] Remove collectChildrenAddressRanges (NFC)
The last use was removed on Dec 21, 2018 in commit
c3f30a7fc6a166910d4b674301e9108f537daf3c.
Dimitry Andric [Sat, 7 Aug 2021 19:39:11 +0000 (21:39 +0200)]
[libomptarget][amdgpu] use --allow-shlib-undefined to link on FreeBSD
On FreeBSD, the `environ` symbol is undefined at link time for shared
libraries, but resolved by the dynamic linker at runtime. Therefore,
allow the symbol to be undefined when creating a shared library, by
using the `--allow-shlib-undefined` linker flag, instead of `-z defs`
(a.k.a `--no-undefined`).
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D107698
Dimitry Andric [Sat, 7 Aug 2021 19:55:19 +0000 (21:55 +0200)]
[mlir] Avoid including <alloca.h> on FreeBSD and NetBSD
Instead, include `<cstdlib>` which is the canonical header containing
the declaration of `alloca()`.
Reviewed By: bondhugula
Differential Revision: https://reviews.llvm.org/D107699
Dorit Nuzman [Thu, 17 Jun 2021 15:39:09 +0000 (18:39 +0300)]
[LV] Support Interleaved Store Group With Gaps
Teach LV to use masked-store to support interleave-store-group with
gaps (instead of scatters/scalarization).
The symmetric case of using masked-load to support
interleaved-load-group with gaps was introduced a while ago, by
https://reviews.llvm.org/D53668; This patch completes the store-scenario
leftover from D53668, and solves PR50566.
Reviewed by: Ayal Zaks
Differential Revision: https://reviews.llvm.org/D104750
Min-Yih Hsu [Sat, 7 Aug 2021 23:37:35 +0000 (16:37 -0700)]
[M68k] Separate ADDA from ADD and migrate rest of the arithmetic MC tests
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed
together, which not only violated Motorola assembly's syntax but also
made asm parsing more difficult. This patch separates these two kinds of
instructions migrate rest of the tests from
test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic.
Note that we observed minor regressions on codegen quality: Sometimes
isel uses ADD instead of ADDA even the latter can lead to shorter
sequence of code. This issue implies that some isel patterns might need
to be updated.
Min-Yih Hsu [Sun, 8 Aug 2021 00:07:28 +0000 (17:07 -0700)]
Update `llvm-readobj` command invocation in extract-section.py
Change `-elf-output-style` to `--elf-output-style` to reflect the recent
changes on short/long CLI options in LLVM binary utils.
Craig Topper [Sun, 8 Aug 2021 00:11:11 +0000 (17:11 -0700)]
[RISCV] Autogenerate test. NFC
Craig Topper [Sat, 7 Aug 2021 22:53:46 +0000 (15:53 -0700)]
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
The fcvt fp to integer instructions saturate if their input is
infinity or out of range, but the instructions produce a maximum
integer for nan instead of 0 required for the ISD opcodes.
This means we can use the instructions to do the saturating
conversion, but we'll need to fix up the nan case at the end.
We can probably improve the i8 and i16 default codegen as well,
but I'll leave that for a follow up.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D107230
Jonas Devlieghere [Sat, 7 Aug 2021 01:41:55 +0000 (18:41 -0700)]
[lldb] Move Objective-C constants into ObjCConstants.h
Move Objective-C constants into ObjCConstants.h and share them between
Cocoa and AppleObjCTypeEncodingParser.
Differential revision: https://reviews.llvm.org/D107679
Nikita Popov [Sat, 8 May 2021 18:39:54 +0000 (20:39 +0200)]
[MemCpyOpt] Remove MemDepAnalysis-based implementation
The MemorySSA-based implementation has been enabled for a few months
(since D94376). This patch drops the old MDA-based implementation
entirely.
I've kept this to only the basic cleanup of dropping various
conditions -- the code could be further cleaned up now that there
is only one implementation.
Differential Revision: https://reviews.llvm.org/D102113
Rainer Orth [Sat, 7 Aug 2021 19:14:15 +0000 (21:14 +0200)]
[clang] Fix libclang linking on Solaris
Linking `libclang.so` is currently broken on Solaris:
ld: fatal: option --version-script requires option -z gnu-version-script-compat to be specified
While Solaris `ld` supports a considerable subset of `--version-script`,
there are some elements of the syntax that aren't.
The fix is equivalent to D78510 <https://reviews.llvm.org/D78510>.
Additionally, use of C-style comments is a GNU extension
that can easily be avoided by using `#` as comment character, which is
supported by GNU `ld`, `gold`, and `lld`.
Tested on `amd64-pc-solaris2.11`, `sparcv9-sun-solaris2.11`,
`x86_64-pc-linux-gnu`.
Differential Revision: https://reviews.llvm.org/D107559
Krishna [Sat, 7 Aug 2021 15:56:49 +0000 (21:26 +0530)]
[InstCombine] Remove nnan requirement for transformation to fabs from select
In this patch, the "nnan" requirement is removed for the canonicalization of select with fcmp to fabs.
(i) FSub logic: Remove check for nnan flag presence in fsub. Example: https://alive2.llvm.org/ce/z/751svg (fsub).
(ii) FNeg logic: Remove check for the presence of nnan and nsz flag in fneg. Example: https://alive2.llvm.org/ce/z/a_fsdp (fneg).
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D106872
Ye Luo [Sat, 7 Aug 2021 16:31:03 +0000 (12:31 -0400)]
[OpenMP] mark target task untied
OpenMP specification Tasking Terminology
target task :A mergeable and untied task that ...
Reviewed By: tianshilei1992
Differential Revision: https://reviews.llvm.org/D107686
Craig Topper [Sat, 7 Aug 2021 15:56:31 +0000 (08:56 -0700)]
[clang][NFC] Fix a -Wparentheses warning.
Craig Topper [Sat, 7 Aug 2021 05:19:38 +0000 (22:19 -0700)]
[X86] Teach shouldSinkOperands to recognize pmuldq/pmuludq patterns.
The IR for pmuldq/pmuludq intrinsics uses a sext_inreg/zext_inreg
pattern on the inputs. Ideally we pattern match these away during
isel. It is possible for LICM or other middle end optimizations
to separate the extend from the mul. This prevents SelectionDAG
from removing it or depending on how the extend is lowered, we
may not be able to generate an AssertSExt/AssertZExt in the
mul basic block. This will prevent pmuldq/pmuludq from being
formed at all.
This patch teaches shouldSinkOperands to recognize this so
that CodeGenPrepare will clone the extend into the same basic
block as the mul.
Fixes PR51371.
Differential Revision: https://reviews.llvm.org/D107689
Craig Topper [Sat, 7 Aug 2021 15:39:54 +0000 (08:39 -0700)]
[X86] Add test cases for pr51371. NFC
Kazu Hirata [Sat, 7 Aug 2021 14:37:54 +0000 (07:37 -0700)]
[IR] Remove unused declaration InitializeTypeMap (NFC)
The corresponding function definition was removed on Apr 23, 2016 in
commit
a59d3e5af889662139b8b08f2175f12567491441.
Roman Lebedev [Sat, 7 Aug 2021 12:59:21 +0000 (15:59 +0300)]
[NFC][InstCombine] `vector_reduce_xor(?ext(<n x i1>))` --> `?ext(vector_reduce_add(<n x i1>))`
Instead of expanding it ourselves,
we can just forward to `?ext(vector_reduce_add(<n x i1>))`, as per alive2:
https://alive2.llvm.org/ce/z/ymz7zE (self)
https://alive2.llvm.org/ce/z/eKu2v2 (skipped zext)
https://alive2.llvm.org/ce/z/c3BXgc (skipped sext)
Roman Lebedev [Sat, 7 Aug 2021 12:45:11 +0000 (15:45 +0300)]
[NFC][InstCombine] Simplify emitted IR for `vector_reduce_xor(?ext(<n x i1>))`
Now that we canonicalize low bit splatting to the form we were emitting
here ourselves, emit simpler IR that will be canonicalized later.
See
1e801439be26569c9ede6fd309a645b00adb656c for proofs:
https://alive2.llvm.org/ce/z/MjCm5W (self)
https://alive2.llvm.org/ce/z/kgqF4M (skipped zext)
https://alive2.llvm.org/ce/z/pgy3HP (skipped sext)
Roman Lebedev [Sat, 7 Aug 2021 12:20:35 +0000 (15:20 +0300)]
[InstCombine] Prefer `-(x & 1)` as the low bit splatting pattern (PR51305)
Both patterns are equivalent (https://alive2.llvm.org/ce/z/jfCViF),
so we should have a preference. It seems like mask+negation is better
than two shifts.
Roman Lebedev [Sat, 7 Aug 2021 11:40:10 +0000 (14:40 +0300)]
[NFC][InstCombine] Add tests for low bit splatting pattern (PR51305)
Roman Lebedev [Sat, 7 Aug 2021 12:25:10 +0000 (15:25 +0300)]
[NFC][InstCombine] Autogenerate checklines in a few tests being affected by an upcoming change
Christudasan Devadasan [Fri, 23 Jul 2021 12:28:55 +0000 (08:28 -0400)]
SROA: Enhance speculateSelectInstLoads
Allow the folding even if there is an
intervening bitcast.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D106667
Florian Hahn [Sat, 7 Aug 2021 13:02:24 +0000 (14:02 +0100)]
[VPlan] Iterate over phi recipes to detect reductions to fix.
After refactoring the phi recipes, we can now iterate over all header
phis in a VPlan to detect reductions when it comes to fixing them up
when tail folding.
This reduces the coupling with the cost model & legal by using the
information directly available in VPlan. It also removes a call to
getOrAddVPValue, which references the original IR value which may
become outdated after VPlan transformations.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D100102
Andrea Di Biagio [Sat, 7 Aug 2021 10:39:33 +0000 (11:39 +0100)]
[MCA] Simplify the rounding logic used in TimelineView::printWaitTimeEntry.
This is related to PR51392.
Before this patch, the timeline view was rounding doubles to the first decimal,
using a logic similar to this:
```
double AverageTime = (double)Input / CumulativeExecutions;
double Result = floor((AverageTime * 10) + 0.5) / 10
```
Here, Input and CumulativeExecutions are both unsigned integers.
The last operation is what effectively performs the rounding of AverageTime.
PR51392 has been raised because - under specific -m32 configurations of GCC -
one of the timeline tests reports slighlty different values (due to a different
rounding choice).
This patch tries to minimise the propagation of floating-point error by
hoisting the multiply by 10, so that it is performed on the unsigned.
```
double AverageTime = (double)(Input * 10) / CumulativeExecutions;
floor(AverageTime + 0.5) / 10
```
So we are trading a floating point multiply for a integer multiply (which can be
expanded using a simple MUL or using an `ADD + LEA` sequence). This decrease in
floating point operations executed should also help with decreasing the error in
the computation..
Strictly speaking, that computation will always be potentially subject to error
(depending on what values are passed in input). However, this patch should
improve the situation and make bug like PR51392 less frequent.
Simon Atanasyan [Sat, 7 Aug 2021 10:29:59 +0000 (13:29 +0300)]
[LLD] Add required `ppc` target to the test cases. NFC
Simon Atanasyan [Fri, 6 Aug 2021 10:29:47 +0000 (13:29 +0300)]
[LLD] Support compressed input sections on big-endian targets
This patch enables compressed input sections on big-endian targets by
checking the target endianness and selecting an appropriate `Chdr`
structure.
Fixes PR51369
Differential Revision: https://reviews.llvm.org/D107635
Amara Emerson [Sat, 7 Aug 2021 08:37:24 +0000 (01:37 -0700)]
[GlobalISel] Fix a combine causing DBG_VALUE with dangling vregs.
We should use MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval()
instead of eraseFromParent().
We should probably use that in other places too but fix this issue which
affects clang bootstrap builds for now.
Roger Ferrer Ibanez [Fri, 6 Aug 2021 20:22:23 +0000 (20:22 +0000)]
[OpenMP] Fix accidental reuse of VLA size
We were using an OpaqueValueExpr allocated on the stack to store
the size of a VLA. Because the VLASizeMap in CodegenFunction
uses the address of the expression to avoid recomputing VLAs,
we were accidentally reusing an earlier llvm::Value. This led to
invalid LLVM IR.
This is a temporary solution until VLASizeMap can be pushed and popped
based on the context.
Differential Revision: https://reviews.llvm.org/D107666
Nemanja Ivanovic [Sat, 7 Aug 2021 03:03:44 +0000 (22:03 -0500)]
Fix PPC buildbot break caused by
4c4093e6e39fe6601f9c95a95a6bc242ef648cd5
This commit adds the isnan intrinsic and provides a default expansion
for it in the SDAG. However, it makes the assumption that types
it operates on are IEEE-compliant types. This is not always the case.
An example of that is PPC "double double" which has a representation
that
- Does not need to conform to IEEE requirements for isnan as it is
not an IEEE-compliant type
- Does not have a representation that allows for straightforward
reinterpreting as an integer and use of integer operations
The result was that this commit broke __builtin_isnan for ppc_fp128
making many valid numeric values report a NaN.
This patch simply changes the expansion to always expand to unordered
comparison (regardless of whether FP exceptions are tracked). This
is inline with previous semantics.
Matt Jacobson [Sat, 7 Aug 2021 02:23:14 +0000 (10:23 +0800)]
[AVR][clang] Add '$SYSROOT/avr' to possible avr-libc locations
Reviewed by: benshi001
Differential Revision: https://reviews.llvm.org/D107672
Roland McGrath [Fri, 6 Aug 2021 02:51:48 +0000 (19:51 -0700)]
[profile][Fuchsia] Add missing system header #include
The _zx_vmar_root_self function is not a system call but
a libc function declared in a separate header.
Reviewed By: gulfem
Differential Revision: https://reviews.llvm.org/D107616
Jonas Devlieghere [Sat, 7 Aug 2021 00:24:47 +0000 (17:24 -0700)]
Re-land "[lldb] Upstream support for Foundation constant classes"
Upstream support for NSConstantArray, NSConstantIntegerNumber,
NSConstant{Float,Double}Number and NSConstantDictionary.
We would've upstreamed this earlier but testing it requires
-fno-constant-nsnumber-literals, -fno-constant-nsarray-literals and
-fno-constant-nsdictionary-literals which haven't been upstreamed yet.
As a temporary workaround use the system compiler (xcrun clang) for the
constant variant of the tests.
I'm just upstreaming this. The patch and the tests were all authored by
Fred Riss.
Differential revision: https://reviews.llvm.org/D107660
Sterling Augustine [Fri, 6 Aug 2021 23:50:00 +0000 (16:50 -0700)]
Revert "[lldb] Upstream support for Foundation constant classes"
This reverts commit
34d78b6a6755946e547afc47d38b59b6a2854457.
This breaks build bots witha missing file:
/home/worker/2.0.1/lldb-x86_64-debian/llvm-project/lldb/source/Plugins/Language/ObjC/Cocoa.cpp:10:10: fatal error: 'objc/runtime.h' file not found
Jim Ingham [Fri, 6 Aug 2021 23:36:25 +0000 (16:36 -0700)]
Use LC_DYLD_EXPORTS_TRIE to locate the dyld trie structure if present
The pointer to the dyld trie data structure which lldb needs to parse to get
"trampoline kinds" on Darwin used to be a field in the LC_DYLD_INFO load command. A
new load command was added recently dedicated to this purpose: LC_DYLD_EXPORTS_TRIE.
The format of the trie did not change, however. So all we have to do is use the new
command if present. The commands are supposed to be mutually exclusive, so I added
an lldb_assert to warn if they are not.
Differential Revision: https://reviews.llvm.org/D107673
Max Kudryavtsev [Fri, 6 Aug 2021 23:29:21 +0000 (16:29 -0700)]
[MLIR][STD] Add safe scalar constant propagation for FPTruncOp
Perform scalar constant propagation for FPTruncOp only if the resulting value can be represented without precision loss or rounding.
Example:
%cst = constant 1.000000e+00 : f32
%0 = fptrunc %cst : f32 to bf16
-->
%cst = constant 1.000000e+00 : bf16
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D107518
Dave Airlie [Fri, 6 Aug 2021 23:25:00 +0000 (09:25 +1000)]
opencl-c.h: add 3.0 optional extension support for a few more bits
These 3 are fairly simple, pipes, workgroups and subgroups.
Reviewed By: Anastasia
Differential Revision: https://reviews.llvm.org/D105858
Steffen Larsen [Fri, 6 Aug 2021 22:10:37 +0000 (15:10 -0700)]
[NVPTX] Add NVPTX intrinsics for CUDA PTX 6.5 ldmatrix instructions
Adds NVPTX intrinsics for the CUDA PTX `ldmatrix.sync.aligned` instructions added in PTX 6.5.
PTX ISA description of `ldmatrix.sync.aligned`: https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-ldmatrix
Authored-by: Steffen Larsen <steffen.larsen@codeplay.com>
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D107046
Jonas Devlieghere [Fri, 6 Aug 2021 20:06:46 +0000 (13:06 -0700)]
[lldb] Upstream support for Foundation constant classes
Upstream support for NSConstantArray, NSConstantIntegerNumber,
NSConstant{Float,Double}Number and NSConstantDictionary.
We would've upstreamed this earlier but testing it requires
-fno-constant-nsnumber-literals, -fno-constant-nsarray-literals and
-fno-constant-nsdictionary-literals which haven't been upstreamed yet.
As a temporary workaround use the system compiler (xcrun clang) for the
constant variant of the tests.
I'm just upstreaming this. The patch and the tests were all authored by
Fred Riss.
Differential revision: https://reviews.llvm.org/D107660
Stanislav Mekhanoshin [Fri, 6 Aug 2021 23:00:35 +0000 (16:00 -0700)]
[AMDGPU] Added test for MachineLICM reg pressure. NFC.
The test shows excessive register pressure after the MachineLICM.
This is a pre-commit for the patch fixing it.
Differential Revision:
Jim Ingham [Wed, 28 Jul 2021 23:59:55 +0000 (16:59 -0700)]
Add a "current" token to the ThreadID option to break set/modify.
This provides a convenient way to limit a breakpoint
to the current thread when setting it from the command line w/o
having to figure out what the current thread is.
Differential Revision: https://reviews.llvm.org/D107015
Paul Robinson [Fri, 6 Aug 2021 22:01:35 +0000 (15:01 -0700)]
Revert "[lit] Have REQUIRES support the target triple"
This reverts commit
100a7b6197863d4d5ebc97761d7e98063e164e26.
Speculating that this is the reason behind a sanitizer failure:
https://lab.llvm.org/buildbot/#/builders/37/builds/5945
Zequan Wu [Fri, 6 Aug 2021 21:42:55 +0000 (14:42 -0700)]
Joseph Huber [Fri, 6 Aug 2021 14:53:51 +0000 (10:53 -0400)]
[OpenMP]Fix PR51349: Remove AlwaysInline for if regions.
After D94315 we add the `NoInline` attribute to the outlined function to handle
data environments in the OpenMP if clause. This conflicted with the `AlwaysInline`
attribute added to the outlined function. for better performance in D106799.
The data environments should ideally not require NoInline, but for now this
fixes PR51349.
Reviewed By: mikerice
Differential Revision: https://reviews.llvm.org/D107649
Sanjay Patel [Fri, 6 Aug 2021 20:36:32 +0000 (16:36 -0400)]
[InstCombine] reduce vector casting before icmp
There may be some generalizations (see test comments) of these patterns,
but this should handle the cases motivated by:
https://llvm.org/PR51315
https://llvm.org/PR51259
The backend may want to transform differently, but at least for
the x86 examples that I looked at, there does not appear to be
any significant perf diff either way.
Sanjay Patel [Fri, 6 Aug 2021 19:58:19 +0000 (15:58 -0400)]
[InstCombine] add tests for icmp of casted vector; NFC
https://llvm.org/PR51315
Michael Liao [Wed, 4 Aug 2021 20:22:51 +0000 (16:22 -0400)]
[amdgpu] Revise the conversion from i64 to f32.
- Replace 'cmp+sel' with 'umin' if possible.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D107507
Zequan Wu [Thu, 5 Aug 2021 19:08:04 +0000 (12:08 -0700)]
[Profile][NFC] Clean up initializeProfileForContinuousMode
Merge two versions of `initializeProfileForContinuousMode` function into one.
Differential Revision: https://reviews.llvm.org/D107591