Timur Kristóf [Mon, 15 Aug 2022 11:22:15 +0000 (13:22 +0200)]
ac/nir/tess: Remove jump from tess factor writes.
When the output patch size <= 32 we can be sure regardless
of wave size that each wave will take this branch, therefore
the jump can be removed.
Fossil DB stats on Navi 21:
Totals from 1385 (1.03% of 134906) affected shaders:
CodeSize: 2664436 -> 2658896 (-0.21%)
Instrs: 488618 -> 487233 (-0.28%)
Latency: 2290157 -> 2289199 (-0.04%)
InvThroughput: 898658 -> 898364 (-0.03%)
Branches: 6554 -> 5169 (-21.13%)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
Timur Kristóf [Sat, 6 Aug 2022 05:37:47 +0000 (07:37 +0200)]
ac/nir/ngg: Remove jumps from some branches where we know LGKMCNT==0.
The GPU can skip LDS instructions when LGKMCNT==0, and for these
branches this should be always faster than a jump.
Fossil DB stats on Navi 21:
Totals from 60918 (45.16% of 134906) affected shaders:
CodeSize:
158624792 ->
157893776 (-0.46%)
Instrs:
30234254 ->
30051500 (-0.60%)
Latency:
139521675 ->
139434597 (-0.06%); split: -0.06%, +0.00%
InvThroughput:
21184146 ->
21183653 (-0.00%); split: -0.00%, +0.00%
Branches: 1115134 -> 932380 (-16.39%)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
Timur Kristóf [Wed, 23 Feb 2022 09:13:54 +0000 (10:13 +0100)]
aco: Allow explicitly removing jumps on GFX10+ when beneficial.
"Removing jumps" in ACO means skipping the jump instruction
at the beginning of a divergent branch (but still modify exec).
ACO already supports implicitly removing jumps when it decides
that executing a branch with empty exec mask is more beneficial
than a jump.
This commit adds the possibility to use this explicitly
through nir_selection_control. ACO will respect this
setting and remove the branch instructions when this is specified,
unless it decides that this would cause bugs (eg. exp instruction).
There are two cases that benefit from the new change:
1. When the application requests to "flatten" a branch (ie.
remove control flow), we now respect that.
2. When the compiler stack determines that a divergent branch
is always taken.
v2 by Georg Lehmann: fixed applying sel_ctrl to else blocks
Fossil DB stats on Navi 21:
Totals from 13 (0.01% of 134906) affected shaders:
CodeSize: 136616 -> 136496 (-0.09%)
Instrs: 26196 -> 26166 (-0.11%)
Latency: 417928 -> 417889 (-0.01%)
Branches: 1241 -> 1211 (-2.42%)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
Georg Lehmann [Mon, 10 Oct 2022 08:44:35 +0000 (10:44 +0200)]
nir: Print nir_selection_control_divergent_always_taken.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
Timur Kristóf [Wed, 7 Sep 2022 11:58:30 +0000 (13:58 +0200)]
nir: Add selection control enum for always taken divergent branches.
The new enum is called nir_selection_control_divergent_always_taken,
and it's almost the same as nir_selection_control_flatten.
The main difference between the two is that "flatten" represents
a choice made by the application but "divergent_always_taken" may
be applied by the compiler stack when it thinks this is beneficial.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
Timur Kristóf [Wed, 7 Sep 2022 11:58:00 +0000 (13:58 +0200)]
nir: Document the flatten/dont_flatten selection control options.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
Sil Vilerino [Mon, 3 Oct 2022 15:42:54 +0000 (11:42 -0400)]
d3d12: Fix get_index7bits - Reuse previously freed indices
Some apps do not always reuse resources contiguously and we need to search for a previous free index/slot
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18944>
Sil Vilerino [Fri, 30 Sep 2022 20:15:05 +0000 (16:15 -0400)]
d3d12: Add VP9 Decode support
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18944>
Sil Vilerino [Fri, 30 Sep 2022 20:14:52 +0000 (16:14 -0400)]
frontends/va: Add VP9 decode ref/mode_deltas information
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18944>
Sil Vilerino [Fri, 30 Sep 2022 19:45:23 +0000 (15:45 -0400)]
frontends/va: Add VP9 decode multi slice information
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18944>
Ruijing Dong [Sat, 8 Oct 2022 02:03:20 +0000 (22:03 -0400)]
frontends/va: fix av1 decoding image distortion issue
problem:
when not using qmatrix, the qm_y, qm_u and qm_v value is set to 0,
which signals av1 decoder to use qmatix and causes confussion.
solution:
when not using qmatrix, set these values to 0xf.
fixed: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5632
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19002>
Rohan Garg [Tue, 6 Sep 2022 15:31:51 +0000 (17:31 +0200)]
anv, iris: Disable pre fetching the binding table entries on DG2
On DG2 the HW will fetch the binding entries into the cache
for every single thread when a compute walker is dispatched,
wiping out the advantages of the cache prefetch.
The spec also advises to not do a cache prefetch when we have more than
31 binding table entries, but most real world applications will never
hit that limit.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18498>
Samuel Pitoiset [Thu, 22 Sep 2022 13:35:24 +0000 (15:35 +0200)]
radv: fix and rework shaders upload with GPL
For fast-linking, we really want to upload the binaries directly in
a library to avoid creating and uploading at pipeline creation time.
To achieve that, add a radeon_winsys_bo pointer to radv_shader in
order to indicate that a shader is already uploaded. When a lib is
imported, the pipeline slab BO is also incremented to make sure it's
not freed when the lib is destroyed.
This also allows to free binaries right after they are uploaded.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18860>
Mike Blumenkrantz [Fri, 30 Sep 2022 04:51:54 +0000 (00:51 -0400)]
vk/graphics_state: don't set default sample locations if rast samples is dynamic
dynamic rasterization samples got added late, and I forgot to update this
Fixes:
1deb83fb86d ("vulkan: Add more dynamic multisample states")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18896>
Timothy Arceri [Tue, 11 Oct 2022 02:42:25 +0000 (13:42 +1100)]
radv: add radv_zero_vram workarounds for OpenGL games
These are needed if the games are running on radv via zink.
Tested with "7 Days to Die"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6449
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19031>
Kenneth Graunke [Mon, 10 Oct 2022 21:58:40 +0000 (14:58 -0700)]
iris: Add miplevel parameters to iris_resource_texture_aux_usage
Sometimes we only access a subset of a texture's miplevels, for example
when peforming GenerateMipmaps(). We want to be able to look for the
aux state being ISL_AUX_STATE_PASS_THROUGH for only the relevant
miplevels, rather than all of them, when deciding whether to bypass aux.
Avoids another occurrence of issues with reading via aux while in
passthrough state (see issue #6558), fixing misrendering in Chrome
and Electron apps while resizing the window to be smaller (#7272).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7272
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19028>
Tapani Pälli [Mon, 10 Oct 2022 10:18:01 +0000 (13:18 +0300)]
mesa: mark debug variables with ASSERTED
To clean up compilation warnings about unused variables
when asserts are disabled.
v2: UNUSED -> ASSERTED (Eric Engestrom)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
Tapani Pälli [Mon, 10 Oct 2022 10:17:37 +0000 (13:17 +0300)]
anv: mark debug variables with ASSERTED
To clean up compilation warnings about unused variables
when asserts are disabled.
v2: UNUSED -> ASSERTED (Eric Engestrom)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
Tapani Pälli [Mon, 10 Oct 2022 10:16:44 +0000 (13:16 +0300)]
intel/fs: mark debug variables with ASSERTED
To clean up compilation warnings about unused variables
when asserts are disabled.
v2: UNUSED -> ASSERTED (Eric Engestrom)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
Bas Nieuwenhuizen [Sat, 24 Sep 2022 18:56:38 +0000 (20:56 +0200)]
radv: Properly annotate all the invalid node usage.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Bas Nieuwenhuizen [Sat, 24 Sep 2022 12:56:06 +0000 (14:56 +0200)]
radv: Add traversal backtracking with a short stack.
So we can now work with arbitrarily deep BVHs.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Bas Nieuwenhuizen [Sat, 24 Sep 2022 12:24:13 +0000 (14:24 +0200)]
radv: Split global & local bvh node variable.
Need the local id later for follow up work.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Bas Nieuwenhuizen [Sat, 1 Oct 2022 13:12:13 +0000 (15:12 +0200)]
radv: Only emit parents from parents that actually end up in the tree.
Otherwise the wrong parent link might be set.
This kinda relies on waves being launched in order which tends to
be the case on AMD. To avoid the busy-wait loop waiting on stuff
from the same subgroup we do the actual processing in the body of
the loop. This can have performance implications but mostly in the
case we'd otherwise deadlock, so meh.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Bas Nieuwenhuizen [Wed, 21 Sep 2022 19:53:57 +0000 (21:53 +0200)]
radv: Generate parent links in BVH.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Bas Nieuwenhuizen [Wed, 21 Sep 2022 19:05:46 +0000 (21:05 +0200)]
radv: Start the BVH after the header.
First usage of the offset field, Can put more in it in the follow
up.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Bas Nieuwenhuizen [Wed, 21 Sep 2022 14:52:21 +0000 (16:52 +0200)]
radv: Simplify buffer copy address generation.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Bas Nieuwenhuizen [Sat, 17 Sep 2022 13:23:35 +0000 (15:23 +0200)]
radv: Add a field for the offset of the bvh in the blas.
So that we can put some metadata in front.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Bas Nieuwenhuizen [Thu, 29 Sep 2022 12:29:37 +0000 (12:29 +0000)]
radv: Clean up unused fields in BVH IR.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
Connor Abbott [Mon, 10 Oct 2022 16:11:57 +0000 (18:11 +0200)]
tu: Add compute shader instrlen workaround
It's a bit unfortunate that this doesn't match any blob workaround that
we know of, but it seems to be necessary.
Closes: #5892
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19023>
Connor Abbott [Mon, 10 Oct 2022 15:40:12 +0000 (17:40 +0200)]
freedreno: Add LABEL flush
This seems like a debug thing, but the blob also seems to use it for
workarounds where an event is required but no actual work needs to be
done. For example CP_REG_WRITE uses it for various workarounds.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19023>
Danylo Piliaiev [Fri, 7 Oct 2022 14:52:41 +0000 (16:52 +0200)]
tu: Reset whether there is DS resolve for dynamic subpass
Otherwise we use old invalid value.
Relevant CTS tests:
dEQP-VK.pipeline.monolithic.multisample.misc.dynamic_rendering.multi_renderpass.r8g8b8a8_unorm_r16g16b16a16_sfloat_r16g16b16a16_*
Fixes:
ed125e6cca188275631641784fcf3ddcbcfef193
("tu: Initial support for dynamic rendering")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18999>
Jason Ekstrand [Wed, 6 Apr 2022 23:01:22 +0000 (18:01 -0500)]
iris: Set SamplerCount in shader packets
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
Karol Herbst [Tue, 10 May 2022 22:01:36 +0000 (00:01 +0200)]
iris: bump IRIS_MAX_GLOBAL_BINDINGS to 128
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
Karol Herbst [Thu, 22 Sep 2022 11:16:18 +0000 (13:16 +0200)]
iris: speed up walking global bindings
we can break on the first NULL resource as frontends always bind
contingous lists of resources without any gaps.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
Karol Herbst [Thu, 12 May 2022 20:23:30 +0000 (22:23 +0200)]
iris: use images_used instead of num_images
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
Lionel Landwerlin [Sun, 9 Oct 2022 14:39:44 +0000 (17:39 +0300)]
anv: add grl build dependency on entrypoints
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7446
Fixes:
f3ddfd81b4de ("anv: Build BVHs on the GPU with GRL")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19007>
Danylo Piliaiev [Fri, 7 Oct 2022 09:46:55 +0000 (11:46 +0200)]
tu: Lazily init VSC to fix dynamic rendering in secondary cmdbufs
Dynamic renderpasses need vsc_prim_strm_pitch, vsc_draw_strm_pitch
values, and a correct BO. The easiest way to solve this is to
lazily init VSC when it is needed, and not at every cmdbuf
initialization.
Fixes CTS tests (when running with TU_DEBUG=gmem,forcebin):
dEQP-VK.draw.dynamic_rendering.complete_secondary_cmd_buff.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18996>
Danylo Piliaiev [Mon, 10 Oct 2022 14:18:13 +0000 (16:18 +0200)]
tu: Do not DCE unused output vars used for transform feedback
Fixes CTS tests:
dEQP-VK.transform_feedback.simple.multiquery_omit_write_1
dEQP-VK.transform_feedback.simple.multiquery_omit_write_3
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19020>
Rob Clark [Sat, 1 Oct 2022 16:02:45 +0000 (09:02 -0700)]
gallium/u_threaded: Add optional call-id tracing
If enabled, use a scoped trace to see where calls happen on frontend vs
where they are pushed down to driver. This is much lighter weight than
printf based tracing, but would still be an extra few instructions even
if perfetto tracing isn't active, so it is not enabled by default.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
Rob Clark [Sat, 1 Oct 2022 15:37:45 +0000 (08:37 -0700)]
gallium/u_threaded: Add some atrace/perfetto
Use the MESA_TRACE_BEGIN/END() macros which will generate perfetto
traces (if perfetto is enabled) otherwise atrace (if android build), in
either case creating track events which will show up on the frontend
thread in a perfetto trace, giving visibility into where syncs happen.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
Thomas Debesse [Sat, 8 Oct 2022 06:43:10 +0000 (08:43 +0200)]
nv50: call nir_lower_flrp
Fix #7432: unknown nir_op flrp assertion
This copy-pastes src/gallium/drivers/radeonsi/si_shader_nir.c
The lower_flrp16 value differs given chipset >= NVISA_GV100_CHIPSET.
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19003>
pal1000 [Wed, 17 Aug 2022 19:29:21 +0000 (22:29 +0300)]
clc/clover: Link clang statically when shared-llvm is disabled
Makes things easier to handle when aiming for a static build
Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18117>
Erik Faye-Lund [Wed, 5 Oct 2022 14:20:27 +0000 (16:20 +0200)]
gallium: normalized_coords -> unnormalized_coords
A lot of code zero-initializes pipe_sampler_state, and sets the states
the non-zero fields manually. This means that normalized_coords is the
"default" setting.
However, setting normalized_coords to true isn't allways allowed, and
we'd need to check PIPE_CAP_TEXRECT first. So it's not really the ideal
default here. There's recently been found quite a bit of bugs in this
area, where the state-tracker didn't properly lower texrects.
Let's switch this around to avoid more bugs like this in the future.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18971>
Filip Gawin [Wed, 5 Oct 2022 22:59:50 +0000 (00:59 +0200)]
r300: don't use smooth line if not requested
Makes these tests passing:
dEQP-GLES2.functional.rasterization.interpolation.basic.line_loop_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.line_loop,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.line_strip,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.lines,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.lines_wide,UnexpectedPass
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18979>
Timothy Arceri [Mon, 3 Oct 2022 09:48:06 +0000 (20:48 +1100)]
util/radeonsi: enable zerovram workaround for Exanima
The issue is very intermittent and can sometimes work fine
without the workaround but turning it on seems to resolve
any issues.
Issue: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6449
Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18935>
Timothy Arceri [Mon, 3 Oct 2022 09:46:15 +0000 (20:46 +1100)]
util/conf: enable init to zero workaround for Exanima
Fixes rendering issues on llvmpipe.
Issue: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6449
Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18935>
Lionel Landwerlin [Sun, 2 Oct 2022 21:36:50 +0000 (00:36 +0300)]
pps: enable track_event in intel.cfg
Take the opportunity to prune some ftraces that are not that useful
and fill the buffer pretty fast.
Record time is bumped to 1.2s
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18930>
Konstantin Seurer [Wed, 5 Oct 2022 13:34:00 +0000 (15:34 +0200)]
radv/rra: Transcode nodes recursively
Instead of relying on a certain BVH layout, this patch traverses the BVH
from the root node which gets rid of any layout requirements.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18967>
David Heidelberg [Thu, 29 Sep 2022 14:12:41 +0000 (16:12 +0200)]
ci: uprev DXVK to 1.10.3
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18888>
Rob Clark [Sat, 1 Oct 2022 15:21:28 +0000 (08:21 -0700)]
isaspec: Fix out of date comment
Assembler support has existed for a long time.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
Rob Clark [Sat, 1 Oct 2022 15:22:45 +0000 (08:22 -0700)]
freedreno: Add perf-debug trace
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
Rob Clark [Fri, 30 Sep 2022 22:26:38 +0000 (15:26 -0700)]
freedreno/drm: Don't call kernel with no ops
When called with FD_BO_PREP_FLUSH as the only op bit set, the intention
is to only sync with the submit-queue.. we shouldn't be calling down to
the kernel (where op==0 gets interpreted as MSM_PREP_READ).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
Rob Clark [Tue, 27 Sep 2022 16:52:18 +0000 (09:52 -0700)]
freedreno: Use TC cpu-storage to shadow buffers
We still use the shadow path for non-buffer updates, where TC isn't
playing any tricks. But for correctness we need to use the cpu-
storage approach, instead of buffer shadowing, otherwise we can race
with the frontend thread for PIPE_MAP_UNSYNCHRONIZED access.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7262
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
Thomas Debesse [Sun, 2 Oct 2022 20:55:30 +0000 (22:55 +0200)]
r600: info.stage MESA_SHADER_KERNEL as MESA_SHADER_COMPUTE
Fixes:
src/gallium/drivers/r600/sfn/sfn_nir.cpp:832: int r600_shader_from_nir(r600_context*, r600_pipe_shader*, r600_shader_key*): Assertion `shader' failed.
karolherbst said:
> long term r600 should implement PIPE_CAP_SHAREABLE_SHADERS
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18963>
Thomas Debesse [Sun, 2 Oct 2022 18:12:42 +0000 (20:12 +0200)]
r600: set clear_buffer = u_default_clear_buffer
Fixes:
thread '<unnamed>' panicked at 'Context missing features. This should never happen!', ../src/gallium/frontends/rusticl/mesa/pipe/context.rs:44:13
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18962>
Konstantin Seurer [Sun, 2 Oct 2022 11:16:51 +0000 (13:16 +0200)]
radv: Remove main_loop_case_visited
Totals from 7 (14.00% of 50) affected shaders:
CodeSize: 219168 -> 216732 (-1.11%)
Instrs: 40211 -> 40040 (-0.43%)
Latency: 963520 -> 961498 (-0.21%)
InvThroughput: 221435 -> 220974 (-0.21%)
Copies: 5634 -> 5562 (-1.28%)
PreSGPRs: 387 -> 380 (-1.81%)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18929>
Konstantin Seurer [Mon, 3 Oct 2022 12:52:10 +0000 (14:52 +0200)]
radv: Use cache_uuid for accel struct compatibility
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18938>
Dave Airlie [Fri, 26 Aug 2022 05:51:32 +0000 (15:51 +1000)]
gallivm/sample: refactor multisample offset calcs code.
Just consoldiate this
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18264>
Dave Airlie [Fri, 26 Aug 2022 05:38:36 +0000 (15:38 +1000)]
gallivm/nir: drop some unused struct members.
These weren't used in the nir paths.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18264>
Dave Airlie [Fri, 26 Aug 2022 05:13:04 +0000 (15:13 +1000)]
gallivm/sample: move some first_level/last_level calcs out
There were a fair few instances of first/level dynamic state getting,
these could be moved up a level or two and made more common.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18264>
Daniel Stone [Fri, 7 Oct 2022 12:34:42 +0000 (07:34 -0500)]
CI: Re-enable Collabora devices
Friday maintenance is done.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18998>
Erik Faye-Lund [Wed, 5 Oct 2022 16:19:07 +0000 (18:19 +0200)]
gallium/u_threaded_context: remove stale comment
We're now using PIPE_SHADER_MAX_SAMPLER_VIEWS, so this advice is
outdated.
Fixes:
620c5e9dd05 ("gallium/u_threaded_context: Use PIPE_MAX_SHADER_SAMPLER_VIEWS for sampler_buffers")
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18973>
Sathishkumar S [Mon, 26 Sep 2022 13:30:43 +0000 (19:00 +0530)]
frontends/va: reallocate surface for yuv400/yuv444 picture
reallocate the surface appropriately based on the mjpeg sampling factor
v2:
use macros for mjpeg sampling factors (Ruijing Dong)
indentation fix (Thong Thai)
v3:
add comments to mention workaround of reallocation (Boyuan Zhang)
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
James Zhu [Mon, 26 Sep 2022 04:36:13 +0000 (10:06 +0530)]
radeonsi/vcn: enable jpeg decode of yuv444 and yuv400
v2: set third plane offset only for 3 plane formats (Boyuan Zhang)
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
Sathishkumar S [Mon, 26 Sep 2022 04:30:24 +0000 (10:00 +0530)]
frontends/va: support yuv 400/444 rt_formats in vaconfig
check if vaprofile supports decode of yuv400 and yuv444 formats
and enable the corresponding rt_formats in vaconfig.
v2: use config->entrypoint as param instead of BITSTREAM (Sil Vilerino)
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
James Zhu [Mon, 26 Sep 2022 04:21:29 +0000 (09:51 +0530)]
frontends/va: add support for yuv400 and yuv444
v2: indentation fixes (Saleem)
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
James Zhu [Thu, 15 Sep 2022 12:24:52 +0000 (17:54 +0530)]
util/format: add util format y8_400_unorm
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
Rajnesh Kanwal [Thu, 29 Sep 2022 15:31:32 +0000 (16:31 +0100)]
pvr: Add vulkan shader factory headers for Query and clear APIs.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
Rajnesh Kanwal [Wed, 28 Sep 2022 18:11:21 +0000 (19:11 +0100)]
pvr: Split pds compute shader create and upload code for reuse.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
Rajnesh Kanwal [Wed, 28 Sep 2022 18:05:16 +0000 (19:05 +0100)]
pvr: Remove double error reporting.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
Rajnesh Kanwal [Wed, 28 Sep 2022 17:52:27 +0000 (18:52 +0100)]
pvr: Fix allocation size passed in pvr_cmd_buffer_alloc_mem.
pvr_cmd_buffer_alloc_mem takes size in bytes. This change
fixes the invocations which assume it to be size in dwords.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
Rajnesh Kanwal [Wed, 28 Sep 2022 17:38:02 +0000 (18:38 +0100)]
pvr: Fix heap type of availability_buffer allocation.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
Rajnesh Kanwal [Wed, 28 Sep 2022 17:33:31 +0000 (18:33 +0100)]
pvr: Update buffer type macro names for consistency.
Also changing struct pvr_descriptor_program_input to
struct pvr_pds_descriptor_program_input for consistency with
other similar structs defined in pvr_pds.h.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
Simon Zeni [Wed, 5 Oct 2022 10:33:37 +0000 (06:33 -0400)]
mesa: unlock texture on error path in glEGLImageTargetTexStorageEXT
The texture mutex was not properly unlocked on error path, leading to deadlocks
Fixes:
6a3f5c65 ("mesa: simplify st_egl_image binding process for texture storage")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7422
Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18964>
Diogo Ivo [Fri, 23 Sep 2022 13:40:34 +0000 (14:40 +0100)]
nouveau: treat DRM_FORMAT_INVALID as implicit modifier
Failing to allocate resources when DRM_FORMAT_INVALID
is passed as a modifier breaks tegra. Change this behaviour
so that this modifier is instead interpreted as a don't care,
allowing for the driver to choose an appropriate modifier internally.
v2: change nouveau instead of tegra (Thierry Rieding)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6693
Fixes:
129d83cac2a ("nouveau: Use format modifiers in buffer allocation")
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18649>
Gert Wollny [Wed, 5 Oct 2022 14:48:27 +0000 (16:48 +0200)]
r600/sfn: Make sure all components are usable when lowering TF inputs
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Wed, 5 Oct 2022 13:05:40 +0000 (15:05 +0200)]
r600/sfn: Always enforce LDS operation order
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Fri, 30 Sep 2022 13:13:33 +0000 (15:13 +0200)]
r600/sfn: Unroll loops after doing some optimizations
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Fri, 30 Sep 2022 13:13:07 +0000 (15:13 +0200)]
r600/sfn: assert on use of abs modifier in op3
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Wed, 28 Sep 2022 12:52:41 +0000 (14:52 +0200)]
r600/sfn:explicitly initialize the memory pool
This reduces the overhead of checking with each allocation
whether the pool is already initialized.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Wed, 28 Sep 2022 12:52:15 +0000 (14:52 +0200)]
r600/sfn: Use the correct allocator for loop lists
This fixes a memory leak.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Wed, 28 Sep 2022 06:47:27 +0000 (08:47 +0200)]
r600/sfn: Fix typo
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Sat, 24 Sep 2022 16:42:24 +0000 (18:42 +0200)]
r600/sfn: Delete final lowered nir shader early
Since this is no longer needed we can as well free the
memory right away instead of waiting until the parent
shader is freed.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Thu, 22 Sep 2022 06:33:39 +0000 (08:33 +0200)]
r600/sfn: Add peephole optimization for kill instructions
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Wed, 5 Oct 2022 09:23:02 +0000 (11:23 +0200)]
r600/sfn: don't propagate registers into conditional test
We don't check whether the register is overwritten between the actual
conditional test and the test of the used result, so don't try to
optimize the evaluation of the conditional.
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Wed, 5 Oct 2022 09:20:00 +0000 (11:20 +0200)]
r600/sfn: Always start a new CF after a KILL instruction
Docu says:
Ensure that the KILL* instruction is the last instruction
in an ALU clause, because the remaining instructions executed
in the clause do not reflect the updated valid state after
the kill operation.
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Gert Wollny [Wed, 5 Oct 2022 07:50:02 +0000 (09:50 +0200)]
r600/sfn: Only run 64 bit ops lowering passes when really needed
If the shader doesn't do 64 bit then there is no need to run these
lowering passes.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Lucas Stach [Wed, 5 Oct 2022 13:23:33 +0000 (15:23 +0200)]
etnaviv: pass shader key by reference
The shader key has grown substancially since the introduction of the
shadow sampler lowering to the point where passing it by value when
looking for the right variant matching the current state is showing
up in the CPU profiles. Pass the key by reference to get rid of this
overhead.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18968>
Lucas Stach [Wed, 5 Oct 2022 13:14:50 +0000 (15:14 +0200)]
etnaviv: slim down etna_shader_key
The max number of exposed fragment samplers and views on any hardware is 16,
so there is no point in having arrays of 128 entries to track information
for the shadow sampler lowering in the shader key. Most of them will never
be used. Reduce the size of the arrays to what is actually necessary and add
a assert to make sure the sampler (view) limit isn't bumped without a
matching change in the shader key.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18968>
Lionel Landwerlin [Wed, 5 Oct 2022 21:34:52 +0000 (00:34 +0300)]
intel: add INTEL_DEBUG=capture-all to capture everything upon hang
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18977>
Jason Ekstrand [Thu, 29 Sep 2022 16:55:03 +0000 (11:55 -0500)]
vulkan,lavapipe: Use a tri-state enum for depth clip enable
This should make it a lot more clear how depth clip enables work.
Annoyingly, because of the way they originally worked in Vulkan 1.0,
it's dependent on the depth clamp if the state isn't set in the pipeline
and isn't declared dynamic. The enum is explicitly set up so that
drivers don't need to be aware of this change unless they already
implement VK_EXT_extended_dynamic_state3. If depth clamp/clamp are not
dynamic, depth clip will be either TRUE or FALSE which map to 1/0 so the
field can still be treated as a boolean.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18889>
Pavel Ondračka [Fri, 20 May 2022 14:38:15 +0000 (16:38 +0200)]
r300: be more careful when pair merging with presubtract
and when some argument reads both from rgb and apha. We would fail to
properly rewrite the sources in such case.
Consider the following instructions:
2: src0.xyz = const[3], src1.xyz = temp[6], srcp.xyz = (src1 - src0)
CMP temp[8].x, src0.0__, src0.1__, srcp.x__
...
5: src0.xyz = const[1], src0.w = const[1]
MAX temp[10].xy, |src0.xz_|, |src0.yw_|
We can merge them together into pair like
2: src0.xyz = const[3], src1.xyz = temp[6], src2.xyz = const[1], src2.w = const[1], srcp.xyz = (src1 - src0)
MAX temp[10].xy, |src2.xz_|, |src2.yw_|
CMP temp[8].w, src0.0, src0.1, srcp.x
However the current code fails to do so properly and we end with this:
2: src0.xyz = const[3], src0.w = const[1], src1.xyz = temp[6], src2.xyz = const[1], srcp.xyz = (src1 - src0)
MAX temp[10].xy, |src2.xz_|, |src2.yw_|
CMP temp[8].w, src0.0, src0.1, srcp.x
where the src2.w is undefined.
Just check for the the case where the arguments reads both from rgb and
alpha and bail out from the merge.
Fixes the following dEQPs:
dEQP-GLES2.functional.uniform_api.random.47
dEQP-GLES2.functional.uniform_api.value.initial.render.array_in_struct.float_vec4_both
dEQP-GLES2.functional.uniform_api.value.initial.render.basic_array.vec4_both
Only a minor change in shader-db with RV530:
total instructions in shared programs: 180847 -> 180864 (<.01%)
instructions in affected programs: 3178 -> 3195 (0.53%)
helped: 2
HURT: 16
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18991>
Daniel Stone [Thu, 6 Oct 2022 14:51:00 +0000 (09:51 -0500)]
CI: Collabora farm down for maintenance
We have major maintenance planned tomorrow, so let's just disable LAVA
until it comes back.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18987>
Christian Gmeiner [Sat, 30 Oct 2021 10:21:54 +0000 (12:21 +0200)]
ci/etnaviv: add GC7000 support
Will be used in combination with Nitrogen8M boards.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13691>
Christian Gmeiner [Fri, 5 Nov 2021 12:24:42 +0000 (13:24 +0100)]
ci/bare-metal: introduce BM_MKBOOT_PARAMS
Make it possible to provide per device mkimage.py params.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13691>
Christian Gmeiner [Sun, 31 Oct 2021 13:54:29 +0000 (14:54 +0100)]
ci: switch to mkbootimg.py
On ARM64 appending the dtb does not work with U-Boot and fastbooting
with such an image failes like:
## Booting Android Image at 0x40480000 ...
Kernel load addr 0x00000000 size 30514 KiB
Kernel command line: ip=dhcp console=ttymxc0,115200n8 root=/dev/nfs rw nfsrootdebug init=/init nfsroot=10.10.10.17:/mnt/disks/testing-nfs-root/gc7000-00,vers=3,tcp
RAM disk load addr 0x00000000 size 1 KiB
Error: header_version must be >= 2 to get dtb
Loading Kernel Image
"Error" handler, esr 0xbf000002
elr:
000000004029ce70 lr :
000000004029cf0c (reloc)
elr:
00000000be59ae70 lr :
00000000be59af0c
x0 :
0000000000100000 x1 :
0000000040580800
x2 :
0000000000010000 x3 :
00000000000020c0
x4 :
f9402063f9400463 x5 :
0000000000000000
x6 :
0000000000100000 x7 :
0000000006000000
x8 :
00000000b64f1488 x9 :
0000000000000008
x10:
00000000b651c450 x11:
00000000b653df68
x12:
0000000000000000 x13:
0000000000000200
x14:
0000000000000000 x15:
0000000000000020
x16:
00000000be55acc8 x17:
0000000000004530
x18:
00000000b64fddc0 x19:
0000000000100000
x20:
0000000040580800 x21:
0000000001ccc4af
x22:
0000000000010000 x23:
0000000000010000
x24:
0000000040480800 x25:
00000000b64f15c8
x26:
0000000000000000 x27:
0000000000000000
x28:
0000000040480800 x29:
00000000b64f1470
Code:
d65f03c0 f8636824 f8236804 91002063 (
cb030044)
Resetting CPU ...
resetting ...
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13691>
Christian Gmeiner [Sat, 30 Oct 2021 10:21:10 +0000 (12:21 +0200)]
ci: include etnaviv support in ARM64 container
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13691>
Timur Kristóf [Wed, 5 Oct 2022 14:53:10 +0000 (09:53 -0500)]
aco: Fix build error with std::max on GCC 12
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18969>
Timur Kristóf [Tue, 27 Sep 2022 16:25:49 +0000 (18:25 +0200)]
ac/nir/ngg: Fix cross-invocation indices and cull outputs.
The layout calculation accidentally thought these would be
stored in variables, but that's not the case.
Fixes:
697ea022020650cecfaeaf8c00afc5bff521e019
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18846>
Brian Paul [Tue, 4 Oct 2022 16:13:19 +0000 (10:13 -0600)]
cso: asst. clean-ups in cso_context.[ch]
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18954>
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