Jason Ekstrand [Fri, 10 Jun 2016 19:03:18 +0000 (12:03 -0700)]
i965/blorp: Add a generic ISL-based surface state emit path
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 3 Jun 2016 23:10:20 +0000 (16:10 -0700)]
i965/miptree: Add a helper for getting the aux isl_surf from a miptree
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 10 Jun 2016 18:36:00 +0000 (11:36 -0700)]
i965/miptree: Add a helper for getting the ISL clear color from a miptree
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 3 Jun 2016 21:32:12 +0000 (14:32 -0700)]
i965/miptree: Add a helper for getting an isl_surf from a miptree
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:32:18 +0000 (16:32 -0700)]
i965: Add an isl_device to the brw_context
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 8 Jun 2016 23:43:35 +0000 (16:43 -0700)]
isl/state: Add support for OffsetX/Y in surface state
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 3 Jun 2016 01:32:11 +0000 (18:32 -0700)]
isl: Add support for filling out surface states all the way back to gen4
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 8 Jun 2016 19:19:41 +0000 (12:19 -0700)]
isl: Add an ISL_DEV_IS_G4X macro
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 3 Jun 2016 01:31:47 +0000 (18:31 -0700)]
genxml: Add macros and #includes for gens 4-6
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Thu, 9 Jun 2016 01:59:29 +0000 (18:59 -0700)]
genxml: Make X/Y Offset field of SURFACE_STATE a uint
THe offset type has special implications that it's intended to be some form
of aligned memory address. These assumptions allow it to handle the case
where there is some alignment requirement on the offset and the bottom bits
are used for other things. However, the offsets in the surface state field
are really just unsigned integers.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 8 Jun 2016 18:29:15 +0000 (11:29 -0700)]
genxml: Add enough XML for gens 4, 4.5, and 5 to get SURFACE_STATE
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 13 Jul 2016 23:42:43 +0000 (16:42 -0700)]
isl/state: Divide the aux qpitch by 4
The field is in multiples of 4 like regular QPitch.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 13 Jul 2016 22:59:33 +0000 (15:59 -0700)]
isl: Fix the bs assertion in isl_tiling_get_info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 15 Jul 2016 04:11:14 +0000 (21:11 -0700)]
anv: Handle VK_WHOLE_SIZE properly for buffer views
The old calculation, which used view->offset, encorporated buffer->offset
into the size calculation where it doesn't belong. This meant that, if
buffer->offset > buffer->size, you would always get a negative size. This
fixes 170 dEQP-VK.renderpass.attachment.* Vulkan CTS tests on Haswell.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 15 Jul 2016 18:50:20 +0000 (11:50 -0700)]
anv: Add an align_down_npot_u32 helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 15 Jul 2016 01:01:29 +0000 (18:01 -0700)]
anv: Enable independentBlend on gen7
We can totally do it, we were just only setting up one BLEND_STATE and, now
that the code is unified with gen8, we should be handling it correctly.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 15 Jul 2016 01:00:50 +0000 (18:00 -0700)]
anv/pipeline: Unify blend state setup between gen7 and gen8
This fixes all 674 broken dEQP-VK.pipeline.blend Vulkan CTS tests on
Haswell.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 15 Jul 2016 00:52:07 +0000 (17:52 -0700)]
genxml: Make gen6-7 blending look more like gen8
This renames BLEND_STATE to BLEND_STATE_ENTRY and adds an new struct
BLEND_STATE which is just an array of 8 BLEND_STATE_ENTRYs. This will make
it much easier to write gen-agnostic blend handling code.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Eric Anholt [Fri, 15 Jul 2016 00:26:43 +0000 (17:26 -0700)]
vc4: Speed up glGenerateMipmaps by avoiding shadow baselevel.
To support general GL_TEXTURE_BASE_LEVEL we have to copy to a temporary
miptree. However, if a single level is being selected, we can use the
existing miptree and force all the sampling to be from that particular
level.
This avoids a ton of software fallbacks in glGenerateMipmaps(), which uses
base levels in the blit implementation in gallium. Improves "glmark2 -b
terrain" from 2 fps to 3 (perhaps some more precision would be useful?),
and cuts its CPU usage during the benchmarking from ~30% to ~10% (total
CPU time from 8.8s to 7.6s).
Eric Anholt [Fri, 15 Jul 2016 00:38:43 +0000 (17:38 -0700)]
vc4: Drop VC4_DIRTY_TEXSTATE in favor of the per-stage flags.
The compiler uses the per-stage flags already, so it didn't need this.
vc4_uniforms was using it, so just replace it with both of the stage flags
for now.
Eric Anholt [Fri, 15 Jul 2016 00:31:33 +0000 (17:31 -0700)]
vc4: Remove dead dirty_samplers field.
We use a big VC4_DIRTY_FRAGTEX/VC4_DIRTY_VERTEX on the stage, instead.
Eric Anholt [Mon, 11 Jul 2016 18:29:28 +0000 (11:29 -0700)]
vc4: Turn on control flow support in the simulator environment.
We can't merge the non-simulator support until we merge the kernel side and
get a new libdrm release.
Brian Paul [Thu, 14 Jul 2016 21:50:18 +0000 (15:50 -0600)]
mesa: handle numLevels, numSamples in _mesa_test_proxy_teximage()
If numSamples > 0, we can compute the size of the whole mipmapped texture.
That's the case for glTexStorage(GL_PROXY_TEXTURE_x).
Also, multiply the texture size by numSamples for MSAA textures.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Brian Paul [Thu, 14 Jul 2016 21:49:40 +0000 (15:49 -0600)]
mesa: add proxy texture targets in _mesa_next_mipmap_level_size()
So we can use it for computing size of proxy textures.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Brian Paul [Thu, 14 Jul 2016 20:25:19 +0000 (14:25 -0600)]
mesa: add numLevels, numSamples to Driver.TestProxyTexImage()
So that the function can work properly with glTexStorage(), where we know
how many mipmap levels there are. And so we can compute storage for MSAA
textures.
Also, remove the obsolete texture border parameter.
A subsequent patch will update _mesa_test_proxy_teximage() to use these
new parameters.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Brian Paul [Wed, 13 Jul 2016 19:52:31 +0000 (13:52 -0600)]
mesa: use _mesa_clear_texture_image() in clear_texture_fields()
This avoids a failed assert(img->_BaseFormat != -1) in
init_teximage_fields_ms() because the internalFormat argument is GL_NONE.
This was hit when using glTexStorage() to do a proxy texture test.
Fixes a failure with the updated Piglit tex3d-maxsize test.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Charmaine Lee [Tue, 12 Jul 2016 00:11:41 +0000 (17:11 -0700)]
svga: avoid ubinding render targets that have already been unbound
Fixed the remaining redundant SetRenderTargets command emission.
Tested with lightsMark2008, Heaven, mtt piglit, glretrace, conform.
Reviewed-by: Brian Paul <brianp@vmware.com>
Neha Bhende [Tue, 12 Jul 2016 06:39:06 +0000 (23:39 -0700)]
svga: dump code for GenMips.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jon Turney [Thu, 9 Jun 2016 18:21:35 +0000 (18:21 +0000)]
Disable use of weak in threads_posix.h on Cygwin
Weak doesn't work the same on PE/COFF as on ELF, they are only weak
references. Specifically, since nothing else pulls in the object which
contains pthread_mutexattr_init() (and coming from the C library, that is
the only thing that object contains), means that it ends up as 0
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Jon Turney [Tue, 7 Jun 2016 14:22:31 +0000 (14:22 +0000)]
configure: Don't require pthread-stubs on Cygwin
Commit
1f4869a2 unconditionally requires pthread-stubs. Unfortunately, the
cleverness that pthread-stubs is doesn't work with PE/COFF, and historically
Cygwin doesn't have a pthread-stubs.pc.
Don't require pthread-stubs on Cygwin.
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Yaakov Selkowitz [Sat, 11 Jun 2016 14:53:50 +0000 (14:53 +0000)]
Use correct names for dlopen()ed files on Cygwin
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>
Yaakov Selkowitz [Tue, 7 Jun 2016 18:09:07 +0000 (18:09 +0000)]
configure: Define _GNU_SOURCE for Cygwin as well
Cygwin headers are now a bit more correct in handling feature test macros,
so use _GNU_SOURCE when building for Cygwin, as well.
(Notwithstanding
f381c27c, we should probably have always been using
_GNU_SOURCE, since asprintf() is used by mesa in places)
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>
Nanley Chery [Fri, 24 Jun 2016 23:06:31 +0000 (16:06 -0700)]
Revert "isl: Don't filter tiling flags if a specific tiling bit is set"
This reverts commit
091f1da902c71ac8d3d27b325a118e2f683f1ae5 .
Although a user may specify a specfic tiling bit, ISL should still
prevent incompatible tiling/surface combinations.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Nanley Chery [Mon, 27 Jun 2016 22:24:36 +0000 (15:24 -0700)]
anv/blit2d: Copy with stencil sources when needed
In the next patch, ISL will unconditionally perform verification of a
surface's tiling and usage. Since it will require that w-tiled images
be stencil buffers, create a stencil surface to copy from a
w-tiled/stencil surface.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Fri, 24 Jun 2016 22:39:14 +0000 (15:39 -0700)]
anv/image: Fix initialization of the ISL tiling
If an internal user creates an image with Vulkan tiling VK_IMAGE_TILING_OPTIMAL
and an ISL tiling that isn't set, ISL will fail to create the image as
anv_image_create_info::isl_tiling_flags will be an invalid value.
Correct this by making anv_image_create_info::isl_tiling_flags an opt-in,
filtering bitmask, that allows the caller to specify which ISL tilings are
acceptable, but not contradictory to the Vulkan tiling.
Opt-out of filtering for vkCreateImage.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Fri, 24 Jun 2016 22:37:34 +0000 (15:37 -0700)]
isl: Fix isl_tiling_is_any_y()
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Wed, 6 Jul 2016 18:13:48 +0000 (11:13 -0700)]
anv/device: Fix max buffer range limits
Set limits that are consistent with ISL's assertions in
isl_genX(buffer_fill_state_s)() and Anvil's format-DescriptorType
mapping in anv_isl_format_for_descriptor_type().
Fixes the following new crucible tests:
* stress.limits.buffer-update.range.uniform
* stress.limits.buffer-update.range.storage
These tests are in this patch: https://patchwork.freedesktop.org/patch/98726/
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Wed, 6 Jul 2016 18:13:15 +0000 (11:13 -0700)]
isl: Fix assert on raw buffer surface state size
See inline PRM reference.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Tue, 12 Jul 2016 15:10:18 +0000 (08:10 -0700)]
anv/cmd_buffer: Simplify range member assignment
A ternary is clearer because the range member is assigned one of two values
dependant on one condition.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Mon, 11 Jul 2016 17:48:02 +0000 (10:48 -0700)]
anv/cmd_buffer: Remove unused variable
This became unused due to commit
612e35b2c65c99773b73e53d0e6fd112b1a7431f .
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Tue, 12 Jul 2016 00:33:24 +0000 (17:33 -0700)]
anv/descriptor_set: Fix binding partly undefined descriptor sets
Section 13.2.3. of the Vulkan spec requires that implementations be able to
bind sparsely-defined Descriptor Sets without any errors or exceptions.
When binding a descriptor set that contains a dynamic buffer binding/descriptor,
the driver attempts to dereference the descriptor's buffer_view field if it is
non-NULL. It currently segfaults on undefined descriptors as this field is never
zero-initialized. Zero undefined descriptors to avoid segfaulting. This
solution was suggested by Jason Ekstrand.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96850
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Brian Paul [Fri, 15 Jul 2016 13:08:13 +0000 (07:08 -0600)]
svga: handle mismatched number of samplers, sampler views
in svga_init_shader_key_common(). Since the CSO module only tracks
sampler views for fragment shaders, the number of samplers and sampler
views can be mismatched for other types of shaders. This situation
triggered an assertion in Chrome with maps.google.com
This patch adds defensive code to handle that situation.
Fixes VMware bug 1694027
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Leo Liu [Mon, 11 Jul 2016 19:27:16 +0000 (15:27 -0400)]
st/omx/enc: check uninitialized list from task release
The uninitialized list should be checked and returned.
Thank Julien for the notification and suggested fix.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Samuel Pitoiset [Tue, 12 Jul 2016 12:17:44 +0000 (14:17 +0200)]
nv50/ir: add missing string for SV_WORK_DIM
Fixes: 2aa1197 ("nouveau: Add support for SV_WORK_DIM")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Marek Olšák [Thu, 14 Jul 2016 20:07:46 +0000 (22:07 +0200)]
Revert "radeon/llvm: Use alloca instructions for larger arrays"
This reverts commit
513fccdfb68e6a71180e21827f071617c93fd09b.
Bioshock Infinite hangs with that.
Jan Vesely [Sun, 26 Jun 2016 02:06:09 +0000 (22:06 -0400)]
r600,compute: Reserve vtx 3 for kernel arguments
Using vtx 0 does not work for dynamic offsets.
v2: add explanatory comment
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Wed, 13 Jul 2016 16:51:36 +0000 (18:51 +0200)]
radeon/uvd: fail to create a decoder if RUVD_MSG_CREATE submission fails
This is the bare minimum for reporting the error to the user.
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Wed, 13 Jul 2016 16:31:16 +0000 (18:31 +0200)]
winsys/amdgpu: return an error on IB submission failures
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Wed, 13 Jul 2016 13:16:20 +0000 (15:16 +0200)]
gallium/radeon: add a return value to cs_flush
Required by our UVD code.
Reviewed-by: Christian König <christian.koenig@amd.com>
Jason Ekstrand [Wed, 13 Jul 2016 21:26:50 +0000 (14:26 -0700)]
glsl/types: Use _mesa_hash_data for hashing function types
This is way better than the stupid string approach especially since you
could overflow the string. Again, I thought I had something better at one
point but it obviously got lost.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 13 Jul 2016 21:25:11 +0000 (14:25 -0700)]
glsl/types: Fix function type comparison function
It was returning true if the function types have different lengths rather
than false. This was new with the SPIR-V to NIR pass and I thought I'd
fixed it a while ago but it may have gotten lost in rebasing somewhere.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
francians@gmail.com [Thu, 30 Jun 2016 17:16:08 +0000 (19:16 +0200)]
freedreno/a4xx: Fix sign compare warnings
Signed-off-by: Rob Clark <robdclark@gmail.com>
francians@gmail.com [Thu, 30 Jun 2016 17:16:07 +0000 (19:16 +0200)]
freedreno/a3xx: Fix sign compare warnings
Signed-off-by: Rob Clark <robdclark@gmail.com>
francians@gmail.com [Thu, 30 Jun 2016 17:16:06 +0000 (19:16 +0200)]
freedreno/a2xx: Fix sign compare warnings
Signed-off-by: Rob Clark <robdclark@gmail.com>
Boyuan Zhang [Wed, 13 Jul 2016 22:51:14 +0000 (18:51 -0400)]
radeon/vce: handle newly added parameters
Replace the previous hardcoded value with newly defined parameters
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Boyuan Zhang [Wed, 13 Jul 2016 22:51:13 +0000 (18:51 -0400)]
st/omx: assign previous values to new structure
Assign previously hardcoded values for OMX to newly defined
structure. As a result, OMX behaviour will not change at all.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Boyuan Zhang [Wed, 13 Jul 2016 22:51:11 +0000 (18:51 -0400)]
vl: add parameters for VAAPI encode
Allow to specify more parameters in the encoding interface
which previously just hardcoded in the encoder
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Christian König [Wed, 13 Jul 2016 12:54:31 +0000 (14:54 +0200)]
st/mesa: fix reference counting bug in st_vdpau
Otherwise we leak the resources created for the DMA-buf descriptors.
Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Tested-and-Reviewed by: Leo Liu <leo.liu@amd.com>
Ack-by: Tom St Denis <tom.stdenis@amd.com>
Eric Anholt [Fri, 6 May 2016 01:11:04 +0000 (18:11 -0700)]
vc4: Emit resets of the uniform stream at the starts of blocks.
If a block might be entered from multiple locations, then the uniform
stream will (probably) be at different points, and we need to make sure
that it's pointing where we expect it to be. The kernel also enforces
that any block reading a uniform resets uniforms, to prevent reading
outside of the uniform stream by using looping.
Eric Anholt [Wed, 27 Apr 2016 19:14:07 +0000 (12:14 -0700)]
vc4: Add support for scheduling of branch instructions.
For now we don't fill the delay slots, and instead just drop in NOPs.
Eric Anholt [Wed, 16 Mar 2016 00:53:36 +0000 (17:53 -0700)]
vc4: Move the QPU instructions to schedule into each block.
We'll want to schedule them individually, to handle delay slots.
Eric Anholt [Sat, 9 Jul 2016 00:06:18 +0000 (17:06 -0700)]
vc4: Disable vc4_opt_vpm in the presence of control flow.
It's a really valuable pass currently, but it will be a mess to rewrite
for control flow. For now, just disable it if we have multiple blocks
present.
Eric Anholt [Fri, 8 Jul 2016 23:23:38 +0000 (16:23 -0700)]
vc4: Convert vc4_opt_dead_code to work in the presence of control flow.
With control flow, we can't be sure that we'll see the uses of a variable
before its def as we walk backwards. Given that NIR is eliminating our
long chains of dead code, a simple solution for now seems fine.
This slightly changes the order of some optimizations, and so an opt_vpm
happens before opt_dce, causing 3 dead MOVs to be turned into dead FMAXes
in Minecraft:
instructions in affected programs: 52 -> 54 (3.85%)
Eric Anholt [Wed, 13 Jul 2016 20:37:56 +0000 (13:37 -0700)]
vc4: Update copy propagation for control flow.
Previously, we could assume that a MOV from a temp was always an available
copy, because all temps were SSA in NIR, and their non-SSA state in QIR
was just due to the fact that they were from a bcsel or pack_unorm_4x8, so
we could use the current value of the temp after that series of QIR
instructions to define it.
However, this is no longer the case with control flow. Instead, we track
a new array of MOVs defined within the block that haven't had their source
or dest killed yet, and use that primarily. We fall back to looking
through the QIR defs array to handle across-block MOVs, but now require
that copies from the SSA defs have an SSA src as well.
Samuel Iglesias Gonsálvez [Thu, 7 Jul 2016 07:19:43 +0000 (09:19 +0200)]
i965/fs: emit DIM instruction to load 64-bit immediates in HSW
v2 (Matt):
- Use brw_imm_df() as source argument of DIM instruction.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Iglesias Gonsálvez [Thu, 7 Jul 2016 11:55:32 +0000 (13:55 +0200)]
i965/eu: set DF imm value to the source of DIM
According to HSW's PRM, vol02b, the DIM instruction has the following
restriction:
"Restriction : src0 must be immediate. src0 must specify the :f (F, Float)
type encoding but is an immediate 64-bit DF (Double Float) value. dst
must have type DF."
This commit allows to upload the immediate 64-bit DF value to the source
of a DIM instruction even when it is of float type encoding.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Iglesias Gonsálvez [Thu, 7 Jul 2016 06:38:22 +0000 (08:38 +0200)]
i965: enable the emission of the DIM instruction
v2 (Matt):
- Take a DF source argument for the DIM instruction emission
in the visitors.
- Indentation.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Thu, 14 Jul 2016 03:11:30 +0000 (20:11 -0700)]
anv: Add a stub for CmdCopyQueryPoolResults on Ivy Bridge
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Timothy Arceri [Thu, 14 Jul 2016 00:27:06 +0000 (10:27 +1000)]
i965: fix compiler warnings for 32bit build
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tim Rowley [Wed, 13 Jul 2016 15:30:46 +0000 (10:30 -0500)]
Revert "gallium: Force blend color to 16-byte alignment"
This reverts commit
d8d6091a846ac2a40a011d512d6d57f6c8442e6a.
Heap allocations may be only 8-byte aligned on 32-bit system, and so having
members with 16-byte alignment (such as in the case where pipe_blend_color is
embedded in radeonsi's si_context) is undefined behavior which indeed causes
crashes when compiled with gcc -O3.
Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96835
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Acked-by: Chuck Atkins <chuck.atkins@kitware.com>
Jason Ekstrand [Fri, 3 Jun 2016 23:37:19 +0000 (16:37 -0700)]
isl/state: Add support for handling auxiliary surfaces
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Tue, 21 Jun 2016 23:16:59 +0000 (16:16 -0700)]
isl: Add an auxiliary surface usage enum
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 05:12:10 +0000 (22:12 -0700)]
isl: Add support for color control surfaces
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 02:37:27 +0000 (19:37 -0700)]
isl: Add support for multisample compression surfaces
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 02:36:33 +0000 (19:36 -0700)]
isl: Add support for HiZ surfaces
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 05:11:06 +0000 (22:11 -0700)]
isl: Kill off isl_format_layout::bs
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 05:04:18 +0000 (22:04 -0700)]
isl: Take bpb rather than bs in tiling_get_info
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 05:10:11 +0000 (22:10 -0700)]
isl: Use bpb in a few places where it's more natural than bs
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Tue, 12 Jul 2016 21:17:18 +0000 (14:17 -0700)]
isl: Use bpb for determining YUV image padding
When we initially dropped bpb in favor of bs, we accidentally didn't change
this one line properly. This brings it back to what it should be.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 04:55:34 +0000 (21:55 -0700)]
isl: Bring back isl_format_layout::bpb
A while ago we got rid of the bits-per-block because we thought we didn't
need it. We're about to introduce some very useful 1 and 2-bit formats so
we really should be able to handle them again.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 00:24:19 +0000 (17:24 -0700)]
isl: Change the physical size of a W-tile to 128x32
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 00:10:59 +0000 (17:10 -0700)]
isl: Rework the way we define tile sizes.
This is based on a very long set of discussions between Chad and myself
about how we should properly represent HiZ and CCS buffers. The end result
of that discussion was that a tiling actually has two different sizes, a
logical size in elements, and a physical size in bytes and rows. This
commit reworks ISL's pitch and size calculations to work in terms of these
two sizes.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 8 Jul 2016 22:08:20 +0000 (15:08 -0700)]
isl: Rework the way we handle surface padding
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Tue, 12 Jul 2016 21:57:30 +0000 (14:57 -0700)]
isl: Use ARRAY_PITCH_SPAN_FULL for depth/stencil surfaces on gen7
We helpfully inserted a PRM quotation about how we need to use
ARRAY_PITCH_SPAN_FULL and then set it to COMPACT. Oops...
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 8 Jul 2016 21:57:19 +0000 (14:57 -0700)]
isl: Stop multiplying height by block size
The row pitch already specifies the size of a row of elements.
Multiplying by the block height simply causes us to allocate as muc as 12
times more memory than needed for compressed textures.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 8 Jul 2016 20:59:05 +0000 (13:59 -0700)]
isl: Get rid of tiling_get_extent
It was unused
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 13 Jul 2016 18:35:29 +0000 (11:35 -0700)]
nir/spirv: Don't multiply the push constant block size by 4
I have no idea why we were multiplying by 4 before. The offsets we get
from SPIR-V are in bytes and so is nir->num_uniforms so there's no need to
do any adjustment whatsoever.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 13 Jul 2016 18:35:24 +0000 (11:35 -0700)]
anv/pipeline: Assert that the number of uniforms from NIR fits
Marek Olšák [Tue, 5 Jul 2016 00:54:43 +0000 (02:54 +0200)]
radeonsi: report accurate SGPR and VGPR spills
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 3 Jul 2016 18:00:17 +0000 (20:00 +0200)]
radeonsi: add a workaround for a compute VGPR-usage LLVM bug
v2: use abort(), describe which LLVM version is affected
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 12 Jul 2016 17:58:28 +0000 (19:58 +0200)]
radeonsi: use LLVMGetTypeKind to tell if an input is an array of descriptors
just a cleanup
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 14:25:01 +0000 (16:25 +0200)]
radeonsi: replace !tbaa with !invariant.load
no change in generated code thanks to dereferenceable(n)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 12 Jul 2016 16:52:55 +0000 (18:52 +0200)]
radeonsi: set dereferenceable attribute on descriptor arrays
This allows moving the loads arbitrarily in the Sinking pass.
26002 shaders in 14643 tests
Totals:
SGPRS: 2080160 -> 2080160 (0.00 %)
VGPRS: 798875 -> 797826 (-0.13 %)
Spilled SGPRs: 108485 -> 79165 (-27.03 %)
Spilled VGPRs: 327 -> 327 (0.00 %)
Scratch VGPRs: 1656 -> 1652 (-0.24 %) dwords per thread
Code Size:
36127192 ->
35559780 (-1.57 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 212464 -> 212672 (0.10 %)
Wait states: 0 -> 0 (0.00 %)
PERCENTAGES / App Shaders SGPRs VGPRs SpillSGPR SpillVGPR Scratch CodeSize MaxWaves Waits
(unknown) 4 . . . . . . . .
0ad 6 . . . . . . . .
alien_isolation 2938 . 0.04 % -8.53 % . . -0.71 % -0.06 % .
anholt 10 . . . . . . . .
batman_arkham_origins 589 . -0.58 % -79.54 % . . -6.72 % 0.57 % .
bioshock-infinite 1769 . -0.65 % -89.32 % . . -4.73 % 0.48 % .
borderlands2 3968 . -0.31 % -51.21 % . . -4.09 % 0.22 % .
brutal-legend 338 . -0.03 % -2.95 % . . -0.06 % . .
civilization_beyond.. 116 . . -14.17 % . . -0.88 % . .
counter_strike_glob.. 1142 . . . . . . . .
dirt-showdown 541 . -0.56 % -40.14 % . -3.45 % -1.82 % 0.35 % .
dolphin 22 . . . . . 0.16 % . .
dota2 1747 . . . . . 0.01 % . .
europa_universalis_4 76 . -0.23 % -42.11 % . . -0.96 % . .
f1-2015 774 . -0.09 % -28.89 % . . -2.60 % 0.09 % .
furmark-0.7.0 4 . . . . . . . .
gimark-0.7.0 10 . . . . . . . .
glamor 16 . . . . . . . .
humus-celshading 4 . . . . . . . .
humus-domino 6 . . . . . . . .
humus-dynamicbranching 24 . 0.71 % . . . 0.29 % -0.45 % .
humus-hdr 10 . . . . . . . .
humus-portals 2 . . . . . . . .
humus-volumetricfog.. 6 . . . . . . . .
left_4_dead_2 1762 . . . . . . . .
metro_2033_redux 2670 . -0.10 % -7.15 % . . -0.03 % . .
nexuiz 80 . . . . . . . .
pixmark-julia-fp32 2 . . . . . . . .
pixmark-julia-fp64 2 . . . . . . . .
pixmark-piano-0.7.0 2 . . . . . . . .
pixmark-volplosion-.. 2 . . . . . . . .
plot3d-0.7.0 8 . . . . . . . .
portal 474 . . . . . . . .
sauerbraten 7 . . . . . . . .
serious_sam_3_bfe 392 . . -13.20 % . . -1.81 % . .
supertuxkart 4 . . . . . . . .
talos_principle 324 . -0.21 % -18.39 % . . -2.73 % 0.14 % .
team_fortress_2 808 . . . . . . . .
tesseract 430 . 0.08 % -68.57 % . . -0.45 % . .
tessmark-0.7.0 6 . . . . . . . .
thea 172 . . . . . 0.03 % . .
ue4_effects_cave 299 . -0.04 % -10.15 % . . -0.25 % 0.04 % .
ue4_elemental 586 . -0.02 % -13.93 % . . -0.13 % 0.02 % .
ue4_lightroom_inter.. 74 . -0.17 % -70.00 % . . -1.27 % . .
ue4_realistic_rende.. 92 . . -32.58 % . . -0.35 % . .
unigine_heaven 322 . 0.12 % -54.17 % . . -1.42 % -0.12 % .
unigine_sanctuary 264 . . . . . . . .
unigine_tropics 210 . . . . . . . .
unigine_valley 278 . -0.15 % -40.74 % . . -2.00 % 0.09 % .
unity 72 . . . . . 0.03 % . .
warsow 176 . . . . . . . .
warzone2100 4 . . . . . 0.13 % . .
witcher2 1040 . -0.03 % -86.28 % . . -0.28 % 0.01 % .
xcom_enemy_within 1236 . -0.24 % -63.54 % . . -0.93 % 0.18 % .
yofrankie 82 . -0.61 % -100.00 % . . -0.83 % 0.41 % .
-----------------------------------------------------------------------------------------------------------
Total 26002 . -0.13 % -27.03 % . -0.24 % -1.57 % 0.10 % .
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 12 Jul 2016 16:49:57 +0000 (18:49 +0200)]
gallivm: add helper lp_add_attr_dereferenceable
Not sure if this is the right way to do it, but it seems to work.
v2: make it a no-op on LLVM <= 3.5
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 14:22:05 +0000 (16:22 +0200)]
radeonsi: clean up shader value metadata code
No change in behavior.
BTW, tbaa_md_kind == 1, which was the magic number in the code.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 18:13:08 +0000 (20:13 +0200)]
radeonsi: remove LLVMNoUnwindAttribute uses
always set by gallivm
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 11 Jul 2016 17:14:33 +0000 (19:14 +0200)]
radeonsi: fix a typo in SI_PARAM_LINEAR_* handling
introduced in
476e9cee1d0cbe321c401277214e6c36ce5b18c9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 18:00:47 +0000 (20:00 +0200)]
gallium/radeon: normalize the code style
no change in behavior
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 8 Jul 2016 16:03:56 +0000 (18:03 +0200)]
radeonsi: just save buffer sizes instead of buffers while recording IBs
whole buffer objects are not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jon Turney [Tue, 5 Jul 2016 09:40:05 +0000 (10:40 +0100)]
Add c99_alloca.h include to fix compilation on Cygwin
Fix compilation on Cygwin, since
50b22354, by adding c99_alloca.h include,
which should know how to portably make the alloc() prototype available.
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>