add support for SPV_KHR_bit_instructions

Merge pull request #219 from cmarcelo/SPV_EXT_shader_atomic_float16_add

Add header changes for SPV_EXT_shader_atomic_float16_add

Merge pull request #220 from kpet/spv-khr-integer-dot-product

Support SPV_KHR_integer_dot_product

Support SPV_KHR_integer_dot_product

Signed-off-by: David Neto <dneto@google.com>
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
Change-Id: Icd243bb9c2a6f8a40713db215a6ca5946ea7abb3

Add header changes for SPV_EXT_shader_atomic_float16_add

Merge pull request #218 from KhronosGroup/fix-ordering

Fix two ordering problems and rebuild headers.

Fix two ordering problems.

Merge pull request #216 from mkinsner/mkinsner/allocate_vendor_extension_enum_range

Allocate additional Intel vendor extension enum blocks

Merge pull request #213 from alan-baker/SPV_KHR_subgroup_uniform_control_flow

Support SPV_KHR_subgroup_uniform_control_flow

Merge pull request #217 from StuartDBrady/add-C++-for-OpenCL-lang

Add CPP_for_OpenCL to grammar

Merge pull request #177 from MrSidims/private/MrSidims/AP

Upstream ac_fixed and hls_float Intel extensions

Add CPP_for_OpenCL to grammar

Allocate additional Intel vendor extension enum blocks

Merge pull request #215 from dneto0/warnings

buildHeaders: Add override decoration

buildHeaders: Add override decoration

Fixes warnings in AppleClang

Merge pull request #214 from dneto0/cmake-3.0-in-build-headers

Update to CMake 3.0

Update to CMake 3.0

This matches the CMakeLists.txt file in the project root.

Support SPV_KHR_subgroup_uniform_control_flow

Update arbitrary float cast interfaces

Signed-off-by: Artem Gindinson <artem.gindinson@intel.com>

Merge pull request #212 from alan-baker/fix-xml

Fix xml entry for SpvGenTwo generator

Fix xml entry for SpvGenTwo generator

Merge pull request #210 from rAzoR8/spvgentwo

Add SpvGenTwo tools to vendor IDs

Add SpvGenTwo to vendor IDs

Merge pull request #208 from mkinsner/mkinsner/tripcount_loop_control_bit

Reserve loop control bit for upcoming trip count (min,max,avg) control

Fix OpTypeBufferSurfaceINTEL token description (#207)

Fix OpTypeBufferSurfaceINTEL token description

Reserve loop control bit for upcoming trip count (min,max,avg) control

Merge pull request #206 from NikitaRudenkoIntel/sc

Add VectorComputeINTEL as enabling capability for Private StorageClass

Add VectorComputeINTEL as enabling capability for Private StorageClass

According to spec: https://github.com/intel/llvm/pull/1612

Merge pull request #204 from DataBeaver/master

Add generator ID for MSP shader compiler

Add generator ID for MSP shader compiler

Merge pull request #201 from baldurk/spv-khr-non-semantic-info

Add NonSemantic.Vulkan.DebugInfo.100 JSON/header

Merge pull request #202 from mkinsner/mkinsner/mem_operand_allocation_section

Add xml section for memory operand bit allocation tracking

Upstream AP Intel extensions

SPV_INTEL_arbitrary_precision_floating_point and
SPV_INTEL_arbitrary_precision_fixed_point extensions are
being upstreamed.

Specs:
https://github.com/intel/llvm/blob/2f6e965e686354fbb25f9c177a667a646de302eb/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_fixed_point.asciidoc
https://github.com/intel/llvm/blob/bd86b218f749ea0e20ddc18c42db491faf54014a/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_floating_point.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add xml section for memory operand bit allocation tracking, and reserve two bits for an upcoming Intel extension

Add NonSemantic.Vulkan.DebugInfo.100 JSON/header

Merge pull request #178 from orbea/datadir

cmake: Install cmake files to CMAKE_INSTALL_DATADIR

Merge pull request #200 from dneto0/public-spv-khr-linkonce-odr-spv-khr-expect-assume

Support SPV_KHR_linkonce_odr and SPV_KHR_expect_assume

Support SPV_KHR_expect_assume

Support SPV_KHR_linkonce_odr

Merge pull request #198 from alan-baker/read-clock-scope

Change operand name in OpReadClockKHR to match extension

Merge pull request #195 from kvark/patch-1

Add Naga as SPIR-V generation tool

Change operand name in OpReadClockKHR to match extension

* The grammar was not updated when revision 3 of SPV_KHR_shader_clock
  was published
  * That revision renamed the *Execution* operand to *Scope*

Merge pull request #193 from bashbaug/DebugInfoFlags-None

add None as a possible value for DebugInfoFlags

Add Naga as SPIR-V generation tool

Merge pull request #187 from bashbaug/function_control_bit_16

add function control bitfield reservation section

Merge pull request #190 from dneto0/check-enumerant-ordering

Header generator: Check enumerant ordering

Merge pull request #189 from jekstrand/SPV_EXT_shader_atomic_float_min_max

Add header changes for SPV_EXT_shader_atomic_float_min_max

Add header changes for SPV_EXT_shader_atomic_float_min_max

Re-run buildSpvHeaders to fix indentation

Header generator: Check enumerant ordering

In the grammar, enforce ordering rules:
- Instructions must appear in order of their opcode
- Non-instructions: each successive enumerant within a single kind must
  appear in order

- Reorder enumerants Subgroup*MaskKHR enums to satisfy the rule.

add generated headers

Merge pull request #192 from cmarcelo/SPV_KHR_workgroup_memory_explicit_layout

Add SPV_KHR_workgroup_memory_explicit_layout

add None as a possible value for DebugInfoFlags

Add SPV_KHR_workgroup_memory_explicit_layout

Merge pull request #191 from dneto0/reorder-enums-in-spec

Push FPDenormMode, FPOperationMode to the end

Push FPDenormMode, FPOperationMode to the end

This is a cosmetic change for the benefit of generating the SPIR-V spec.
It reorders the "FP Denorm Mode" and "FP Operation Mode" so they are
the last sections in chapter 3 before the instruction listing.
They become 3.37 and 3.38. The idea is to preserve the section numbering
for earlier sections. For example, keep 3.31 as the Capability section.

Merge pull request #176 from MrSidims/private/MrSidims/OtherExtensions

Upstream several Intel extensions

Apply suggestions to Intel extensions PR

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update generated files

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add SPV_INTEL_long_constant_composite extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add SPV_INTEL_loop_fuse extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add SPV_INTEL_fpga_cluster_attributes and SPV_INTEL_fp_fast_math_mode

Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fpga_cluster_attributes.asciidoc
https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fp_fast_math_mode.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_fpga_loop_controls extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_kernel_attributes extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_function_pointers extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_float_controls2 extension

Spec:
https://github.com/intel/llvm/blob/39fa9b0cbfbae88327118990a05c5b387b56d2ef/sycl/doc/extensions/SPIRV/SPV_INTEL_float_controls2.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_vector_compute extension

Spec:
https://github.com/intel/llvm/blob/e185a6b49e4bc9806a799b774977f1196b24f0d6/sycl/doc/extensions/SPIRV/SPV_INTEL_vector_compute.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_fpga_memory_accesses extension

Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_accesses.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_io_pipes extension

Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_io_pipes.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_variable_length_array extension

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_variable_length_array.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_usm_storage_classes extension

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_usm_storage_classes.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_arbitrary_precision_integers extensions

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_int.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_inline_assembly extension

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_inline_assembly.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_fpga_buffer_location extension

Spec:
https://github.com/intel/llvm/blob/2237b42035f31cb10b16d4f9abaeed45bed98587/sycl/doc/extensions/SPIRV/SPV_INTEL_fpga_buffer_location.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

add function control bitfield reservation section
reserve bit 16 for an upcoming Intel extension

Merge pull request #184 from dgkoch/dkoch_remove_hittkhr

remove HitTKHR alias

remove HitTKHR

It was not added to the SPV_KHR_ray_tracing extension since it is just
an alias of RayTMaxKHR.

Merge pull request #180 from dneto0/issue-179

MeshShadingNV enables builtins PrimitiveId, Layer, and ViewportIndex

MeshShadingNV enables builtins PrimitiveId, Layer, and ViewportIndex

Fixes #179

See extension SPV_NV_mesh_shader

Merge pull request #182 from dgkoch/khr_rt_final

Updates to final ray tracing extensions

de-alias/reassign OpIgnoreIntersectionKHR/OpTerminateRayKHR

vulkan/vulkan#2374

Raytracing and Rayquery updates for final

Updated headers for new trace/executeCallable and acceleration structure cast.

cmake: Install cmake files to CMAKE_INSTALL_DATADIR

Reserve additional loop control bit for Intel extension (NoFusionINTEL) (#175)

Add EmbarkStudios/rust-gpu to vendor list. (#174)

Bump revision to 4, for SPIR-V 1.5.

Add SPV_EXT_shader_image_int64 (#170)

Co-authored-by: Arkadiusz Sarwa <arkadiusz.sarwa@amd.com>

Added SPV_KHR_fragment_shading_rate (#172)

 Register the Xenia emulator as a generator (#171)

Register the Messiah SPIR-V CodeGen (#169)

Register the ANGLE compiler (#168)

Rebuild of latest headers, which slightly moves OpTerminateInvocation

Reserve SPIR-V token range for upcoming Intel extensions. (#165)

Update BUILD.bazel and BUILD.gn (#166)

* Export NonSemantic.ClspvReflection.h for both
* Add exports for the extended instruction sets in the unified1
  directory (for use in SPIRV-Tools)

Publish the headers for the clspv embedded reflection non-semantic extended instruction set (#164)

* Clspv non-semantic reflection instruction set
* Version 1

Update the registry in spir-v.xml to modernize and split out opcodes. (#156)

Support SPV_KHR_terminate_invocation (#163)

* Support SPV_KHR_terminate_invocation

* Fix order in spirv.core.grammar.json

Co-authored-by: David Neto <dneto@google.com>

Merge pull request #162 from vkushwaha-nv/SPV_EXT_shader_atomic_float

Add changes for SPV_EXT_shader_atomic_float

Add changes for SPV_EXT_shader_atomic_float