Timur Kristóf [Mon, 10 Jul 2023 08:36:20 +0000 (10:36 +0200)]
radv: Move radv_select_hw_stage to radv_shader_info.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>
Timur Kristóf [Mon, 3 Jul 2023 15:07:18 +0000 (17:07 +0200)]
ac/nir: Add new pass to lower intrinsics to shader args.
This is beneficial for intrinsics that do an algebraic
instruction such as bitfield extract on shader arguments,
because it allows NIR to be aware of these instructions and
optimize them together with other algebraic instructions in
the shader.
Currently, just handle subgroup_id and num_subgroups intrinsics.
More will be added here in the future.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>
Timur Kristóf [Mon, 3 Jul 2023 15:06:50 +0000 (17:06 +0200)]
ac/nir: Simplify arg unpacking when shift is zero.
This is so we can just use the same function when it's zero.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>
Timur Kristóf [Tue, 4 Jul 2023 12:28:45 +0000 (14:28 +0200)]
aco: Fix subgroup_id intrinsic on GFX10.3+.
Change this to match how it works in the LLVM backend.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>
Karmjit Mahil [Mon, 26 Jun 2023 10:52:39 +0000 (11:52 +0100)]
pvr: Submit PR commands
This commit adds a partial render command to job submission.
For geom only jobs we must always submit a pr command in case we
enter SPM. For now, for geom+frag jobs, we'll also always submit
a pr command event.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>
Karmjit Mahil [Thu, 6 Jul 2023 09:26:04 +0000 (10:26 +0100)]
pvr: Restructure `rogue_kmd_stream.xml`
Now things are structured in sections, like the other xml files.
And elements within a section are sorted alphabetically.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>
Karmjit Mahil [Thu, 29 Jun 2023 14:17:57 +0000 (15:17 +0100)]
pvr: Remove some magic numbers and increments from km stream
- Update and add csbgen definitions to make the content of the
geom and frag km stream more obvious.
- Replace some of the hard coded constants with defines.
- Adds some static assert to make the provenance of definitions
more clear as well as making sure things fit properly.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>
Karmjit Mahil [Mon, 26 Jun 2023 12:09:53 +0000 (13:09 +0100)]
pvr: Use the SPM EOT on barrier stores
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>
Karmjit Mahil [Wed, 28 Jun 2023 13:39:59 +0000 (14:39 +0100)]
pvr: Compile SPM EOT shader
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>
Karmjit Mahil [Wed, 28 Jun 2023 13:39:51 +0000 (14:39 +0100)]
pvr: Remove mrt setup from SPM EOT
Remove the mrt setup stuff since the EOT program only support
output registers for now. When implementing the tile buffer
support this change can be reverted, or things could be changed
to better fit with how the compiler wants things.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>
Marcin Ślusarz [Mon, 10 Jul 2023 12:05:37 +0000 (14:05 +0200)]
intel/compiler: remove NV_mesh_shader support
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24071>
Marcin Ślusarz [Mon, 10 Jul 2023 12:02:28 +0000 (14:02 +0200)]
anv: drop support for VK_NV_mesh_shader
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24071>
Marcin Ślusarz [Mon, 10 Jul 2023 11:59:37 +0000 (13:59 +0200)]
hasvk: remove dead code & comments related to mesh shading
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24071>
Marcin Ślusarz [Tue, 11 Jul 2023 11:57:47 +0000 (13:57 +0200)]
iris: avoid duplicating validation entries
If the *first* BO is not marked as "written", but the same BO is marked
as "written" later, then it will be added twice, because the first
instance will have index_for_handle equal to 0.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24108>
Frank Binns [Thu, 13 Jul 2023 12:35:39 +0000 (13:35 +0100)]
pvr: skip setting up SPM consts buffer when no const shared regs are used
This is a temporary measure until the zeroed shaders are replaced with the real
ones. This avoids a VK_ERROR_OUT_OF_DEVICE_MEMORY error due to a zero sized
allocation.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Fixes:
1dfd5351249 ("pvr: Setup SPM background object")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24139>
Alyssa Rosenzweig [Tue, 30 May 2023 15:41:12 +0000 (11:41 -0400)]
ntt: Switch to new-style registers and modifiers
Use all the nir_legacy.h features to transition away from the deprecated
structures. shader-db is quite happy. I assume that's a mix of more aggressive
source mod usage and better coalescing (nir-to-tgsi doesn't copyprop).
total instructions in shared programs: 900179 -> 887156 (-1.45%)
instructions in affected programs: 562077 -> 549054 (-2.32%)
helped: 5198
HURT: 470
Instructions are helped.
total temps in shared programs: 91165 -> 91162 (<.01%)
temps in affected programs: 398 -> 395 (-0.75%)
helped: 21
HURT: 18
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24116>
Alyssa Rosenzweig [Thu, 13 Jul 2023 11:13:34 +0000 (07:13 -0400)]
nir/legacy: Fix handling of fsat(fabs)
Consider code like:
32x4 %2 = @load_interpolated_input (%1, %0 (0x0)) (base=0, component=0, dest_type=float32, io location=VARYING_SLOT_VAR0 slots=1 mediump) // Color
32x4 %3 = fabs %2
32x4 %4 = fsat %3
32x4 %5 = fsin %4
The existing logic would incorrectly tell the backend that both fabs and fsat
could be folded, and then half the shader disappears. Whoops. Fix by stopping
the folding in this case. I choose to do this check in the fsat rather than the
fabs because it's more straightforward (1 source vs N uses) but it's somewhat
arbitrary.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24116>
Alyssa Rosenzweig [Wed, 12 Jul 2023 12:17:52 +0000 (08:17 -0400)]
nir/legacy: Fix fneg(load_reg) case
Consider the IR:
%0 = load_reg
%1 = fneg %0
%2 = ffloor %1
%3 = bcsel .., .., %1
Because the fneg has both foldable and non-foldable users, nir/legacy does not
fold the fneg into the load_reg. This ensures that the backend correctly emits a
dedicated fneg instruction (with the load_reg folded in) for the bcsel to use.
However, because the chasing helpers did not previously take other uses of a
modifier into account, the helpers would fuse in the fneg to the ffloor. Except
that doesn't work, because the load_reg instruction is supposed to be
eliminated. So we end up with broken chased IR:
1 = fneg r0
2 = ffloor -NULL
3 = bcsel, ..., 1
The fix is easy: only fold modifiers into ALU instructions if the modifiers can
be folded away. If we can't eliminate the modifier instruction altogether, it's
not necessarily beneficial to fold it anyway from a register pressure
perspective. So this is probably ok. With that check in place we get correct IR
1 = fneg r0
2 = ffloor 1
3 = bcsel, ..., 1
Fixes carchase/230.shader_test under softpipe.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24116>
Juston Li [Thu, 13 Jul 2023 20:29:42 +0000 (13:29 -0700)]
zink: remove venus from renderpass optimizations
For venus, need to query the underlying driver.
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/9358
Remove venus for now as it is causing crashes on top of anv/radv.
Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24147>
Alyssa Rosenzweig [Tue, 11 Jul 2023 12:59:35 +0000 (08:59 -0400)]
compiler: Remove blend enums duplicating util
Now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Tue, 11 Jul 2023 12:59:12 +0000 (08:59 -0400)]
gallium: Remove pipe->compiler BLEND enum translation
Now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Tue, 11 Jul 2023 12:42:36 +0000 (08:42 -0400)]
panfrost: Convert to PIPE_BLEND enums internally
This removes all the users of the compiler enums, and is a lot more natural now
that nir_lower_blend speaks PIPE_BLEND enums.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Tue, 11 Jul 2023 11:51:03 +0000 (07:51 -0400)]
nir/lower_blend: Use util enums
This avoids the silly compiler versions. Some bits are slightly more
complicated, because they have to account for inverted enum values (rather than
a separate invert bit), but this is a LOT friendlier to drivers using the pass
and it makes the pass itself more readable.
The conversion functions in panfrost/panvk will go away momentarily.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Mon, 10 Jul 2023 22:14:03 +0000 (18:14 -0400)]
lvp: Use common blend/logicop translation
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Mon, 10 Jul 2023 20:27:24 +0000 (16:27 -0400)]
vulkan: Add helpers for blend enum translation
Vulkan drivers that use nir_lower_blend need to translate Vulkan enums to the
common (non-Vulkan) versions used in nir_lower_blend. We don't need to duplicate
that boilerplate in every VK driver that uses nir_lower_blend, move panvk's
versions to common code so we can use them in agxv. I suspect powervr wants this
too.
It might be useful to also share the logic to translate vk_color_blend_state
to nir_lower_blend_options wholesale, but panvk wouldn't use it and agxv is
downstream so it wouldn't have any in-tree users. So I'll keep that part
vendored (for now). For now, let's share the easy win of the enum translation.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Tue, 11 Jul 2023 11:50:35 +0000 (07:50 -0400)]
util/blend: Add helpers for normalizing inverts
To avoid duplicating piles of cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Tue, 11 Jul 2023 11:33:21 +0000 (07:33 -0400)]
gallium,util: Move util_blend_dst_alpha_to_one
PanVK will use this too.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Tue, 11 Jul 2023 14:06:47 +0000 (10:06 -0400)]
gallium,util: Move blend enums to util/
For sharing across the tree.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Alyssa Rosenzweig [Tue, 11 Jul 2023 14:06:12 +0000 (10:06 -0400)]
gallium/trace: Collect enums from multiple files
We're going to do some code motions out of p_state.h so the one file assumption
will fail. relax it.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>
Dylan Baker [Thu, 13 Jul 2023 16:46:44 +0000 (09:46 -0700)]
docs: truncate feature list for 23.3-devel
Which I forgot to do when branching for 23.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24143>
Connor Abbott [Wed, 12 Jul 2023 18:00:07 +0000 (20:00 +0200)]
afuc: Rework and significantly expand README.rst
This hasn't been updated since the a5xx days, and we've learned much
more since then. I've tried to expand it from a random collection of
notes to a more complete guide to explaining how to read the firmware
and understand the various tricks it uses to make code more compact.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24125>
Amber [Fri, 26 May 2023 13:31:43 +0000 (15:31 +0200)]
turnip: Add debug option to allow non-conforming features.
This is because we still may want to be able to expose vulkan 1.3
on some devices that technically do not support it, for instance
the adreno 610 has everything required except multiview, which is
not essential for most games.
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Amber [Mon, 17 Apr 2023 16:53:56 +0000 (18:53 +0200)]
freedreno: Add support for devices not supporting double thread size.
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Amber [Tue, 11 Apr 2023 05:31:46 +0000 (07:31 +0200)]
ir3: handle non-uniform case for atomic image/ssbo intrinsics
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Amber [Mon, 10 Apr 2023 11:49:54 +0000 (13:49 +0200)]
freedreno, turnip: set correct reg_size_vec4 for a6xx_gen1_low
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Amber [Mon, 10 Apr 2023 11:48:36 +0000 (13:48 +0200)]
turnip: make sampler_minmax support configurable.
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Amber [Mon, 10 Apr 2023 11:42:25 +0000 (13:42 +0200)]
turnip: Add support for devices not supporting double thread size.
On these devices the actual thread size for compute shaders seems to be
controlled by REG_A6XX_HLSQ_FS_CNTL_0 rather than the CS-related
register.
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Amber [Mon, 10 Apr 2023 11:28:31 +0000 (13:28 +0200)]
ir3: make wave_granularity configurable
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Danylo Piliaiev [Fri, 3 Feb 2023 11:00:21 +0000 (12:00 +0100)]
ir3: Make FS tex prefetch optimization optional
a610 and friends seem not to have tex prefetch.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Danylo Piliaiev [Thu, 2 Feb 2023 17:21:52 +0000 (18:21 +0100)]
turnip: Make multiview support configurable per generation
a610 and similar models don't have HW support for multiview,
proprietary driver unrolls the drall calls instead.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Danylo Piliaiev [Mon, 30 Jan 2023 17:28:52 +0000 (18:28 +0100)]
freedreno: Add A605, A608, A610, A612 GPUs definition
While we tested a610, a605/a608 are added by observing traces being same
to a610.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Danylo Piliaiev [Thu, 2 Feb 2023 16:23:22 +0000 (17:23 +0100)]
freedreno,turnip: Make VS input attr/binding count configurable
a610 and similar models have fewer VS inputs available.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Danylo Piliaiev [Thu, 2 Feb 2023 16:19:54 +0000 (17:19 +0100)]
freedreno,turnip: Make CS shared memory size configurable
a610 and similar models have less shared memory size.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Danylo Piliaiev [Mon, 30 Jan 2023 17:09:42 +0000 (18:09 +0100)]
freedreno,turnip: Make number of VSC pipes configurable
a610/a608 has less pipes, so we need to make it configurable.
In particular we need to program all of the VSC_PIPE_CONFIG_REG[n]
rather than leaving garbage values for the unused pipes. Pointing
multiple VSC pipes at the same bin makes the hw angry.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Konrad Dybcio [Fri, 27 Jan 2023 20:16:44 +0000 (21:16 +0100)]
freedreno: Set magic writes per-GPU, using existing data
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Danylo Piliaiev [Mon, 30 Jan 2023 16:08:29 +0000 (17:08 +0100)]
freedreno, turnip: Clarify some RB_CCU_CNTL fields
There is no .gmem field, there is a ccu color cache size field
which tells the size as a fraction of depth cache used in direct
rendering.
There is also GMEM_FAST_CLEAR_DISABLE flag which is set on a608/a610.
Since these values will stop being the same between models,
make them configurable.
Credits to Connor Abbott for deciphering color cache size meaning.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
Lionel Landwerlin [Mon, 10 Jul 2023 07:20:33 +0000 (10:20 +0300)]
anv: hide exec_flags selection inside the i915 backend
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24073>
Sil Vilerino [Wed, 12 Jul 2023 14:54:16 +0000 (10:54 -0400)]
util: Blake3 - Identify arm64ec as aarch64 instead of x64
ARM64EC is a new build target for Windows ARM64 devices for x64 support.
Currently that build flavor fails due to attempting to use x64 intrinsics.
This commit fixes it by changing the auto-detection to be aarch64
instead of x64 for arm64ec.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24119>
Filip Gawin [Sun, 2 Jul 2023 11:40:30 +0000 (13:40 +0200)]
crocus: Avoid fast-clear with incompatible view
Port of code from iris.
Original author: Nanley Chery
Helps with fast_color_clear@fcc-write-after-clear
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24135>
Danylo Piliaiev [Mon, 10 Jul 2023 14:28:41 +0000 (16:28 +0200)]
freedreno/cffdec: Decode CP_DRAW_AUTO
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24074>
Pavel Ondračka [Thu, 13 Jul 2023 08:57:11 +0000 (10:57 +0200)]
r300: update RV370 failures
This was missed in
0bf6dcb785ce82006f9757217153735e39127834
There is a loop which iterates over a temp array. NIR optimization
moves the real work out of the loop and what remains are just ALU ops
with undefs. So after converting undefs to zero, the ALU ops are
optimized out and DCE kills the loop. This is a good thing in
general and we don't fail the linking due to the loop presence.
However than we hit the shader constants and ALU limits later :-(
So from dEQP POW we go from NotSupported to Fail.
Fixes:
0bf6dcb785ce82006f9757217153735e39127834
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24134>
Frank Binns [Mon, 10 Jul 2023 10:20:33 +0000 (11:20 +0100)]
pvr: clang-format fixes
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24070>
Jordan Justen [Fri, 28 Apr 2023 01:35:27 +0000 (21:35 -0400)]
isl: Set MOCS to uncached for MTL stream-out
Without this change various OpenGL CTS tranform feedback tests were
failing.
Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>
Jordan Justen [Fri, 23 Jun 2023 01:05:41 +0000 (18:05 -0700)]
isl/dev: Add uncached MOCS value
Rework:
* Jordan: Add uncached for all platforms (Requested by Francisco)
* Jordan: Use gen7 & gen8 values suggested by Francisco
* Jordan: Fix IVB and CHV MOCS mistakes pointed out by Francisco
Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>
Jordan Justen [Mon, 10 Jul 2023 18:28:38 +0000 (11:28 -0700)]
genxml/chv: Add MEMORY_OBJECT_CONTROL_STATE_CHV to document compared to BDW
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>
Jordan Justen [Mon, 10 Jul 2023 18:17:57 +0000 (11:17 -0700)]
genxml/hsw: Add additional MOCS field enumerations
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>
Jordan Justen [Fri, 28 Apr 2023 01:35:27 +0000 (21:35 -0400)]
anv,iris,hasvk: Use ISL_SURF_USAGE_STREAM_OUT_BIT for setting stream-out MOCS
Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>
Jordan Justen [Fri, 23 Jun 2023 00:47:08 +0000 (17:47 -0700)]
isl: Add ISL_SURF_USAGE_STREAM_OUT_BIT
Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>
Helen Koike [Mon, 10 Jul 2023 14:23:31 +0000 (11:23 -0300)]
docs/ci: Add docs for EXTRA_LOCAL_PACKAGES
Add a section about reusing the CI scripts for other projects.
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23894>
Helen Koike [Wed, 28 Jun 2023 00:01:12 +0000 (21:01 -0300)]
ci: add EXTRA_LOCAL_PACKAGES to apt-get install
This can make it more convenient for other projects to reuse these
scripts.
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23894>
Helen Koike [Tue, 27 Jun 2023 23:43:25 +0000 (20:43 -0300)]
ci: re-add EXTRA_LOCAL_PACKAGES to rootfs
This variable was removed on commit
848f59deda3ae7bb99409a3d15ddafe96b763ea1 when file `create-rootfs.sh`
was splitted.
Re-add it.
This can make it more convenient for other projects to reuse these
scripts.
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23894>
David Heidelberg [Thu, 13 Jul 2023 00:23:16 +0000 (02:23 +0200)]
ci/freedreno: update a530 flakes
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24132>
Dylan Baker [Wed, 12 Jul 2023 23:03:53 +0000 (16:03 -0700)]
docs: Update release calendar for 23.2.0-rc1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24131>
Faith Ekstrand [Wed, 12 Jul 2023 08:06:35 +0000 (03:06 -0500)]
nv50/ir: Convert to new-style NIR registers
Shader-db results on Turing:
total inst in shared programs :
11121531 ->
11121458 (-0.00%)
total gpr in shared programs : 1848287 -> 1848425 (0.01%)
total ugpr in shared programs : 0 -> 0 (0.00%)
total local in shared programs : 27200 -> 27200 (0.00%)
total shared in shared programs : 236476 -> 236476 (0.00%)
total bytes in shared programs :
177944496 ->
177943328 (-0.00%)
total cached in shared programs : 0 -> 0 (0.00%)
inst gpr ugpr local shared bytes cached
helped 470 50 0 0 0 470 0
hurt 327 197 0 0 0 327 0
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24110>
Yiwei Zhang [Wed, 12 Jul 2023 20:16:28 +0000 (20:16 +0000)]
venus: refactor query feedback cmd record
Now copy and reset are similar enough to unify.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24130>
Yiwei Zhang [Wed, 12 Jul 2023 19:05:20 +0000 (19:05 +0000)]
venus: add a missing barrier before copying query feedback
The 1st sync scope of vkCmdCopyQueryPoolResults is not sufficient to
cover transfer writes against query feedback buffer. We must ensure
ordering against prior query reset cmd where the feedback buffer fill
gets injected.
Fixes:
de4593faa193 ("venus: add query pool feedback cmds")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24130>
Mohamed Ahmed [Tue, 11 Jul 2023 17:23:59 +0000 (20:23 +0300)]
vulkan/util: Use ycbcr_info for multiplane helpers in vk_format.c
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24096>
Mohamed Ahmed [Tue, 11 Jul 2023 17:12:35 +0000 (20:12 +0300)]
vulkan/util: Support VK_EXT_ycbcr_2plane_444_formats color formats in vk_format.c
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24096>
Mohamed Ahmed [Tue, 11 Jul 2023 16:13:32 +0000 (19:13 +0300)]
vulkan/util: Support 10-bit and 12-bit color formats in ycbcr_info in vk_format.c
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24096>
Yiwei Zhang [Wed, 12 Jul 2023 17:09:22 +0000 (17:09 +0000)]
venus: ensure consistency of query overflow behavior
Fixes:
e6cffa1f0e4e ("venus: use feedback for vkGetQueryPoolResults")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24123>
Yiwei Zhang [Wed, 12 Jul 2023 16:39:30 +0000 (16:39 +0000)]
venus: handle query feedback creation failure
Fixes:
e6cffa1f0e4e ("venus: use feedback for vkGetQueryPoolResults")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24123>
Friedrich Vock [Tue, 11 Jul 2023 17:31:51 +0000 (19:31 +0200)]
radv/ci: Set DRIVER_NAME in LAVA raven vkcts jobs
Some CTS tests work with RADV, but take a very long time, making
deqp-runner trigger timeout failures. These tests are supposed to be
skipped, so they're contained in radv-skips.txt. But without setting
DRIVER_NAME to "radv", deqp-runner.sh won't pick up that file.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24095>
Eric Engestrom [Wed, 12 Jul 2023 15:36:27 +0000 (16:36 +0100)]
ci: avoid running hardware jobs if lint fails - now on Windows too!
I missed this in !23774.
Fixes:
a1c1cce9dfc2d8400a67 ("ci: avoid running hardware jobs if there are already trivial issues")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24121>
Eric Engestrom [Wed, 12 Jul 2023 15:36:27 +0000 (16:36 +0100)]
ci: avoid running hardware jobs if lint fails - now on LAVA too!
I missed this in !23774.
Fixes:
a1c1cce9dfc2d8400a67 ("ci: avoid running hardware jobs if there are already trivial issues")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24121>
Alyssa Rosenzweig [Mon, 12 Jun 2023 20:59:11 +0000 (16:59 -0400)]
zink: Switch to register intrinsics
SPIR-V does not have anything like nir_register natively, so we were already
inserting loads/stores for register sources/destinations. That means it's easy
to switch to register intrinsics, getting explicit load_reg/store_reg intrinsics
in the NIR and translating those to the SPIR-V load/stores, dropping the
handling for nir_register. There's no need to use any of the chasing helpers for
coalescing the load/stores, like a hardware backend would. (In
fact, the underlying Vulkan driver will probably turn this back into SSA.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24111>
Dylan Baker [Wed, 12 Jul 2023 17:32:49 +0000 (10:32 -0700)]
VERSION: bump to 23.3.0-devel
For further development
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24124>
Karol Herbst [Sat, 8 Jul 2023 16:53:38 +0000 (18:53 +0200)]
api/icd: drop static lifetime from `get_ref` return type
This was never correct as the object pointed to can be destroyed at any
moment.
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24061>
Karol Herbst [Sat, 8 Jul 2023 16:41:32 +0000 (18:41 +0200)]
rusticl/device: make it &'static
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24061>
Karol Herbst [Sat, 8 Jul 2023 15:38:02 +0000 (17:38 +0200)]
rusticl: Replace &Arc<Device> with &Device
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24061>
Karol Herbst [Mon, 10 Jul 2023 13:09:20 +0000 (15:09 +0200)]
rusticl/kernel: silence newer clippy warning
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24061>
Eric Engestrom [Tue, 20 Jun 2023 13:37:22 +0000 (14:37 +0100)]
ci: avoid running hardware jobs if there are already trivial issues
Suggested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23774>
Danylo Piliaiev [Fri, 30 Jun 2023 13:30:06 +0000 (15:30 +0200)]
freedreno/regs: Document a7xx CP_BV_BR_COUNT_OPS
Fully tested on HW. Credits to Connor Abbott for finding out how
it works.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Thu, 29 Jun 2023 17:30:08 +0000 (19:30 +0200)]
freedreno/regs: Properly document a7xx CP_EVENT_WRITE, CP_WAIT_TIMESTAMP
Event write is changes so much in a7xx that it makes sense to
create a new event CP_EVENT_WRITE7.
All credits to Connor Abbott for finding out what different flags
in these commands are doing.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Thu, 20 Apr 2023 15:07:30 +0000 (17:07 +0200)]
tu: Use reg usage tables for stale reg dbg option
Defining regs to stomp as ranges in a separate header is a mistake
from maintenance standpoint. Now we have this information at the
point where reg is defined.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Tue, 11 Jul 2023 12:33:10 +0000 (14:33 +0200)]
tu: Allow reg stomping of compute related registers
We don't use draw states for dispatches, so the bound pipeline
could be overwritten by reg stomping in a renderpass or blit.
The solution is to re-emit pipeline's IB on every dispatch if
reg stomping is used.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Thu, 20 Apr 2023 15:06:21 +0000 (17:06 +0200)]
freedreno/regs: Define usage for all a6xx/a7xx regs
Could be used for knowing which regs to stomp and to verify that
only appropriate regs are emitted.
Each register that is actually being used by driver should have "usage"
defined, currently there are following usages:
- "cmd" - the register is used outside of renderpass and blits,
roughly corresponds to registers used in ib1 for Freedreno
- "rp_blit" - the register is used inside renderpass or blits
(ib2 for Freedreno)
It is expected that register with "cmd" usage may be written into only at
the start of the command buffer (ib1), while "rp_blit" usage indicates that
register is either overwritten by renderpass/blit (ib2) or not used if not
overwritten by a particular renderpass/blit.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Thu, 20 Apr 2023 15:03:29 +0000 (17:03 +0200)]
freedreno/regs: Generate per-gen reg usage tables
"reg" and "array" now could have `usage="a,b,c"` attribute, for each
usage a separate array is generated.
Would be used for register stomping debug option.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Tue, 27 Jun 2023 13:52:54 +0000 (15:52 +0200)]
freedreno/regs: Fix a7xx SP_FS_PREFETCH definition
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Mon, 3 Apr 2023 16:53:29 +0000 (18:53 +0200)]
freedreno/regs: Add more a7xx regs and reg fields
Deduced from a740 cmdtraces from running CTS on prop driver.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Wed, 5 Jul 2023 14:40:52 +0000 (16:40 +0200)]
freedreno/regs: Add some new a7xx events
There are many more a7xx events but they are left for later.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Wed, 5 Jul 2023 14:08:54 +0000 (16:08 +0200)]
freedreno/regs: Add 2 new a7xx modes to CP_COND_REG_EXEC
Also reworked how CP_COND_REG_EXEC is defined to print
less irrelevant fields.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Wed, 5 Jul 2023 14:04:49 +0000 (16:04 +0200)]
freedreno/regs: a7xx has a new source type CP_REG_TEST
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Wed, 5 Jul 2023 14:01:26 +0000 (16:01 +0200)]
freedreno/regs: Add a7xx pseudo-regs to CP_SET_PSEUDO_REG
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Wed, 5 Jul 2023 13:57:41 +0000 (15:57 +0200)]
freedreno/regs: Clarify polling on a7xx for CP_WAIT_REG_MEM/CP_COND_WRITE5
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Wed, 5 Jul 2023 13:52:47 +0000 (15:52 +0200)]
freedreno/regs: Document a7xx CP_MODIFY_TIMESTAMP
Clears, adds to local, or adds to global timestamp
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Wed, 5 Jul 2023 13:49:19 +0000 (15:49 +0200)]
freedreno/regs: Document CP_MEM_TO_SCRATCH_MEM
Best guess is that it is a faster way to fetch all the VSC_STATE registers
and keep them in a local scratch memory instead of fetching every time
when skipping IBs.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Connor Abbott [Wed, 28 Jun 2023 16:25:12 +0000 (17:25 +0100)]
freedreno/regs: Document a7xx CP_FIXED_STRIDE_DRAW_TABLE
Executes an array of fixed-size command buffers where each
buffer is assumed to have one draw call, skipping buffers with
non-visible draw calls.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Mon, 3 Apr 2023 11:25:12 +0000 (13:25 +0200)]
freedreno/regs: More CP commands are the same on a7xx as on a6xx
These ones are seen to be used by blob in CTS, the rest a6xx commands
were not seen beeing used.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Tue, 20 Jun 2023 14:04:55 +0000 (16:04 +0200)]
freedreno/regs: Change a7xx regs to have open range for generation
Until proven otherwise regs stay the same between gens.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
Danylo Piliaiev [Fri, 21 Apr 2023 10:36:38 +0000 (12:36 +0200)]
freedreno/rnn: Take into account array's variant for regs
Otherwise even if array only exists in one generation the code for
its registers is generated for all gens.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
projects / platform / upstream / mesa.git / log