zink: reset tc fb info upon splitting a renderpass

not sure if this actually affects anything, but if a renderpass has
to be split for some reason, ensure subsequent renderpasses don't lose
data

also ensure that rp data isn't lost when triggering primgen clears and
delete a now-invalid assert

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21800>

zink: don't use/update tc rp info while blitting

this is illegal

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21800>

zink: add an assert to catch renderpass optimizing bugs

this should only trigger if tc has a bug

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21800>

intel/fs: Fix register coalesce in presence of force_writemask_all copy source writes.

This fixes the behavior of register coalesce in cases where the source
of a copy is written elsewhere in the program by a force_writemask_all
instruction, which could cause the overwrite to be executed for an
inactive channel under non-uniform control flow, causing
can_coalesce_vars() to give incorrect results.  This has been reported
in cases like:

> while (true) {
>    x = imageSize(img);
>    if (non_uniform_condition()) {
>       y = x;
>       break;
>    }
> }
> use(y);

Currently the register coalesce pass would coalesce x and y in the
example above, which is invalid since in the example above imageSize()
is implemented as a force_writemask_all SEND message, whose result is
broadcast to all channels, so when a given channel executes 'y = x'
and breaks out of the loop, another divergent channel can execute a
subsequent iteration of the loop overwriting 'x' with a different
value, hence coalescing y and x into the same register changes the
behavior of the program.

Note that this is a regression introduced by commit a4b36cd3dd30.  In
order to avoid the problem without reverting that patch, we prevent
register coalesce if there is an overwrite of the source with
force_writemask_all behavior inconsistent with the copy and this
occurs anywhere in the intersection of the live ranges of source and
destination, even if it occurs lexically before the copy, since it
might be physically executed after the copy under divergent loop
control flow.

Fixes: a4b36cd3dd30 ("intel/fs: Coalesce when the src live range is contained in the dst")
Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21351>

intel/fs: Fix copy propagation dataflow analysis in presence of force_writemask_all ACP overwrites.

This fixes the behavior of copy propagation in cases where either the
source or destination of an ACP is overwritten elsewhere in the
program by a force_writemask_all instruction, which could cause the
overwrite to be executed for an inactive channel under non-uniform
control flow, causing the current per-channel dataflow propagation to
give incorrect results.  This has been reported in cases like:

> while (true) {
>    x = imageSize(img);
>    if (non_uniform_condition()) {
>       y = x;
>       break;
>    }
> }
> use(y);

Currently the copy propagation pass would propagate copy 'y = x' into
'use(y)', which is invalid since in the example above imageSize() is
implemented as a force_writemask_all SEND message, whose result is
broadcast to all channels, so when a given channel executes 'y = x'
and breaks out of the loop, another divergent channel can execute a
subsequent iteration of the loop overwriting 'x' with a different
value, hence replacing 'y' with 'x' at 'use(y)' changes the behavior
of the program.

This patch extends the global dataflow analysis algorithm to determine
whether there is any control flow path from a given copy to an
overwrite of its source or destination which has force_writemask_all
behavior inconsistent with the copy, and in such case prevents copy
propagation for that ACP entry at any point of the program which can
be reached from the overwrite, even if the copy is statically
re-executed along all such control flow paths (as in the example
above), since the execution of the overwrite for a given channel i may
corrupt other channels j!=i inactive for the subsequently re-executed
copy.

Note that a simpler solution has been attempted which fully shuts down
copy propagation if such a force_writemask_all ACP overwrite is
present /anywhere/ in the program regardless of its location in the
control flow graph, however that led to large shader-db regressions in
some programs from shader-db (like a CS from Car Chase which would
emit 53% more instructions).  With this solution the only handful of
shaders that suffer instruction count regressions seem to be getting
misoptimized right now (e.g. some compute shaders from Deus Ex
Mankind).  This solution doesn't seem to affect the run-time of
shader-db significantly, it's less than 1% higher with the fix
applied.

Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21351>

intel/fs: Track force_writemask_all behavior of copy propagation ACP entries.

force_writemask_all determines whether all channels of the copy are
actually valid, and may be required to be set for it to be propagated
safely in cases where the destination of the copy is used by another
force_writemask_all instruction, or when the copy occurs in a
divergent control flow block different from its use.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21351>

i965/vec4: Implement uclz in the vec4 backend

Commit 28311f9d029 moved ufind_msb lowering to NIR and started emitting
uclz.  Unfortunately, the vec4 backend never actually implemented uclz.

It's trivial to do.  Now it does.

Fixes: 28311f9d029 ("nir: intel/compiler: Move ufind_msb lowering to NIR")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21974>

intel/fs: Make bld.F16TO32 actually emit F16TO32 not F32TO16

Ahem, "add builder helpers that work on Gfx7"...now might actually work.
Too much copy and paste...

Fixes: 966995d9117 ("intel/fs: Add builder helpers for F32TO16/F16TO32 that work on Gfx7.x")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21974>

intel/vec4: Retype texture/sampler indexes to UD

generate_tex() asserts that sampler_index.type == UD, but commit
83fd7a5ed15 removed the uint temporary, which caused us to see D at
some points.  Really, either should be fine, but let's just put the
UD retype back.  This fixes a ton of things in crocus.

Fixes: 83fd7a5ed15 ("intel: Use nir_lower_tex_options::lower_index_to_offset")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21974>

nir: Propagate alignment when rematerializing cast derefs

Fixes: 878a8daca6bf ("nir: Add alignment information to cast derefs")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21975>

zink: track tc fences better

tc fence lifetimes can exceed the lifetimes of their parent contexts,
which means they can be destroyed after mfence->fence has been destroyed

to avoid invalid memory access on a destroyed fence, store all the assigned
tc fences into an array on the real fence and then use that to unset fence
pointers on any outstanding tc fences

fixes flakiness in dEQP-EGL.functional.sharing.gles2.multithread.random_egl_sync.images.texsubimage2d.12

in caselist:
dEQP-EGL.functional.query_context.get_current_surface.rgba4444_pbuffer
dEQP-EGL.functional.create_surface.platform_window.rgba5551_depth_no_stencil
dEQP-EGL.functional.query_surface.simple.pbuffer.rgb888_depth_no_stencil
dEQP-EGL.functional.color_clears.multi_context.gles2.rgb888_pixmap
dEQP-EGL.functional.color_clears.multi_context.gles1_gles2.rgba8888_window
dEQP-EGL.functional.color_clears.multi_context.gles1_gles2_gles3.rgb888_window
dEQP-EGL.functional.render.multi_thread.gles2_gles3.rgba5551_pbuffer
dEQP-EGL.functional.sharing.gles2.multithread.random_egl_sync.buffers.buffersubdata.3
dEQP-EGL.functional.sharing.gles2.multithread.random_egl_sync.programs.link.6
dEQP-EGL.functional.sharing.gles2.multithread.random_egl_sync.images.texsubimage2d.12

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21843>

d3d12: Track up to 16 contexts worth of batch references locally in bos

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21909>

d3d12: Unroll shader variant selection loop

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21909>

d3d12: Reduce gs variant key init cost; unnecessary validate gs calls

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21909>

d3d12: Use short circuit in shader key compare; update key hash

Move common key compare to the final step; change to short circuit from
memcmp.

Update key hash to treat varying pointers as uint64.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21909>

d3d12: Use context-level sampler_state array for filling shader keys

This significantly reduces the size of d3d12_shader_key

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21909>

d3d12: Don't unnecessarily recompute manual_depth_range

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21909>

d3d12: Track up to 16 contexts worth of pending barriers locally in bos

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21909>

zink: use res->queue to auto-handle queue transitions back to gfx queue

much simpler

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21733>

zink: remove redundant dmabuf_acquire setting

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21733>

zink: track current queue for resources

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21733>

ci/traces: disable nheko trace with zink since it flakes

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21976>

glsl: Fix codegen for constant ir_binop_{l,r}shift with mixed types

Fixes: 13106e10 ("glsl: Generate code for constant ir_binop_lshift and ir_binop_rshift expressions")

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17787>

zink: fix layer check for compressed format surface creation

this is a universal check, not a check based on mutable state

Fixes: 56108b411fd ("zink: verify compressed format layer count when creating surfaces")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21881>

aco: Always enable idxen for swizzled buffer access on GFX11.

This helps pass the mesh shader I/O tests.
Swizzled buffer addressing seems to be broken on GFX11
when the idxen bit is 0.

No Fossil DB changes on Rembrandt (GFX10.3).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21930>

aco: Disable MUBUF/MTBUF offsets when they are zero.

Fossil DB stats on Rembrandt (GFX10.3):

Totals from 1264 (0.94% of 134920) affected shaders:
VGPRs: 69504 -> 69336 (-0.24%)
CodeSize: 6885468 -> 6886224 (+0.01%); split: -0.02%, +0.03%
MaxWaves: 24632 -> 24670 (+0.15%)
Instrs: 1287027 -> 1287209 (+0.01%); split: -0.04%, +0.05%
Latency: 6830411 -> 6831165 (+0.01%); split: -0.06%, +0.07%
InvThroughput: 1220643 -> 1220438 (-0.02%); split: -0.04%, +0.02%
VClause: 24737 -> 24751 (+0.06%); split: -0.25%, +0.30%
SClause: 42774 -> 42911 (+0.32%); split: -0.13%, +0.45%
Copies: 75408 -> 75600 (+0.25%); split: -0.62%, +0.88%
PreVGPRs: 60544 -> 59809 (-1.21%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21930>

aco: Use zero for MUBUF/MTBUF when soffset is undefined.

No Fossil DB changes on Rembrandt (GFX10.3).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21930>

aco: Don't add soffset to swizzled MUBUF base.

No Fossil DB changes on Rembrandt (GFX10.3).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21930>

android/ci: raise error on script when not related to the tests

The cuttlefish-runner.sh script was failing before reaching the test
suite execution (which was not executing the complete test suite due to
the previous non-catched failures, and was erroneous passing) and we
were not catching that.
Add set -e so we can catch those.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21941>

android/ci: Fix call to adb

Call to adb should be made with ADB variable, following the pattern from
the script.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21941>

android/ci: fix removal of inexistent file

file libEGL_mesa.so doesn't exist and the rm command was failing,
replace by libGLES_mesa.so which exists.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21941>

radv: Add RT shader stage names for executable properties

Now that we use raygen shaders, we also need to support RT stages for
executable properties.

Fixes: f123d65e9f5 ("radv/rt: use prolog for raytracing shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21960>

Revert "zink/kopper: Add extra swapchain images for Venus"

This reverts commit 10f8240caf20382826015d99f368e073093880d7.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21963>

asahi: Extend batch tracking for explicit sync

Now that we have stub sync support in the submission API, we can
implement the batch tracking changes required to support an explicit
sync world. This excludes the UAPI-specific bits (command decoding and
status parsing).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21620>

asahi: Make agx_flush_resource reallocate non-shareable resources

It's not legal to share a resource that isn't PIPE_BIND_SHARED, but
flush_resource needs to prepare a resource for potential sharing.
Let's allocate a new resource and blit it over when this happens.

See also:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13154

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21620>

asahi: Support importing sync objects on BO export

When a BO is exported, implicit sync convention requires that writers
signal a fence on the object when complete. We already do this for BOs
that are *already* exported, but it is possible for a BO to be written
to, then exported for the first time.

Add a field to agx_bo to keep track of the current writer syncobj
handle. On first export, we use this to import it into the DMA-BUF.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21620>

asahi: Use a dynarray for writers

We don't want a writer hash table with persistent pointers to resources, because
the resources could be freed without the hash table being updated (even though
the underlying BO will not be freed until it's ready). To avoid the reference
count hell, do away with the pointer hash table and instead use a flat dynarray
for mapping BO (handles) to writer (batch indices).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21620>

radv: Wait for shader uploads asynchronously.

This introduces tracking of the required semaphore values in pipelines,
which is then propagated to cmd_buffers on bind. Each queue also keeps
track the maximum count it has waited for, so that we can avoid the waiting
overhead once all the shaders are loaded and referenced.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16271>

radv: Upload shaders to invisible VRAM on small BAR systems.

Following PAL's implementation, this patch avoids allocating shader code
buffers in BAR and use SDMA to upload them to invisible VRAM
directly.

For some games like HZD, shaders can take as much as 400MB, which exceeds
the non-resizable BAR size (256MB) and cause inconsistent spilling
behavior. The kernel will normally move these to invisible VRAM on its own,
but there are a few cases that it does not reliably happen. This patch does
the moving explicitly in the driver to ensure predictable results.

In this patch, we upload the shaders synchronously; so the shader will be
ready as soon as vkCreate*Pipeline returns. A following patch will make
this asynchronous and don't block until we see a use of the pipeline.

As a side effect, when SQTT is used we now store the shaders on a cacheable
buffer which would speed up writing the trace to the disk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16271>

radv: Introduce sdma_copy_buffer for GFX7+.

Helper salvaged from radeonsi (before SDMA removal).

This will be used for driver internal submissions to DMA shaders from GTT
to invisible VRAM.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16271>

radv: Use radeon_cmdbuf for sdma_copy_image.

For consistency with the sdma_copy_buffer helper that will be added next.

As a general justification, SDMA commands require little state tracking and
using radeon_cmdbuf makes it more suitable for driver internal use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16271>

Revert "CI: Disable Windows runners"

This reverts commit 023d7e860eeb148d0d245bcc49f5b66b9aeb8363.

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21932>

radv: Fix returning an expression from a void function

Fixes: d5de56bf ("radv: add RT shader args")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21932>

vulkan/wsi: Fix Windows build

The headless path doesn't build for Windows (yet, anyway).

Fixes: d4a2c0fc ("vulkan/wsi: add a headless swapchain implementation/option")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21932>

iris: implement TES distribution mode WA 22012785325

Set TEDMODE_RR_STRICT when TEEnable is set.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21899>

anv: implement TES distribution mode WA 22012785325

Set TEDMODE_RR_STRICT when TEEnable is set.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21899>

asahi: replace copies of .clang-format with symlinks

Avoid all the issues of having to keep them in sync, and few-enough
people (read: probably no-one ever) will be working on the asahi driver
from a Windows machine, so symlinks can be relied upon, especially for
something optional like automatic code formatting.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21951>

radv/rt: Don't upload the prolog twice.

radv_shader_create already calls radv_shader_binary_upload.

Fixes: 4b92a532859 ("radv: add radv_create_rt_prolog()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21945>

v3dv/ci: fix test name (`,Fail` is not part of the test name)

Fixes: a0bf0adade0b23f72d69 ("ci/broadcom: move rare failure to the flakes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21954>

zink/ci: update the radv expectations

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>

zink/ci: increase the parallelism of zink-radv-vangogh-valve

It current takes 17 minutes to run this job, which is above the 15
minutes target for Mesa CI. Let's increase the parallelism to reduce
exec time to closer to 13 minutes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>

radv/ci: reduce the parallelism for vkcts-vangogh

We are about to enable pre-merge testing for radv-zink on vangogh,
which would mean the steam decks would be used for the following jobs:

 * Mesa pre-merge CI:
  * zink: 3 (~12 minutes)
 * Mesa Post-merge CI:
   * vkcts: 4 (~30 minutes)
   * vkd3d: 1 (~5 minutes)
 * DXVK CI: 1 (takes ~4 hours)

This means we could have 9 jobs running at the same time on steam
decks, despite only having 6 available. By reducing the number of decks
allocated for VKCTS runs from 4 to 2, we get closer to the actual
availability, and since vkd3d is so short + DXVK CI runs so
infrequently, we should never have to wait for a deck for too long!

Unfortunately, with the change of parallelism, a known flake started
failing more consistently, so I added it to the flakes list.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>

meson: correct typo in comment

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21868>

virgl: Lower binding start into buffer indices

This requires that we limit the number of max combinded SSBOs to 31,
otherwisewe shaders that use SSBO binding points with higher values
will break on the host.

Fixes CTS:
  KHR-GL43.shader_storage_buffer_object.basic-atomic-case1
  KHR-GL43.shader_storage_buffer_object.basic-atomic-case2
  KHR-GL43.shader_storage_buffer_object.advanced-indirectAddressing-case2
  KHR-GL43.shader_storage_buffer_object.advanced-usage-case1
  KHR-GL43.shader_storage_buffer_object.advanced-usage-sync
  KHR-GL43.shader_storage_buffer_object.advanced-matrix

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>

ntt: add option to lower SSBO bindings to buffer index

When a shader uses SSBOs in various shader stages, then we have to track
the binding locations in order to be able to properly bind these SSBOs.

Therefore add a flag that enables adding the start index of the bindings to
the SSBO index.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>

virgl: Don't try to do re-alloc or readback by transfer for blob resources

Blob resources are mapped directly, no need to copy data around, and
in any case, neither the resource nor the transfer info will have an
IOV attached to it, so the transfer would result error out on the host
anyway.

In addition, blob resources should not use re-allocation.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>

virgl: Enable AMD_vertex_shader_(layer|viewport_index) when host supports it

This increase the number of cases when the texture upload from buffer
can use the PBO upload code path.

v2: Fix logic combination (Corentin)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>

anv: use vk_get_physical_device_features

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>

panvk: Use vk_get_physical_device_features

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>

vulkan: use vk_features for vk_device::enabled_features

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>

vulkan: add hepler for vkGetPhysicalDeviceFeatures2

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>

vulkan: delete trailing namespace

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>

vulkan: tidy up vk_physical_device_features

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>

vulkan: relocate rmv to its correct home

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>

radeonsi: monolithic TCS emit tessfactor in nir directly

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>

radeonsi: lower nir_load_ring_tess_factors_offset_amd

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>

ac/llvm,radeonsi: lower nir_load_ring_tess_factors_amd

No one implement this intrinsic in llvm, so remove the
llvm entry too.

This will be used in TCS nir tess factor write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>

ac/nir: handle tess factor output missing case

tcs_tess_lvl_(in|out)_loc may be not set if user miss tess
factor output.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>

ac/nir: init tess factor location with IO remap

Radeonsi is going to use nir tess factor write, so need to
remap tess factor location.

RADV set tess factor driver location to be 0 and 1 in
get_linked_variable_location(). While radeonsi also set them
to be 0 and 1 in st->map_io aka. si_shader_io_get_unique_index_patch().

We could just set them to be 0 and 1 at the beginning of
ac_nir_lower_hs_outputs_to_mem(), but in order to keep the
location map at the same place, we still do this in
lower_hs_output_store().

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>

ac/nir: tcs write tess factor support pass by reg

For radeonsi usage.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>

ac/nir: move store_var_components to common place

It will be shared by other nir lowering too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>

panfrost: Don't round up Midgard polygon list BOs

Rounding up the polygon list BO can waste large amounts of memory. In a common
case I observed, it rounded up 11MB to 16MB, wasting 5MB. That adds up quickly
across processes, especially on the 2GB machines.

This only applies to Midgard. On Bifrost and newer, the driver does not
explicitly allocate this data structure. Cc stable because this rounding is
incorrect and the increase in RAM usage can cause real problems (especially
given how slow the shrinker is).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21831>

glsl: allow 64-bit integer on RHS of shift

Fixes: 9ba9a7f854dd ("glsl: Add 64-bit integer support to some operations.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6862

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21919>

aco: remove aco::rt_stack variable

Since we initialize scratch in the RT proglog,
there is no need for this variable anymore.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv/rt: use prolog for raytracing shaders

Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv/rt: Add shader config combination/postprocessing utils

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv: Emit RT shader VA user SGPR

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv: compile rt_prolog

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv: add radv_create_rt_prolog()

Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

aco: implement select_rt_prolog()

Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

aco: create hw_init_scratch() function for p_init_scratch lowering

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

aco: implement load_ray_launch_{id|size}

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

aco: move rt_dynamic_callable_stack_base_amd to VGPR

In future, we will use a VGPR arg for that between RT stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

aco: don't set private_segment_buffer/scratch_offset on GFX9+

It is unused. Also don't initialize scratch in raytracing stages as it gets
initialized in the prolog shader.

Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

aco: add RT stage enums

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv: add RT shader handling to radv_postprocess_config

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv: add RT stages to radv_get_shader_name()

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv: handle RT stages in radv_nir_shader_info_pass()

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

radv: add RT shader args

Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

mesa: add gl_shader_stage_is_rt()

to indicate raytracing shader stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>

driconf: Work around incorrect GI discard/invalidate

Genshin Impact does a depth+stencil invalidate (or discard, not sure
which entrypoint they are using) and then proceeds to do draws with
depth test enabled.  For IMRs (or freedreno in sysmem mode) this is no
problem.  But for tilers that use this as a hint that they can skip the
z/s tile load, it is.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21916>

driconf: Add ignore_discard_framebuffer option

Some apps use glDiscardFramebuffer()/glInvalidateFramebuffer() when they
only kidding.  Add a knob to disable that.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21916>

mesa: Rework discard_framebuffer()

Decouple the logic turning API attachment enums into gl_buffer_index.
This will make it easier to re-use discard_attachments() internally (See
!21910)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21916>

aco_validate: allow for wave32 in p_dual_src_export_gfx11

Fixes RADV_PERFTEST=pswave32

Fixes: bb90d29660b ("aco: add p_dual_src_export_gfx11 for dual source blending on GFX11")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21934>

intel: use generated helpers for Wa_1409433168/Wa_16011107343

HSD 1306463417 is a hardware defect.  The originating software
workaround for the issue is Wa_1409433168.  Convert all references to
the software workaround number, and use generated helpers instead of
GFX comparisons.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21914>

ci/turnip: Move some more of the 1.3.5 new xfails under links.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21915>

ci/turnip: Disable dEQP-VK.image.queue_transfer.* for now.

We're waiting on the upstream CTS fix to land.  Until then, quiet the spam
in #freedreno-ci to see if we have any other flakes we need to be managing
right now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21915>

ci/turnip: Clear out stale xfails.

These were all fixed in the CTS, but missed from removal due to fractional runs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21915>

turnip: Don't push inline uniform buffer contents outside constlen.

This would apparently lead to trying to load from this inline uniform
buffer in later submits.

Fixes: 37cde2c63483 ("tu: Rewrite inline uniform implementation")
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8219
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21915>

aux/trace: delete GALLIUM_TRACE_NIR log message

this is not only annoying, it breaks trace xml output

cc: mesa-stable

Acked-by: Simon Zeni <simon@bl4ckb0ne.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21609>