Revert "iris: Avoid abort() if kernel can't allocate memory"

This reverts commit f9d8d9acbb6a620684fb4dac4affe25816587d92.

Now ENOMEM is handled in submit_batch(), we don't need to check it for
resetting anymore.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20449>

iris: Retry DRM_IOCTL_I915_GEM_EXECBUFFER2 on ENOMEM

We are seeing endless DRM_IOCTL_SYNCOBJ_WAIT ioctl when system memory is
under pressured.

Commit f9d8d9acbb6a ("iris: Avoid abort() if kernel can't allocate
memory") avoids the abort() on ENOMEM by resetting the batch. However,
when there's an ongoing OpenGL query, resetting the batch will make the
snapshots_landed never be flipped, so iris_get_query_result() gets stuck
in the while loop forever.

Since there's no guarantee that the next batch after resetting won't hit
ENOMEM, so instead of resetting the batch, be patient and wait until kernel has
enough memory. Once the batch is submiited and snapshots_landed gets
flipped, iris_get_query_result() can proceed normally.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6851
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20449>

intel/compiler: add comment about workaround on simd width

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21619>

radv: use new EVENT_WRITE_ZPASS packet3 on GFX11

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21621>

radv: ignore alpha_is_on_msb on GFX11 because the hw ignores it

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21621>

nir/lower_mediump: don't use fp16 for constants if the result is denormal

Image stores are not required to preserve denorms.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21622>

aco: use v_fma_mix_f32 for v_fma_f32 with 2 fp16 representable, different literals

We can pack two fp16 literals into one 32bit literal and use opsel to select
the correct value. Note that LLVM currently disassembles these instructions
incorrectly.

Foz-DB Navi21:
Totals from 13365 (9.91% of 134913) affected shaders:
VGPRs: 840880 -> 840016 (-0.10%); split: -0.11%, +0.01%
SpillSGPRs: 724 -> 722 (-0.28%)
CodeSize: 82439364 -> 82451336 (+0.01%); split: -0.06%, +0.08%
MaxWaves: 244858 -> 244980 (+0.05%)
Instrs: 15265976 -> 15247201 (-0.12%); split: -0.13%, +0.01%
Latency: 223316180 -> 223272495 (-0.02%); split: -0.03%, +0.02%
InvThroughput: 41981375 -> 41969917 (-0.03%); split: -0.04%, +0.01%
VClause: 266775 -> 266558 (-0.08%); split: -0.14%, +0.06%
SClause: 646602 -> 645996 (-0.09%); split: -0.16%, +0.07%
Copies: 794703 -> 776075 (-2.34%); split: -2.46%, +0.12%
Branches: 296317 -> 296316 (-0.00%)
PreSGPRs: 658796 -> 656479 (-0.35%); split: -0.35%, +0.00%
PreVGPRs: 744014 -> 743679 (-0.05%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20587>

aco: mark mad definition as precise if the mul/add were precise

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20587>

amd,ac/rgp: fix SQTT memory types

This crashed on Steam Deck because the memory type is LPDDR5 and it
wasn't not handled in the switch. It seems the kernel changed the
memory type returned for VanGogh because it used to work.

Fixes: aef7ea868fe ("ac/gpu_info: handle LPDDR4 and 5 in ac_memory_ops_per_clock")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21627>

gallivm: Add some notes about other invocation_0_must_be_active usages.

So that the next person trying to cut down LLVM compile times doesn't trip
over this.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21142>

gallivm: Use first_active_invocation for scalar SSBO loads.

Again, this should reduce the complexity of the LLVM IR we emit in some
cases.  We don't use it for shared loads, due to the noted corner case.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21142>

gallivm: Use first_active_invocation for ubo/kernel memory loads.

If we're just loading memory, we can take the scalar offset_is_uniform
paths even the first active invocation is nonzero, saving a bunch of
looping and bounds checking for per-element loads.  And, if we don't have
an active invocation, doing the load for element 0 (which is
bounds-checked to return 0 if element 0 had a bad value in it) before
throwing away the result is still better than doing bounds-checked loads
for each element before throwing away the result.

dEQP-VK.ubo.random.16bit.scalar.92 goes from 16.5 to 14.0 seconds.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21142>

gallivm: Return 0 for first active invocation when no invocations are active.

gallivm doesn't actuially jump across branches where no invocations are
active, so my previous assertion about the exec mask being nonzero was
incorrect.  This means that we'll always use a defined invocation for the
various LLVMBuildExtractElements using the result value, which is an
improvement over my even the code before my cttz change that would use
undefined values for the element to be extracted.

Fixes: 8c2493d041c4 ("gallivm: Use cttz instead of a loop for first_active_invocation().")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21142>

ci/radv: remove dEQP-VK.image.sample_texture.* fails/flakes

They were fixed since commit 11b2a063bf1 ("vulkan: Unconditionally add
barriers for missing external subpass deps").

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21616>

intel/dev: generate helpers to identify platform workarounds

Workarounds for defects in Intel silicon have been manually
implemented:

 - consult defect database for the current platform

 - add workaround code behind platform ifdef or devinfo->ver checks

Some bugs have occurred due to the manual process.  Typical failure
modes:

 - defect database is updated after a platform is enabled

 - version checks are overly broad (eg gfx11+) for defects that were
   fixed (eg in gfx12)

 - version checks are too narrow for defects that were extended to
   subsequent platforms.

 - missed workarounds

This commit automates workaround handling:

 - Internal automation queries the defect database to collate and
   summarize defect documentation in json.

 - mesa_defs.json describes all public defects and impacted platforms.
   Defects which are extended to subsequent platforms are listed under
   the original defect.

 - gen_wa_helpers.py generates workaround helpers to be called
   in place of version checks:

   - NEEDS_WORKAROUND_{ID} provides a compile time check suitable for
     use in genX routines.

   - intel_device_info_needs_wa() provides a more precise runtime
     check, differentiating platforms within a generation and
     platform steppings.

Internal automation will generate new mesa_defs.json as needed.
Workarounds enabled with these helpers will apply correctly based on
updated information in Intel's defect database.

Reviewed-by: Dylan Baker <dylan@pnwbakers>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>

util: add macro to support gcc/clang poison

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>

intel/dev: create a helper dependency for libintel_dev

This ensures that users of libintel_dev.a won't be compiled until
include files are generated, and that they are recompiled when the
header changes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>

glthread: fix a perf regression due to draw_always_async flag, fix DrawIndirect

Performance regressed by 31% in one VP2020/Creo subtest because
the draw_always_async flag wasn't implemented correctly. Remove it
instead of fixing it.

While removing it, I noticed that our DrawIndirect async conditions
were incorrect. I fixed them.

Fixes: 3b897719e632a165f - glthread: add ctx->GLThread.draw_always_async to simplify draw checking

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21566>

glx: fix indirect initialization crash

Fixes: b090246a ("glx: Only compute client GL extensions for indirect contexts")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8393

Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21591>

d3d12: Use memcmp for full tcs/gs variant keys

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>

d3d12: Cache varying info to reduce compare/copy cost

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>

d3d12: Compare shader key common parts with memcmp, instead of if's

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>

d3d12: Compare shader keys with union-encompassing fields all at once

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>

d3d12: Compare shader keys with a switch, instead of cascading if's

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>

anv: use the parameter passed to the macro

The two points calling this macro pass dyn->rs.provoking_vertex to it,
which is why it works, but it's cleaner to use the parameter instead.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21613>

intel/mi: use 64bit constant for bitshift

Coverity complains that we could end up rolling over on a 32bit
platform, which isn't really true because of the assertion, but there's
also no harm in ensuring that we have exactly the same behavior for both
32 bit and 64 bit platforms.

CID: 1515989
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21572>

venus: fix VK_EXT_image_view_min_lod feature query

Fixes: 8b810985196 ("venus: enable VK_EXT_image_view_min_lod")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21617>

pvr: Setup SPM background object

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21575>

glsl: remove do_copy_propagation_elements() optimisation pass

Since 13b859de do_copy_propagation_elements() has a flaw where
the time it takes to complete grows exponentially slowers as the number
of nested loops increases. It can also hurt rather than help verses
just letting NIR optimise the code. So if the NIR linker is enabled we
let it handle it instead.

shader-db results Iris (BDW):

total instructions in shared programs: 11177181 -> 11199739 (0.20%)
instructions in affected programs: 119424 -> 141982 (18.89%)
helped: 109
HURT: 65
total cycles in shared programs: 368946819 -> 372277173 (0.90%)
cycles in affected programs: 116539428 -> 119869782 (2.86%)

total spills in shared programs: 3983 -> 8785 (120.56%)
spills in affected programs: 2072 -> 6874 (231.76%)
helped: 0
HURT: 6

total fills in shared programs: 2016 -> 6068 (200.99%)
fills in affected programs: 230 -> 4282 (1761.74%)
helped: 0
HURT: 6

LOST:   85
GAINED: 77

freedreno results:

total instructions in shared programs: 11011122 -> 11011620 (<.01%)
instructions in affected programs: 939829 -> 940327 (0.05%)
total full in shared programs: 762725 -> 762674 (<.01%)
full in affected programs: 1096 -> 1045 (-4.65%)
total constlen in shared programs: 1772092 -> 1771596 (-0.03%)
constlen in affected programs: 2780 -> 2284 (-17.84%)
total stp in shared programs: 4040 -> 4058 (0.45%)
stp in affected programs: 3656 -> 3674 (0.49%)
total ldp in shared programs: 2160 -> 2178 (0.83%)
ldp in affected programs: 1748 -> 1766 (1.03%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/13.shader_test CL: 1231 -> 1234 (0.24%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/13.shader_test CL: 1231 -> 1234 (0.24%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/15.shader_test CL: 453 -> 456 (0.66%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/15.shader_test CL: 453 -> 456 (0.66%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/17.shader_test CL: 144 -> 147 (2.08%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/17.shader_test CL: 144 -> 147 (2.08%)

however, those stp counts are misleading -- gfxbench gl-5-normal actually
gets its scratch (ldp/stp) stored as 16 bits instead of 32 thanks to
better NIR copy prop, and the result is 2.64398% +/- 0.0991923% perf
improvement!

i915 results:

total instructions in shared programs: 510528 -> 510489 (<.01%)
instructions in affected programs: 3303 -> 3264 (-1.18%)
total tex_indirect in shared programs: 16708 -> 16717 (0.05%)
tex_indirect in affected programs: 134 -> 143 (6.72%)
total temps in shared programs: 30181 -> 30169 (-0.04%)
temps in affected programs: 1268 -> 1256 (-0.95%)
LOST:   0
GAINED: 1

i915 highlights:
instructions HURT:   shaders/closed/steam/legend-of-grimrock/47.shader_test FS: 141 -> 144 (2.13%)
instructions HURT:   shaders/closed/steam/steamworld-dig/22.shader_test FS: 84 -> 108 (28.57%)
temps HURT:   shaders/closed/steam/left-4-dead-2/medium/3682.shader_test FS: 7 -> 13 (85.71%)

r300 results:

total instructions in shared programs: 1340439 -> 1340845 (0.03%)
instructions in affected programs: 32354 -> 32760 (1.25%)
total temps in shared programs: 179394 -> 179329 (-0.04%)
temps in affected programs: 1505 -> 1440 (-4.32%)
total consts in shared programs: 1177742 -> 1177885 (0.01%)
consts in affected programs: 1107 -> 1250 (12.92%)
total lits in shared programs: 24992 -> 25019 (0.11%)
lits in affected programs: 138 -> 165 (19.57%)
instructions HURT:   shaders/closed/steam/legend-of-grimrock/26.shader_test FS: 47 -> 52 (10.64%)
instructions HURT:   shaders/closed/steam/sanctum-2/6072.shader_test FS: 43 -> 48 (11.63%)
instructions HURT:   shaders/closed/steam/champions-of-regnum/2378.shader_test VS: 35 -> 40 (14.29%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13288>

nir/split_64bit_vec3_and_vec4: Handle 64-bit matrix types.

The offset handling should already work for flattening to our split vars,
just need to make sure we have enough (or any!) array elements.

Fixes: #7154
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13288>

spirv: Add skip_os_break_in_debug_build option to use in unit tests

When running in the CI environment, instead of crashing the test
binary, it is preferable to just fail gracefully (in this case return
a NULL shader) like is done in release mode, so other tests continue
to be executed.

For convenience add a variable break_on_failure to the test so the
breaking behavior can be re-enable in individual tests when debugging.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>

spirv/tests: Add some basic control flow tests

The DISABLED test currently fails parsing.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>

spirv/tests: Parametrize stage in get_nir() helper

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>

spirv/tests: Add script to generate C array from SPIR-V source

This is useful for generating the C code to embed the SPIR-V
when adding a new test.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>

spirv/tests: Subclass spirv_test helper to namespace the tests

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>

ci: implement unified sections

in after_script, variable $SCRIPTS_DIR is lost

Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20272>

ci: alpine: install bash and coreutils for date -d

bash is needed for consistency.
coreutils is needed for `date -d`.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20272>

ci/alpine: keep the curl inside the image

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20272>

nir/opt_algebraic: add patterns for iand/ior of feq/fneu with 0

Foz-DB Navi21:
Totals from 1245 (0.92% of 134913) affected shaders:
VGPRs: 66232 -> 66248 (+0.02%); split: -0.01%, +0.04%
CodeSize: 5874976 -> 5868168 (-0.12%); split: -0.17%, +0.05%
MaxWaves: 25278 -> 25274 (-0.02%); split: +0.01%, -0.02%
Instrs: 1087502 -> 1085267 (-0.21%); split: -0.21%, +0.00%
Latency: 6531489 -> 6531672 (+0.00%); split: -0.04%, +0.05%
InvThroughput: 1531774 -> 1532327 (+0.04%); split: -0.02%, +0.05%
VClause: 22218 -> 22202 (-0.07%); split: -0.08%, +0.00%
SClause: 45906 -> 45873 (-0.07%); split: -0.08%, +0.01%
Copies: 64004 -> 64102 (+0.15%); split: -0.24%, +0.39%
Branches: 21529 -> 21534 (+0.02%); split: -0.00%, +0.03%
PreSGPRs: 51936 -> 51850 (-0.17%)
PreVGPRs: 55393 -> 55398 (+0.01%); split: -0.02%, +0.03%

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21576>

radv: only expose EXT_pipeline_library_group_handles if RT is enabled

VK_EXT_pipeline_library_group_handles requires
VK_KHR_ray_tracing_pipeline to be enabled.

Fixes dEQP-VK.info.device_extensions.

Fixes: ed768337050 ("radv: Implement & expose VK_EXT_pipeline_library_group_handles.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21618>

spirv: Don't specify nir_var_uniform or nir_var_mem_ubo in barriers

These are constant read-only data and don't need to be synchronized.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21517>

iris: Fix to release BO immediately if not busy

Currently the iris driver is adding the buffer objects to zombie list
without checking if it is busy or not. It checks for it after 1 second
which adds delay to buffer release.

This fix checks if the bo is busy or not before adding it to zombie list.

Without this fix, the applications expecting immediate buffer release would
fail.

The fix is identified while debugging below android cts tests:
android.graphics.cts.BitmapTest#testDrawingHardwareBitmapNotLeaking
android.graphics.cts.BitmapTest#testHardwareBitmapNotLeaking

Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21460>

genxml: fix border color offset field on Gfx12+

I wonder if the docs are correct for Gfx11 because this is the
generation that gave us the Bindless Sampler Heap of 4Gb. So it would
make sense that the border colors can also be placed anywhere in that
4Gb heap.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21600>

genxml: Fix STATE_BASE_ADDRESS::BindlessSurfaceStateSize field size

BSpec 44507

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21600>

radv: add video format support to format probing.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21457>

radv: Replace radv_trap_handler_shader with radv_shader.

Now that the upload memory is tied to the shader itself, the trap handler
shader no longer needs an additional wrapper.

This is a cleanup to ease introduction of a new shader uploading code path.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21541>

anv: always pick graphics queue to execute prime blits on.

This will change when we get transfer queues but this should avoid
video queues being picked by accident.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21204>

asahi: Flush USC caches on the first draw

It seems that when batches are submitted back to back, the USC can
retain cache contents between them. This causes a problem when the CPU
updates a VBO between batches, since some of those updates might not be
visible to the USC.

Looks like the VDM barrier command with one magic bit set fixes this, so
let's try that.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21538>

asahi: Identify USC cache invalidate

Signed-off-by: Asahi Lina <lina@asahilina.net>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21538>

asahi: Add readonly BO flag

Signed-off-by: Asahi Lina <lina@asahilina.net>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21538>

asahi: Add BO_SHAREABLE flag

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21538>

anv: remove more Gfx7 code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21599>

iris: fix Wa_16011107343 for Gfx12

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: df9f71d79574 ("iris: emit 3DSTATE_HS for each primitive on gfx12")
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21605>

anv: fixup Wa_16011107343 for Gfx12 only

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 75968398f37c ("anv: emit 3DSTATE_HS for each primitive on gfx12")
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21605>

ci: Reuse MESA_CI_PERFORMANCE_ENABLED in performance-rules

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21492>

ci: Use workflow to make CI aware of performance jobs

With the workflow keyword, we can have more control over how pipelines
are created.

One of the features is to set a variable for the entire pipeline
depending on the rule. These variables would be available for all jobs
manifest and can be used inside job rules, for example.

We can use that to set a variable to enable performance jobs in the
pipeline, both at the YAML and script levels.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21492>

ci: Use release builds in perf jobs

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21492>

ci: Create debian-arm64-release job

To be able to upload the mesa's release build for arm64 to S3 and use it
in performance jobs.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21492>

ci: Upload debian-release artifact to S3

This will enable performance jobs to use release versions for
performance tracking, since they download the artifacts from S3.

We were using debugoptimized versions, which are not the most performant
ones.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21492>

llvmpipe: fix compute address bits to return native pointer size.

On 32-bit systems llvm will only be dealing with 32-bit ptrs

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21601>

pvr: Don't update fragment signal sync when fragment stage is disabled

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21577>

pvr: Clear wait syncs after job submission

Avoids the fw having to process redundant waits.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21577>

pvr: Enable threaded submit when supported

Adds a winsys feature flag to enable threaded submit.

Currently pvrsrvkm can't support threaded submit as pvrsrvkm syncs don't
support VK_SYNC_FEATURE_WAIT_PENDING.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21577>

pvr: Add support for VK_KHR_timeline_semaphore

pvrsrvkm will run with VK_DEVICE_TIMELINE_MODE_EMULATED and
powervr will run with VK_DEVICE_TIMELINE_MODE_ASSISTED.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21577>

pvr: Use common queue submit implementation

A simplification of the synchronization code is also undertaken as part
of this commit to account for the implicit guarantee the FW gives the driver
that jobs submitted to the same context will be run in submission order.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21577>

radv: Only init geometry infos if RRA is enabled

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21532>

radv: Move header and geometry info init into separate functions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21532>

anv: halve the push constants space in mesh pipelines

It's only used by fragment shaders, so halving it matches the size
used in the most optimal primitive pipeline (VS + FS).

This change frees some URB space for mesh and task shaders and as
a result improves vk_meshlet_cadscene performance by up to 2%,
depending on the model.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21559>

iris: consider bufmgr creation to have failed if `dup`ing of the fd fails

Coverity points out that we can pass a negative value to `close()`,
which results in an unchecked error. While this is technically true, it
really isn't a problem as `close()` is speced to return -1 in that case
(which we ignore). However, what is true is that if we fail to dup the
fd (the only case where we could end up with a negative value), then
we're in an unrecoverable error state anyway, and should go to the error
cleanup code.

CID: 1521539
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21568>

ci/freedreno: add flaking KHR-GL45.buffer_storage.map_persistent_flush

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21598>

intel/vulkan: add missing dependency on generated headers

Adding correct dependencies prevents occasional build flakes with parallel builds.

```
FAILED: src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o
ccache cc -Isrc/intel/vulkan/libanv_common.a.p -Isrc/intel/vulkan -I../src/intel/vulkan -Iinclude -I../include -Isrc -I../src -Isrc/mapi -I../src/mapi -Isrc/mesa -I../src/mesa -I../src/gallium/include -Isrc/intel -I../src/intel -Isrc/compiler -I../src/compiler -Isrc/compiler/nir -I../src/compiler/nir -Isrc/vulkan/util -I../src/vulkan/util -Isrc/vulkan/runtime -I../src/vulkan/runtime -Isrc/vulkan/wsi -I../src/vulkan/wsi -Isrc/intel/genxml -Isrc/intel/vulkan/shaders -Isrc/intel/ds -I/usr/local/include -I/usr/local/include/libdrm -fvisibility=hidden -fdiagnostics-color=always -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -std=c11 -O2 -g -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS '-DPACKAGE_VERSION="23.1.0-devel"' '-DPACKAGE_BUGREPORT="https://gitlab.freedesktop.org/mesa/mesa/-/issues"' -DHAVE_OPENGL=1 -DHAVE_OPENGL_ES_1=1 -DHAVE_OPENGL_ES_2=1 -DHAVE_SWRAST -DHAVE_VIRGL -DHAVE_RADEONSI -DHAVE_ZINK -DHAVE_CROCUS -DHAVE_IRIS -DHAVE_I915 -DVIDEO_CODEC_VC1DEC=1 -DVIDEO_CODEC_H264DEC=1 -DVIDEO_CODEC_H264ENC=1 -DVIDEO_CODEC_H265DEC=1 -DVIDEO_CODEC_H265ENC=1 -DHAVE_X11_PLATFORM -DHAVE_SURFACELESS_PLATFORM -DHAVE_DRM_PLATFORM -DHAVE_XCB_PLATFORM -DHAVE_ST_VDPAU -DENABLE_ST_OMX_BELLAGIO=0 -DENABLE_ST_OMX_TIZONIA=0 -DGLX_INDIRECT_RENDERING -DGLX_DIRECT_RENDERING -DGLX_USE_DRM -DALLOW_KCMP -DENABLE_SHADER_CACHE -DHAVE___BUILTIN_BSWAP32 -DHAVE___BUILTIN_BSWAP64 -DHAVE___BUILTIN_CLZ -DHAVE___BUILTIN_CLZLL -DHAVE___BUILTIN_CTZ -DHAVE___BUILTIN_EXPECT -DHAVE___BUILTIN_FFS -DHAVE___BUILTIN_FFSLL -DHAVE___BUILTIN_POPCOUNT -DHAVE___BUILTIN_POPCOUNTLL -DHAVE___BUILTIN_UNREACHABLE -DHAVE___BUILTIN_TYPES_COMPATIBLE_P -DHAVE_FUNC_ATTRIBUTE_CONST -DHAVE_FUNC_ATTRIBUTE_FLATTEN -DHAVE_FUNC_ATTRIBUTE_MALLOC -DHAVE_FUNC_ATTRIBUTE_PURE -DHAVE_FUNC_ATTRIBUTE_UNUSED -DHAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT -DHAVE_FUNC_ATTRIBUTE_WEAK -DHAVE_FUNC_ATTRIBUTE_FORMAT -DHAVE_FUNC_ATTRIBUTE_PACKED -DHAVE_FUNC_ATTRIBUTE_RETURNS_NONNULL -DHAVE_FUNC_ATTRIBUTE_ALIAS -DHAVE_FUNC_ATTRIBUTE_NORETURN -DHAVE_FUNC_ATTRIBUTE_VISIBILITY -DHAVE_UINT128 -DHAVE_REALLOCARRAY -D_GNU_SOURCE -DUSE_SSE41 -DUSE_GCC_ATOMIC_BUILTINS -DUSE_X86_64_ASM -DMAJOR_IN_SYSMACROS -DHAS_SCHED_H -DHAS_SCHED_GETAFFINITY -DHAVE_LINUX_FUTEX_H -DHAVE_ENDIAN_H -DHAVE_DLFCN_H -DHAVE_SYS_SHM_H -DHAVE_CET_H -DHAVE_SYS_INOTIFY_H -DHAVE_STRTOF -DHAVE_MKOSTEMP -DHAVE_TIMESPEC_GET -DHAVE_MEMFD_CREATE -DHAVE_RANDOM_R -DHAVE_FLOCK -DHAVE_STRTOK_R -DHAVE_GETRANDOM -DHAVE_GNU_QSORT_R -DHAVE_STRUCT_TIMESPEC -DHAVE_PROGRAM_INVOCATION_NAME -DHAVE_ISSIGNALING -DHAVE_POSIX_MEMALIGN -DHAVE_DIRENT_D_TYPE -DHAVE_STRTOD_L -DHAVE_DLADDR -DHAVE_DL_ITERATE_PHDR -DSUPPORT_INTEL_INTEGRATED_GPUS -DHAVE_ZLIB -DHAVE_COMPRESSION -DHAVE_PTHREAD -DHAVE_PTHREAD_SETAFFINITY -DHAVE_LIBDRM -DLLVM_AVAILABLE '-DMESA_LLVM_VERSION_STRING="13.0.1"' -DLLVM_IS_SHARED=1 -DDRAW_LLVM_AVAILABLE -DUSE_LIBELF -DMESA_EXECMEM -DHAVE_LIBUNWIND -DHAVE_OPENMP -DHAVE_DRI -DHAVE_DRI2 -DHAVE_DRI3 -DHAVE_DRI3_MODIFIERS -DHAVE_DRISW_KMS -DHAVE_PERFETTO -mtls-dialect=gnu2 -Werror=implicit-function-declaration -Werror=missing-prototypes -Werror=return-type -Werror=empty-body -Werror=incompatible-pointer-types -Werror=int-conversion -Wimplicit-fallthrough -Wmisleading-indentation -Wno-missing-field-initializers -Wno-format-truncation -Wno-nonnull-compare -fno-math-errno -fno-trapping-math -fno-common -Wno-unused-function -Werror=format -Wformat-security -ffunction-sections -fdata-sections -fPIC -DVK_USE_PLATFORM_XCB_KHR -DVK_USE_PLATFORM_XLIB_KHR -DVK_USE_PLATFORM_DISPLAY_KHR -DVK_USE_PLATFORM_XLIB_XRANDR_EXT -Wno-override-init -DANV_SUPPORT_RT=0 -MD -MQ src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o -MF src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o.d -o src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o -c ../src/intel/vulkan/anv_generated_indirect_draws.c
../src/intel/vulkan/anv_generated_indirect_draws.c:34:10: fatal error: shaders/generated_draws_spv.h: No such file or directory
   34 | #include "shaders/generated_draws_spv.h"
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
```

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21592>

radv: fix draw calls with 0-sized index buffers and robustness on NAVI10

The correct workaround is to bind an internal index buffer to handle
robustness2 correctly.

Fixes dEQP-VK.robustness.index_access.* in CTS 1.3.5.0 on NAVI10.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21471>

pvr: replace nop binary shader with run-time compiled shader

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21536>

meson: allow checking for null pointers even if they're supposed to be non-null

    ../src/c11/impl/time.c: In function 'timespec_get':
    ../src/c11/impl/time.c:71:8: error: 'nonnull' argument 'ts' compared to NULL [-Werror=nonnull-compare]
       71 |     if (!ts)
          |        ^
    cc1: all warnings being treated as errors

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21558>

v3dv: Enable (leased) direct display extensions.

Enable support for the following extensions, which are already supported
by the driver and shared wsi code, and were just missing enables inside
v3dv_device:

VK_EXT_direct_mode_display, VK_EXT_acquire_drm_display,
VK_EXT_acquire_xlib_display.

Successfully tested on RPi 400, RaspberryPi OS 11, with X11 RandR output
leasing to lease a RandR output and use it for direct display mode.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21529>

pvr: initialise size for placeholder "zeroed" shaders

Fixes an assert() in pvr_gpu_upload_usc().

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21537>

glapi/meson: drop duplicate line in deps

Fixes: 0842bc879b34414de54b ("meson: wire the new generator for es1 and es2")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21562>

radv: fix flushing non-coherent images in EndCommandBuffer()

The condition was inverted.

This doesn't fix anything known.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21549>

radv: fix flushing non-coherent images inside secondaries on GFX9+

Fixes
dEQP-VK.draw.dynamic_rendering.complete_secondary_cmd_buff.multi_draw.mosaic.*
on VEGA10 (related to the use of HTILE).

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21549>

glsl: align definition of _mesa_problem with the one in main/error.h

The ctx pointer not used by that function anyway, so const'ing it makes
no difference.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21557>

util: rzalloc and free hash_table_u64

Otherwise we're prone to leaking the table itself, since it's not freed
in the destroy function

CID: 1516552
fixes: 6649b840c34016b4753e69d4513a8d09da9febb2
       ("mesa/util: add a hash table wrapper which support 64-bit keys")

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21499>

anv: emit 3DSTATE_HS for each primitive on gfx12

This is Wa_16011107343, same workaround as commit 880a3efe6c2
but for gfx12.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21551>

iris: emit 3DSTATE_HS for each primitive on gfx12

This is Wa_16011107343, same workaround as commit a043ae8e249
but for gfx12.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21551>

aco: only ls and ps use store output now

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21435>

ac/llvm: only init outputs when fragment shader for radv

LS pass output to TCS by reg is not enabled when LLVM.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21435>

radeonsi: only init llvm output when needed.

These are the cases which still uses nir_store_output.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21435>

glsl: Move lower_vector_insert to GLSL-to-NIR.

We already have a nir_builder equivalent for generating this code, just
use that instead of doing it in GLSL.

No change on r300 shader-db.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21476>

panfrost/midgard: Drop redundant arg to emit_explicit_constant.

Every caller passed the same value twice.  Just reuse it?

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21476>

panfrost/midgard: Fix handling of csel with a vector constant condition.

If it's not all true or all false, then you'll have a csel with a vector
constant, and the backend failed to translate appropriately.  Expand the
constant to fix it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21476>

venus: fix device memory export alloc info

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: fix external image creation

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: simplify support for non-AHB external images

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: simplify ahb image creation

Those excessive asserts are only useful when bringing up Android.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: refactor image create info pnext tracking

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: remove redundant abstractions for wsi struct search

Doing that won't avoid linking wsi headers, and in fact we have already
included both android and common wsi headers. For swapchain info, it's
currently disabled by the swapchain spec version advertised on Android.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: fix external buffer creation

Move buffer create info scrub into core venus.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: distinguish external memory from mappable memory support

Mappable memory support is a must for Venus core, but the support of
such can be transparent to the driver. Thus the renderer external memory
type won't expose opaque fd type.

External memory over vtest can be exposed and the wsi support on top can
be made explicit as long as masking out the importable bit.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: tighten up the sync fd requirements for Android wsi

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: refactor sync fd fence and sempahore features

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>

venus: clean up globalFencing

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21379>