review.tizen.org Git - platform/upstream/mesa.git/log

intel: Fix crashes for importing drm buffer

image_aspect_to_binding() converts aspect to index by subrracting
VK_IMAGE_ASPECT_MEMORY_PLANE_0_BIT_EXT, however these enum values
are bitfields, not consecutive numbers, so comparing and subtracting
them won't work.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20269>
(cherry picked from commit 7642f3b99c8b17c7cfa1f140c65ce82e7dbcea2b)

anv: fixup descriptor copies

I did not properly understood that we cannot access the views written
to the descriptor sets because they might have been destroyed after
the write operation and the copy operation is allowed to copy what is
invalid data. The shader just can't access it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 03e1e19246 ("anv: Refactor descriptor copy")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20222>
(cherry picked from commit a0991c7c794da39bf1a4b5fb5484b77afde200cc)

hasvk: pipelineStageCreationFeedbackCount is allowed to be 0

Fixes: 6601e5d6fc6 ("anv: implement VK_EXT_pipeline_creation_feedback")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20216>
(cherry picked from commit 68b546ec3daacc93513b31583cbe6eb7f8fdc25c)

intel/nir/rt: fixup primitive id

There is a delta index value in the hit structure, we forgot to add it
to the base value.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 046571479028 ("intel/nir/rt: add more helpers for ray queries")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7565
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19346>
(cherry picked from commit 610639682533783796fe32bdcb2b4d3375fae56f)

radv: fix hashing descriptor set layout

Shouldn't have pointers.

Fixes: 19f8d338761 ("radv: Use vk_descriptor_set_layout")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20250>
(cherry picked from commit 13f39da71a69026445fc5455d749858aa7ad94dc)

nir: Do not consider phis with incompatible dests equal

CSE tries to collapse equal instructions, and collapsing two phis with incompatible dests is illegal.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Fixes: 6bdce55c ("nir: Add a basic CSE pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19960>
(cherry picked from commit a54c2c828941ef1325fc1a3b49eba32f3c964f0d)

Revert "anv: compile anv_acceleration_structure.c"

This reverts commit 74d0be27ae9eb666df948874a20a3b4464df7db1.

Also remove anv_acceleration_structure.c, it was meant to be removed
earlier. There was probably a rebase issue somewhere.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20248>
(cherry picked from commit d608706875996b05df48b0e35ee0456f0f2ae8cf)

aco/ra: don't swap p_create_vector operand with definition blocker for scc

SCC is 1-bit, and we can't copy a 32-bit value into it.

Fixes dEQP-VK.spirv_assembly.type.scalar.i32.iequal_tesse with
ACO_DEBUG=noopt.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 9476986e6f6 ("aco/ra: special-case get_reg_for_create_vector_copy()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20240>
(cherry picked from commit a05dd58309caf7e3857eb7f02084d8c9667c9efc)

frontends/va: fix gst videotestsrc h264 enc fail issue.

problem:
when doing "gst-launch-1.0 -v videotestsrc num-buffer=10 !
vaapih264enc ! fakeink"

The command will fail due to gst will fetch the first
available supported format in the list, it becomes P010_LE
due to the commit in

[0b02db3007]
frontends/va: fixed av1 decoding 10bit ffmpeg output YUV issue

fix:
move the P010_LE code block to the end of the function, the sequence
of the supported formats restored to its original.

cc: mesa-stable

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20242>
(cherry picked from commit a73e86e0a5eb58e2f25f7b7419a78c122cc5ab1a)

anv: emit sample mask state independent of fragment stage

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7861
Fixes: 9f6af43743d ("anv: dynamic multisample sample mask")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20221>
(cherry picked from commit 68ef0d84481fd92df6cde8935f079d958e6b36e9)

radeonsi: disable av1 decode for navi24

Disable AV1 decode for Navi24 since hardware doesn't support.

fixed: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7855

cc: mesa-stable

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20230>
(cherry picked from commit 5233551e1912519b456515ac8da7a62c9779fca8)

intel/fs: implement Wa_14017989577

The first instruction of any kernel should have non-zero emask. This
restriction needs to be obeyed to avoid GPU hangs.

Patch adds a function to insert dummy mov as first instruction
to make sure this requirement is fulfilled.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20194>
(cherry picked from commit bc4b7de0d0469e296f7ec4626fccdf97926b1c8e)

intel/compiler: Set NoMask on cr0 access for float controls mode

This is trying to clear a bit in the control register.  However, it's
executing with whatever channel mask happens to be active.  Typically
this is the one at the start of the program, so at least some channels
will be active.  Typically the first channel will be active due to
packed dispatch, but that's not always guaranteed.  Without NoMask,
the float controls writes may randomly not happen.

Recent GPUs also seem to have a hang issue when the first instruction in
the shader doesn't have any active channels.  Having an instruction with
NoMask at the start of the program works around the issue.  See HSD bug
14017989577.  In our case, the float controls preamble was breaking that
restriction every time, causing us to run into this problem frequently.

Thanks to Tapani Pälli for finding this hang issue, and Francisco
Jerez and Lionel Landwerlin for helping pinpoint this issue during
review of a workaround patch in !20194.

Fixes GPU hangs in Elder Scrolls Online, Witcher 3, and likely more.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7639
Fixes: 9da56ffc522 ("i965/fs: add emit_shader_float_controls_execution_mode() and aux functions")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20214>
(cherry picked from commit bafbe7c23a1cdd8c27ee5ea2da6b0575c53e2c5f)

vulkan: VkPolygonMode has a bit more than two values

Fixes: 9d0ed9cbcc0 ("vulkan: Add more dynamic rasterizer state")

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20212>
(cherry picked from commit e1ab7629f8a459df87009c7cb28b41acfb17e45c)

anv/hasvk: Clamping Scissor Rect values in a valid range

On cmd_buffer_emit_scissor(), if VkViewport height or width are set to
a value lower than 1.0, y_max or x_max can be attributed negative values,
causing an overflow. That leads to ScissorRectangleYMax or
ScissorRectangleXMax to be set to values on an unsupported range.

Clamping x_max and y_max in the valid range solves the problem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7471
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20200>
(cherry picked from commit 2e775b8bdbc5cd0d120b5c757188f6e85bf0d59d)

meson: Do not enable drm for KGSL Turnip build

Android may use either DRM or some downstream solution, KGSL is a
downstream kernel driver for Adreno. Don't enable DRM when we want
Turnip to use KGSL instead of DRM.

Fixes: 09ac29cca9bf7978911f81bcfce12ce71c260a97
("meson: Enable system_has_kms_drm for android")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20168>
(cherry picked from commit 1cfc413c9a4cdd26222197ab0a518c2b603d82b1)

glx: fix xshm check to init xshm_opcode.

Found and proposed by Ray Strode (halfline)

Fixes: 68e89401140d ("glx/drisw: use xcb instead of X to query connection")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20188>
(cherry picked from commit 57b7102ef96a282128ead4e7a8c03c7fdb53e71a)

zink: don't use defunct custom-flag

We're no longer respecting this flag, so there's no need in setting it.

Fixes: 00dc0036bb6 ("zink: flatten out buffer creation usage flags codepath")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20183>
(cherry picked from commit 2ccf481c17ccded161b9eecb63a257d81056e3ec)

venus: fix deqp tests failed on iub descriptor type

Fixes: abae9d4831b ("Add the iub binding count tracking")

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20064>
(cherry picked from commit fbf4c6e43ff810625ff916d40c6b00429adaaf14)

radv: fix guardband if the polygon mode is points or lines

If points or lines are drawn using the polygon mode, the guardband
should be adjusted for large points/lines.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20185>
(cherry picked from commit 12f26b5e6d57a1fd03c1f1fb0ab8ccae657026ab)

nir/lower_task_shader: fix task payload corruption when shared memory workaround is enabled

We were not taking into account that when all invocations within workgroup
are active, we'll copy more data than needed, corrupting task payload
of other workgroups.

Fixes: 8aff8d3dd42 ("nir: Add common task shader lowering to make the backend's job easier.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20080>
(cherry picked from commit ffefa386fda5aec8f66b4499d93b41a846a0b86c)

aco: more carefully apply constant offsets into scratch accesses

Death stranding does scratch_arr[80-idx]. This doesn't seem to work if we
try to combine the subtraction into the access.

fossil-db (navi21):
Totals from 52 (0.04% of 135636) affected shaders:
Instrs: 78560 -> 79036 (+0.61%)
CodeSize: 427940 -> 431188 (+0.76%)
Latency: 1313809 -> 1318142 (+0.33%)
InvThroughput: 292833 -> 293842 (+0.34%)
VClause: 2361 -> 2555 (+8.22%); split: -0.51%, +8.73%
Copies: 8767 -> 8746 (-0.24%); split: -0.35%, +0.11%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 0e783d687a3 ("aco: use scratch_* for scratch load/store on GFX9+")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7735
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20117>
(cherry picked from commit 381de3c809fce5427308c696bbd313360194eff4)

radeonsi/vcn: adding av1 decoding film grain block

add the logic for calculating film grain related
coefficients for VCN to generate film grain output.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19660>
(cherry picked from commit b28356745686571676742f3822fd371b95e8742b)

radv: use LATE_Z for depth/stencil attachments used in feedback loops

To make sure shader invocations read the correct values.

Fixes dEQP-VK.rasterization.rasterization_order_attachment_access.*.samples_*.multi_draw_barriers

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19728>
(cherry picked from commit a42f8d49c39eb59a520fde05fdcab0ffab3a16c6)

nir: fix nir_link_varying_precision

link_varyings ignores precisions and can assign the same location to
variables with different precisions. nir_link_varying_precision should
check location_frac as well.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20113>
(cherry picked from commit 7244d885164aa59ca136358d256a0078b24a455d)

intel: add missing restriction on fragment simd dispatch

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7755
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
(cherry picked from commit d4cd33630a9b90b95390f10d3aaa52f6f5e20245)

intel: factor out dispatch PS enabling logic

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
(cherry picked from commit b9403b1c477e7af04114ae6a4e16ca370e22253c)

radv: do not set ZPASS_INCREMENT_DISABLE on GFX11

This field no longer exists.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20090>
(cherry picked from commit b051719b05894c3c5b9f0f8ad919be478b43697b)

radv: fix emitting invalid color attachments

Note sure how this happened.

Fixes: 97dc28b1776 ("radv: fix configuring COLOR_INVALID on GFX11")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20127>
(cherry picked from commit 664aa7a37b540b27f8bd96b1d685c8e449d6a711)

dzn: Don't crash when libd3d12.so can't be found

`dzn_instance_create` will call `dzn_instance_destroy` when the d3d12
library fails to load. Just like the issue in `d3d12_screen`, this will
lead to a crash because `d3d12_mod` is NULL.

To fix this, only close the library after if it was actually opened.

Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20145>
(cherry picked from commit b5133894005720db24a8e0cc17e047a291953ff4)

d3d12: Don't crash when libd3d12.so can't be found

`d3d12_destroy_screen` is called by `d3d12_create_dxcore_screen` after
`d3d12_init_screen_base` fails and attempts to call `util_dl_close` on
a NULL pointer, leading to an abort.

To fix this, only close the library after if it was actually opened.

Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20145>
(cherry picked from commit b3d1ae19f2f4d93cf0a5f45a598149ac4e8e05aa)

anv: Defer flushing PIPE_CONTROL bits forbidden in CCS while in GPGPU mode

Fixes: 313aeee8 ("anv: Use pending pipe control mechanism in flush_pipeline_select()
")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7816
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20124>
(cherry picked from commit 77ecf9149c7fdadbb24b471785c4d5b4e285f2df)

dxil: Use nir_const_value_for_uint in dxil_nir_lower_int_samplers

This change should avoid any accidental rounding issues because of
border colors getting stored in a float in dxil_wrap_sampler_state. It
also switches us to using the correct helpers for nir_const_value so we
can avoid any weird uninitialized data failures that can be caused by
filling out the fields in the struct directly.

Fixes: b9c61379ab4c ("microsoft/compiler: translate nir to dxil")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit cd5c66e165374026d62692bcbf69a7157e460f91)

r600/nir: Fix u64vec2 immediate lowering

There were a couple of issues here:

1. We should be using nir_const_value_for_uint instead of setting the
union fields directly to ensure the rest of the union is zeroed.

2. It was always filling out the first two components of val even if
the incoming constant had 2 64-bit components.

Fixes: 165fb5117bf7 ("r600/sfn: add lowering passes to get 64 bit ops lowered to 32 bit vec2")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit f3f1c28f8e6d40823e3d12415a8d0ea622f9fa20)

st/mesa: Use nir_const_value_for_bool() in ATIFS

Fixes: 0a179bb6e26b ("st/mesa: Generate NIR for ATI_fragment_shader instead of TGSI.")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit 49d86200e5cd8ac15c14131772644b21bf57865e)

nir: Use nir_const_value_for_int in nir_lower_subgroups

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7670
Fixes: e4e79de2a420 ("nir/subgroups: Support > 1 ballot components")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit e6de164e0305d517fb66c01c9fc8931c278867f6)

radv/rra: Set the metadata size correctly

Fixes: 5749806 ("radv: Add Radeon Raytracing Analyzer trace dumping utilities")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20047>
(cherry picked from commit bb6b45e26ed56af8a94357a58fd849143671cf7f)

nir/nir_opt_offsets: Prevent offsets going above max

In try_fold_load_store when trying to extract const addition from
non-const offset source, we should take into account that there is
already a constant base offset, which should count towards the limit.

The issue was found in "Monster Hunter: World" running on Turnip.

Fixes: cac6f633b21799bd1ecc35471d73a0bd190ccada
("nir/opt_offsets: Use nir_ssa_scalar to chase offset additions.")

Well, the issue was present before this commit but it made a lot
of changes in surrounding code.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20099>
(cherry picked from commit 5d025f4003b34c3540b62f9146a5e68da7756cf2)

anv: correctly predicate ray tracing

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7479fe6ae093 ("anv: Implement vkCmdTraceRays and vkCmdTraceRaysIndirect")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20011>
(cherry picked from commit af3f7948d149faded1b4f24ec5e6ae03001e7cfb)

isl: don't report I915_FORMAT_MOD_Y_TILED_CCS on Gfx8

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
(cherry picked from commit 0626b68c88df50e30e61e9fd2ba3e46144ff9ad5)

ir3: Reduce the maximum allowed imm offset for shared var load/store

STL/LDL have 13 bits to store imm offset. However the most significant
bit in the offset is a sign bit, so the positive offset is limited by
12 bits.

nir_opt_offsets only has the upper limit and doesn't deal with
negative offsets, so shared_max should be changed to `(1 << 12) - 1`.

The issue was found in "Monster Hunter: World".

Fixes: 0b2da9d795610df15346a594384c39a096be338f
("ir3: Limit the maximum imm offset in nir_opt_offset for shared vars")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20100>
(cherry picked from commit 8f0177b3345f8bcc3673b8a2a7c36ea36cbaa029)

ci: Rebalance radv/grunt testing

We've recently rebalanced our lab devices to get a fewer number of
grunts. Switch to scheduling only on the newer shinier ones, running
fewer tests. We'll evaluate the runtime, and if they're quick enough
then we can increase the amount of testing we do.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20081>
(cherry picked from commit 921cfcf4c4f5cb6f82ef978587e0462218093542)

v3dv: fix job serialization for single sync path

The idea in the single sync path is that we serialize any job that
needs to wait, however, our ANY queue syncobj only tracks the last job
submitted to any hardware queue, so in practice when we wait on this
we are only serializing against the queue to which we have submitted
the last job, which is not correct.

Fix that by accumulating the last job sync into the ANY queue synbcobj
to ensure that waiting on this syncobj effectively waits on all
hardware queues.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
(cherry picked from commit 4276ec9f2af33da270ca9cf6a6a9a62b2a4d060a)

v3dv: make single-sync paths more explicit

Instead of having functions that return early in multi-sync mode
let's only call them when we are in single-sync mode. I think this
makes the code more explicit.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
(cherry picked from commit 95b9293eeb02f3b43fb7de5afc6f7c89ffffe92f)

intel/compiler: user payload starts after TUE header & its padding

All data written by the user are offset by TUE header size.
Without this patch we copy the correct amount of user data, but both
"from" and "to" offsets are wrong.

Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit db0e6f9a07b49a95d99c2b2c25fd8a008466c4e8)

nir/lower_task_shader: allow offsetting of the start of payload

We need this, because on Intel task payload starts with private header,
followed by user-accessible data.

Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit f6adfd6278301aa772d3d44fc64ade21c9860574)

intel/compiler: adjust [store|load]_task_payload.base too

Base also needs to be converted from bytes to words.

Fixes: c36ae42e4cc ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit 7aaafaa8ae26ee1086a51089c12e4fa9e9645c2e)

freedreno/fdl: Set sRGB bit for storage images

This probably wasn't noticed earlier because tests using sRGB storage
images didn't exist, and we didn't know whether this works, but this
fixes dEQP-VK.image.store.without_format.2d.*_srgb which also proves
that the bit works.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20060>
(cherry picked from commit ccef6d1f5fdae95ee8aa5a68e83662e02645b64a)

radv: Handle nodes with 2 invalid children in internal node converter.

Fixes: 682dc5c28e4 ("radv: Add conversion shader for internal nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>
(cherry picked from commit f531f671ef64acc8ea56a473c05aeb5ea9f4c1f0)

aco: Use wave size specific opcode for s_or in cube map coord code.

Cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20041>
(cherry picked from commit a3beb82cf6bcf84425431ec17c046a80b2b7fc79)

pan/mdg: Emulate 8-bit with the 16-bit pipe

We don't care to support i8vec16, we just need a bit of 8-bit support to
implement format packing/unpacking in blend shaders. We're already doing
this by using the 16-bit pipe, we just need to commit to it all the way
-- reporting the correct sizes in max_bitsize_for_alu so the mask
packing logic works as intended -- and dropping the imov-specific hack
that was introduced to workaround a similar class of bugs.

With the previous patch, fixes:

dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1

Fixes: 39e4b7279dc ("pan/midg: Fix swizzling on 8-bit sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>
(cherry picked from commit 976405907e35629b42501a9f86b067986599cb28)

.pick_status.json: Update to 264a0cabd1dd2a619f24e34f21f767c6bf36fe76

iris: move bindless surface state heap inside the surface state heap

We're about to make scratch surface states part of the surface state
heap. Because those are required to be in the low 26bits parts surface
state heap (we're limited in bits handed in the CFE_STATE, 3DSTATE_VS,
etc... instructions), this change splits the 32bit surface state heap
as follow:

   - 8Mb of surface states for scratch
   - 1Gb - 8Mb of binding tables
   - 3Gb of surface states

That way all of the surfaces are located within a 4Gb region visible
from STATE_BASE_ADDRESS::SurfaceStateBaseAddress

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
(cherry picked from commit daab161535747cf5aef443e4cee46c5415662848)

docs: add release notes for 22.3.0

VERSION: bump for 22.3.0

commit_in_branch.py: add support for checking staging branches

Or any branch that contains a `/` slash.

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>
(cherry picked from commit 707015891fc65dcf5b0b2601aa78f1fb33a01f39)

ir3: Don't save/restore disasm string pointer

It's not in the key, so it randomly may or may not be present, and if it
is present then we don't actually save/restore the contents, so we will
save/restore random pointer values from the last run. Turnip already
disables searching the shader cache when assembly is requested, but
still wrote the final ir3_shader_variant which resulted in trying to
save random stale pointers when saving off the executable if a
subsequent compile hit that cache entry.

This fixes flakes in
dEQP-VK.pipeline.pipeline_library.shader_module_identifier.pipeline_from_id.*
for me.

Fixes: 56909868cd1 ("turnip: implement VK_KHR_pipeline_executable_properties")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20056>
(cherry picked from commit 8ba2d612d51497b274ff9c4213e1c373b9bb1ca5)

tu: Fix binding NULL descriptor sets

This fixes the new test
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.other.null_descriptor_set_in_monolithic_pipeline.

Fixes: e9f5de11d40 ("tu: Initial implementation of VK_EXT_graphics_pipeline_library")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20057>
(cherry picked from commit 515c9a2e0754bd8a12b0d0b708ce4b0dba29102e)

radv: disable VRS entirely on GFX11

Based on registers, VRS changed a lot and it's unclear how to program
it. This disable VK_KHR_fragment_shading_rate, VRS flat shading and
RADV_FORCE_VRS.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 80072df8246f580a4c7d31fb82a9f746c3e1ba8d)

radv: do not enable NGG culling on GFX11

RadeonSI disables it as well. It's really unclear if it will help or
not (eg. NGG culling never helped on GFX10).

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 5d552b4f6cbfcb4bf14e3a0bdce01cc00eb61073)

radv: do not enable DCC for MSAA images without FMASK

I don't know how this is supposed to work, especially for fast clears
because CMASK should be cleared to 0xC but FMASK implies CMASK.
This fixes a bunch of MSAA test failures on GFX10.3 with
RADV_DEBUG=nofmask.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 84a7138d3cfca05fbd623707525b9d4479a27e94)

radv: set INTERPOLATE_COMP_Z to 0 on GFX11

Ported from RadeonSI to fix a EQAA bug.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 9b637aa9a17fd14c63b821629fb30d5fc4875df0)

radv: set missing SPI_SHADER_PGM_xxx registers on GFX11

Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 62715a6d039a7f2499ceca78476ebd42a5a03068)

radv: introduce RADV_DEBUG=nofmask

To disable MSAA compression on MSAA images. This will also allow us to
emulate GFX11 (FMASK has been removed) and to experiment 32 byte
descriptor sizes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19613>
(cherry picked from commit cf7b96a83f66f150bca5df2f510ed6951497d9c6)

panfrost/blend: Fix invalid const values leading to NIR validation errors

Using a designated initializer like this leaves padding bits, which form
part of the aliasing u64/f64 member of the union, uninitialised, but a
nir_const_value must always have the unused bits zeroed out. Thus, use
the nir_const_value_for_float helper instead like everywhere else which
will do a memset 0 for us first.

Without this, using the pan_blend shader in a build with validation
enabled fails with:

  NIR validation failed after nir_lower_vars_to_ssa
  ...
            vec4 32 ssa_58 = load_const (0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f800000 /* 1.000000 */)
  error: memcmp(val, &cmp_val, sizeof(cmp_val)) == 0 (../src/compiler/nir/nir_validate.c:976)

Fixes: 1378c67bcf9e ("panfrost/blend: Inline blend constants")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20071>
(cherry picked from commit 750325730bb84981f68d78b205fb0cec1e165100)

venus: fix android wsi with global fencing disabled

Fixes: b21e4a7990c ("venus: put android wsi on the sub-optimal path")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20049>
(cherry picked from commit 6148ccef6372e634ea4875b75419bfdc64e6b219)

radeonsi/vcn: set current pic index correctly

video corruption observed while running decode test for av1
content in chromeos.

solution is when target buffer is found in render pic list and when
target codec is null, set curr_pic_indx as index to the
pic in render pic list.

Cc: mesa-stable
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20000>
(cherry picked from commit 8b99e96dc8b44a747824b9d227a72e68012ec520)

nir/lower_int64: fix shift lowering

Starting with !19748 lowered 64 bit shifts were showing wrong results for
shifts with insignificant bits set.

nir shifts are defined to only look at the least significant bits. The
lowering has take this into account.

So there are two things going on:
1. the `ieq` and `uge` further down depend on `y` being masked.
2. the calculation of `reverse_count` actually depends on a masked `y` as
well, due to the `(iabs (iadd y -32))` giving a different result for
shifts > 31;

Fixes: 41f3e9e5f5d ("nir: Implement lowering of 64-bit shift operations")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19995>
(cherry picked from commit 5398dd04bf62db100639d96c84a8c41041f4ad01)

tu: Use right enum for compute active_shader_stages

This is VkShaderStageFlags, not VkPipelineStageFlags. Fixes preloading
descriptors for compute dispatches.

Fixes: d862a2ebcbf ("turnip: Only emit descriptor loads for active stages in the pipeline.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20059>
(cherry picked from commit 0a0a04bdaa6faf1dd3e937f7087ae1c4f240c916)

meson: Enable system_has_kms_drm for android

This allows to build libgbm when system = 'android' is set in
the cross_file.

Cc: "22.3" "22.2" mesa-stable
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20033>
(cherry picked from commit 09ac29cca9bf7978911f81bcfce12ce71c260a97)

d3d12: fix max-array-layers

We used to need this, because we incorrectly multiplied the cube array
sizes by 6. Now that this has been fixed, we can actually support the
OpenGL 4.1 limit for this.

Fixes: 7118b2136e9 ("d3d12: Don't multiply cube array sizes by 6")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
(cherry picked from commit acc0039aecec661e55e2dd90554a1d08a39d677c)

AOSP: Add intel_hasvk vulkan library suffix

Required to correctly install vulkan.intel_hasvk.so module
after commit 50013ca9 ("intel: add a hasvk vulkan driver")

In order to set property ro.hardware.vulkan as 'intel_hasvk' for the correct iGPU parts at init stage,
i915 'graphics version' can only be detected by means of /sys/kernel/debug/dri/0/i915_capabilities
and debugfs needs to be mounted at early-init stage

https://review.lineageos.org/c/LineageOS/android_device_lge_g3-common/+/19875

Cc: "22.3" mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20048>
(cherry picked from commit ea10b0fc7add2ad9dd486e69b5b5e7aca3c422f7)

r600/sfn: always use four slots for Cayman trans ops

This is a partial revert of
ed6204eb0 (r600/sfn: only use 3 channels on Cayman for trans ops)

The scheduler and/or optimizer passes generate faulty code when
we use only three slots as decribed in the spec. So for now disable
this optimization.

Fixes: ed6204eb0 (r600/sfn: only use 3 channels on Cayman for trans ops)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7774

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20034>
(cherry picked from commit 28c7684eb9a898089844376193d8332b5f58f3d8)

radv/rt: Check space before emitting descriptors

Found by inspection.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20020>
(cherry picked from commit c5d91ab254e59bedfc0faf71cfc46531d9be4ea8)

radv/ray_queries: Fix AABB handling

AABB intersections always have to be committed manually.
-> We don't have to copy opaque ones to closest.

It's also invalid to query t for candidate AABBs.

Totals from 7 (14.29% of 49) affected shaders:
CodeSize: 171008 -> 169672 (-0.78%)
Instrs: 32499 -> 32250 (-0.77%); split: -0.78%, +0.01%
Latency: 418859 -> 414759 (-0.98%); split: -0.98%, +0.00%
InvThroughput: 89182 -> 88251 (-1.04%); split: -1.05%, +0.00%
VClause: 602 -> 599 (-0.50%)
SClause: 837 -> 835 (-0.24%)
Copies: 4804 -> 4802 (-0.04%); split: -0.35%, +0.31%
Branches: 1593 -> 1585 (-0.50%)
PreSGPRs: 567 -> 566 (-0.18%)

Fixes: 3f72061 ("radv/rq: Use the common traversal helper")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19698>
(cherry picked from commit 0966fb2c10025398fc048361a9898ba2d56b4f9b)

radv: reserve space for the scissor in vkCmdBeginRendering.

Fixes: c7d0d328d56 ("radv: Set the window scissor to the render area, not framebuffer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20014>
(cherry picked from commit a97a6d0f0e78c637f7aa4d907e608043efb51528)

etnaviv: fix wrong surface TS clear size

Clearing ts_size - ts_offset bytes in a level means we are clearing the
TS region of all layers in the level starting from the surface layer, so
clearing one surface might corrupt all other layers of a resource level.
Use the correct size to clear only the requested TS region.

Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19814>
(cherry picked from commit b6fa3cdb0e693f49cdc278ed5923bb9dc048ccbb)

etnaviv: blt: use correct TS offset in clear operations

Using the ts_offset from the level means we are always clearing the
TS region of layer 0 of the level. Use the correct offset which takes
into account the layer offset.

Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19814>
(cherry picked from commit d9e2a7d6adace0a794c7147f0a5bab43277e5fa6)

Revert "glx/dri: Fix DRI drawable release at MakeCurrent time"

This reverts commit 31b04e420b0eb080084c6323066ea0b83929d59e which
is also breaking KDE in some ways.

Fixes: #7674
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19972>
(cherry picked from commit ea3f73ba85be46dcb9712b43fef52b09cfae643b)

Revert "glx: Fix drawable refcounting for naked Windows"

This reverts commit 768238fdc06eed3dce36da3baf811cb70db42b5c which
is not only leading to memory leaks, but also reportedly breaks KDE
pretty badly.

Fixes: #7674, #7435
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19972>
(cherry picked from commit 0cee008fee1dc0365cfb767ff7acf03f2127a03b)

etnaviv: rs: fix blits with insufficient alignment for dual pipe operation

Up-aligning the blit height does not always work, as some blit targets
have a smaller padded height. Fall back to single pipe operation if
increasing the height alignment fails. Still try to do it opportunistically
as it improves performance when resolving MSAA targets.

Fixes: 0ff96aaef3b1 ("etnaviv: rs: fix MSAA alignment adjustment")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19991>
(cherry picked from commit 797454edfcc4d2a6d0c21db451e9a0ea6e0a8023)

etnaviv: always use RS align when GPU has TEXTURE_HALIGN feature

Due to a logic bug we didn't always up-align the resource when the GPU
has the TEXTURE_HALIGN feature, which broke the RS blit when we need
to blit into a sampler shadow from a multi-tiled render target.

Fixes: 735718ed33b2 ("etnaviv: move etna_layout_multiple into etnaviv_resource.c")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19991>
(cherry picked from commit fd06b313b010adb6c6e9a7c30ab55163397f4d47)

driconf/intel: Use fake vendor to WA bad detection in Source engine games

Source engine uses flawed device detection in Linux native OpenGL backend,
which causes it to use bad configurations for Intel devices and thus
not always render correctly. Workaround this by using vendor string that
does not include "Intel" in it.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7725
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19828>
(cherry picked from commit 478ffe712765b5746482d37df32fff36e12192ef)

vulkan: Remove asserts that weren't valid for RADV ETC2 emulation.

Wasn't caught when radv was modified to use these helpers ...

Tried to move the aspects assert so it still checks application inputs.

Fixes: d9048e31a0d ("radv: Use vk_image_view as the base for radv_image_view")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19914>
(cherry picked from commit 13d755441c7b648e4f6671d833a6d58ada9ae32d)

radv: Fix sampler types in ETC2 decode.

Otherwise we'd have a type mismatch vs texture fetches, which
is asserted upon these days.

Fixes: 1153db23f58 ("radv: Add ETC2 decode shader.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19914>
(cherry picked from commit eab61863c0bd6b08bfc7c28d96cd99f49856e449)

radv: Use correct init order for ETC2 image views

Fixes: d9048e31a0d ("radv: Use vk_image_view as the base for radv_image_view")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19914>
(cherry picked from commit c6ec4925c0688cef557beb65c280b28ef3185132)

radv: make sure to mark DCC as compressed on GFX11

The bit has moved to FDCC_ENABLE on GFX11.
Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20005>
(cherry picked from commit ccac91db7bbf3b428ad4138e0982c54636b4b96c)

ac/nir: mask shift operands

NIR shifts are defined to truncate the shift amount to the number of bits
needed to represent the bit-size of the value shifted. LLVM treats large
shifts as poison. This fix achieves NIR semantics for shifts.

As an example, a|(b << 32), where "a" is 32bits, should produce a|b
according to NIR (because 32&31 == 0).

This caused LLVM to incorrectly optimize "(a >> c) | (b << (32 - c))" to a
u2u32(pack_64_2x32(a, b) >> c) (v_alignbit_b32), when the original NIR
should have returned "a | b" if c==0.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19966>
(cherry picked from commit 064336d35977abd0d5b6ed37784c6cc42cf4f66f)

virgl: Fix injection of double from const mov instruction

We only copy two components, we have to use the complete original source,
and we should rewrite the new source from scratch to avoid incorrect
dimension and indirect handling.

Fixes: 036d7172c (virgl: Move double operands to a temp to avoid double-swizzling bugs)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19975>
(cherry picked from commit d5217b024eac4e725a671b1c3992ab282c9c50f1)

.pick_status.json: Mark 470fbb35efe1935242b346427ec0fa22b40fff2b as denominated

radv: re-emit dynamic depth clamp enable if depth clip enable changed

The depth clamp mode depends on depth clip enable/disable.

Fixes: e48c0fbd8f7 ("radv: add support for dynamic depth clamp enable")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19843>
(cherry picked from commit de4de09a56c421ec1194dea016c3b9ef80abbb83)

mesa: treat unsupported queries as dummies

It's legal in OpenGL to start a query even if the result will have zero
valid bits. It's not enough to just report zero bits, We need to also
prevent calling down into the driver with these invalid queries.

Because ARB_ES3_compatibility adds ANY_SAMPLES_PASSED and
ANY_SAMPLES_PASSED_CONSERVATIVE to the set of queries that support zero
bits, we also need to check for the corresponding indices.

Fixes: 0186e9e1c51 ("mesa: always support occlusion queries")
Reviewed-by: Soroush Kashani <soroush.kashani@imgtec.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19750>
(cherry picked from commit 1b1e8873fe90e878f014140b3b6bd1e5dbfb5a4c)

st/vdpau: fix interop with GL

Fixes: e00bb6cb98b - mesa/st: use tracked samplerview swizzle values
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7751

Tested-By: Veerabadhran.Gopalakrishnan@amd.com
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19961>
(cherry picked from commit c70eec86efd9ca2faa1f66fcaf42cc37360dcb5e)

panfrost: Revert "Require 64-byte alignment on imports"

This reverts commit 811f8a19469722bea32f3c539b8cf0939fe3b057. As Alpine put it
-- this is causing more problems than it's fixing. Hotfix to revert the
offending commit until a more measured fix can be implemented.

Closes: #7731
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Jan Palus
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19993>
(cherry picked from commit 4b19725ee525f6f0b5785436680cea63a21445a1)

venus: enable VK_KHR_push_descriptor

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18988>
(cherry picked from commit 505a5bc79fa051781878df32603a505356c389bd)

venus: implement vkCmdPushDescriptorSetWithTemplateKHR

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18988>
(cherry picked from commit 933ca11f1a48b19fea088edfcf5177779083d7b5)

venus: extend VkPipelineLayout lifetime for batched VkCmdPushConstants()

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18988>
(cherry picked from commit 19f2b9d0bbd71ba218962a26434507e70f6cde98)

venus: extend lifetime of push descriptor set layout

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18988>
(cherry picked from commit 91966f2eff17cc7c95ca8a89ac40d5d211e5b407)

docs/zink: add missing required device-feature

Seems I forgot to add this to the list of required features.

Fixes: eb0195358c4 ("zink: only inspect dual-src limit if feature enabled")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19779>
(cherry picked from commit a2a0ac21e4f5a7c873e1bab05dee02a61171e378)