Simon Glass [Mon, 2 Aug 2021 00:54:35 +0000 (18:54 -0600)]
pci: imx: Drop DM_PCI check from cpu driver
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:33 +0000 (18:54 -0600)]
pci: Drop DM_PCI check from bios_emul
We don't need these checks anymore since when PCI is enabled, driver model
is always used.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:32 +0000 (18:54 -0600)]
pci: scsi: pci: Drop DM_PCI check from scsi
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:31 +0000 (18:54 -0600)]
pci: imx: Drop use of DM_PCI
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:30 +0000 (18:54 -0600)]
pci: msc01: Drop use of DM_PCI
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:29 +0000 (18:54 -0600)]
pci: gt64120: Drop use of DM_PCI
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:28 +0000 (18:54 -0600)]
ppc: socrates: Drop use of DM_PCI
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:27 +0000 (18:54 -0600)]
ppc: malta: Drop use of DM_PCI
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:26 +0000 (18:54 -0600)]
pci: usb: ohci: Test on PCI not DM_PCI
Now that DM_PCI is always enabled, check on CONFIG_PCI instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for non-PCI users of this code, reword]
Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Mon, 2 Aug 2021 00:54:24 +0000 (18:54 -0600)]
ppc: Drop DM_PCI from config files
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:23 +0000 (18:54 -0600)]
pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci()
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:22 +0000 (18:54 -0600)]
pci: freescale: Drop old code
Drop this old pre-driver model code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:21 +0000 (18:54 -0600)]
pci: powerpc: Drop old code
Drop the old pre-driver model code from these drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:20 +0000 (18:54 -0600)]
ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID
This is not used. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:19 +0000 (18:54 -0600)]
pci: Drop DM_PCI check from pci_common
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:17 +0000 (18:54 -0600)]
pci: Remove guard around compatibility functions
This prevents use of IS_ENABLED() in other files. Functions should be
visible in headers even if they are not available at link time.
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:14 +0000 (18:54 -0600)]
pci: Drop old code from pci command
Drop the pre-driver model code from this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 5 Aug 2021 01:18:33 +0000 (21:18 -0400)]
Merge branch '2021-08-04-assorted-minor-fixes'
- Assorted fixes
Adarsh Babu Kalepalli [Mon, 24 May 2021 08:05:39 +0000 (13:35 +0530)]
cmd:(cosmetic)Mentioned in 'chpart' command HELP text that it is for MTD devices
Modified the help text of 'chpart' command ,mentioning that it is
for MTD devices.
Signed-off-by: Adarsh Babu Kalepalli <opensource.kab@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adarsh Babu Kalepalli [Wed, 30 Jun 2021 18:27:45 +0000 (23:57 +0530)]
cmd:Elaborate 'blkcache' cmd HELP statement
HELP description is provided for ‘configure’ sub-command
of ‘blkcache’.
Signed-off-by: Adarsh Babu Kalepalli <opensource.kab@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Thu, 29 Jul 2021 18:27:17 +0000 (20:27 +0200)]
config: MPC8548CDS: eliminate symbol CONFIG_SYS_ID_EEPROM
Symbol CONFIG_SYS_ID_EEPROM is defined in include/configs/MPC8548CDS.h
but never used. Remove it here and from the whitelist.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Tue, 27 Jul 2021 17:01:44 +0000 (13:01 -0400)]
doc: Add basic information about running CI tests
Start out by documenting general expectations on when CI is run, how
anyone can run Azure pipelines, and how GitLab CI pipelines can be run.
Signed-off-by: Tom Rini <trini@konsulko.com>
Campbell Suter [Fri, 30 Apr 2021 04:45:46 +0000 (16:45 +1200)]
fs/squashfs: Fix some hardlinks reading the wrong inode
In SquashFS, the contents of a directory is stored by
squashfs_directory_entry structures which contain the file's name, inode
and position within the filesystem.
The inode number is not stored directly; instead each directory has one
or more headers which set a base inode number, and files store the
offset from that to the file's inode number.
In mksquashfs, each inode is allocated a number in the same order as
they are written to the directory table; thus the offset from the
header's base inode number to the file's inode number is usually
positive.
Hardlinks are simply stored with two directory entries referencing the
same file. This means the second entry will thus have an inode number
much lower than the surrounding files. Since the header's base inode
number comes from the first entry that uses the header, this delta will
usually be negative.
Previously, U-Boot's squashfs_directory_entry.inode_offset field was
declared as an unsigned value. Thus when a negative value was found, it
would either resolve to an invalid inode number or to that of an
unrelated file.
A squashfs image to test this can be created like so:
echo hi > sqfs_test_files/001-root-file
mkdir sqfs_test_files/002-subdir
touch sqfs_test_files/002-subdir/003-file
ln sqfs_test_files/{001-root-file,002-subdir/004-link}
mksquashfs sqfs_test_files/ test.sqfs -noappend
Note that squashfs sorts the files ASCIIbetacally, so we can use the
names to control the order they appear in. The ordering is important -
the first reference to the file must have a lower inode number than the
directory in which the second reference resides, and the second
reference cannot be the first file in the directory.
Listing this sample image in U-Boot results in:
=> sqfsls virtio 2 002-subdir
0 003-file
Inode not found.
0 004-link
Signed-off-by: Campbell Suter <campbell@snapit.group>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
John Keeping [Tue, 20 Apr 2021 18:19:44 +0000 (19:19 +0100)]
fit: Fix verification of images with external data
The "-E" option to mkimage generates a FIT with external data using the
data-size and data-offset properties which must both be ignored when
verifying a signature.
Add "data-offset" to the list of excluded properties for signature
verification; since the line is now too long, re-format the list to
one-per-line and make it static since the data is constant.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 15 Jul 2021 18:24:25 +0000 (14:24 -0400)]
CI: Update to LLVM-12
The current stable release of LLVM is 12, update to that. While at it,
fix that we had not correctly upgraded to LLVM 11 previously.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 3 Aug 2021 18:06:41 +0000 (14:06 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-spi
- SPI-NOR fix (Big Meng)
- XMC XM25QH64C flash (Reto Schneider)
Tom Rini [Tue, 3 Aug 2021 13:07:01 +0000 (09:07 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-samsung
Bin Meng [Fri, 30 Jul 2021 07:20:17 +0000 (15:20 +0800)]
mtd: spi-nor: Mask out fast read if not requested in DT
The DT bindings of "jedec,spi-nor" [1] defines "m25p,fast-read" property
to indicate that "fast read" opcode can be used to read data from the
chip instead of the usual "read" opcode.
If this property is not present in DT, mask out fast read in
spi_nor_init_params(). This change mirrors the same logic in
spi_nor_info_init_params() in drivers/mtd/spi-nor/core.c in
the Linux kernel v5.14-rc3.
[1] Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml in the kernel tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Bin Meng [Fri, 30 Jul 2021 07:20:16 +0000 (15:20 +0800)]
mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()
The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's
hwcaps, and only looks to the controller on what can be supported.
The flash's hwcaps needs to be AND'ed before checking.
Fixes:
71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Bin Meng [Wed, 28 Jul 2021 12:50:14 +0000 (20:50 +0800)]
spi: spi-mem-nodm: Fix read data size issue
When slave drivers don't set the max_read_size, the spi-mem should
directly use data.nbytes and not limit to any size. But current
logic will limit to the max_write_size.
This commit mirrors the same changes in the dm version done in
commit
535b1fdb8e5e ("spi: spi-mem: Fix read data size issue").
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reto Schneider [Thu, 17 Jun 2021 16:26:51 +0000 (18:26 +0200)]
mtd: spi-nor-ids: Add support for XMC XM25QH64C
This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA
smart gateway.
Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Tue, 3 Aug 2021 01:35:50 +0000 (21:35 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
Tom Rini [Mon, 2 Aug 2021 17:32:20 +0000 (13:32 -0400)]
Merge branch '2021-08-02-numeric-input-cleanups'
- Merge in a series that cleans up and makes more consistent how we deal
with numeric input on the CLI. This saves a few bytes in a lot of
places.
Simon Glass [Sat, 24 Jul 2021 15:03:38 +0000 (09:03 -0600)]
lib: Allow using 0x when a decimal value is requested
U-Boot mostly uses hex for value input, largely because addresses are much
easier to understand in hex.
But in some cases a decimal value is requested, such as where the value is
small or hex does not make sense in the context. In these cases it is
sometimes useful to be able to provide a hex value in any case, if only to
resolve any ambiguity.
Add this functionality, for increased flexibility.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:37 +0000 (09:03 -0600)]
doc: Add a note about number representation
Mention the default base of U-Boot in the command-line section. Add
examples for decimal and octal.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:36 +0000 (09:03 -0600)]
doc: Convert command-line info to rST
Take this part of the README and put it into rST format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:35 +0000 (09:03 -0600)]
lib: Move common digit-parsing code into a function
The code to convert a character into a digit is repeated twice in this
file. Factor it out into a separate function. This also makes the code a
little easier to read.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:34 +0000 (09:03 -0600)]
lib: Add octal tests for simple_strtoul/l()
This function support decoding octal but no tests are included yet.
Add some.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:33 +0000 (09:03 -0600)]
lib: Add tests for simple_strtoull()
Add some tests that check the behaviour of this function. These are the
same as for simple_strtoul() but with a few longer values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:32 +0000 (09:03 -0600)]
lib: Drop unnecessary check for hex digit
If we see 0x then we can assume this is the start of a hex value. It
does not seem necessary to check for a hex digit after that since it will
happen when parsing the value anyway.
Drop this check to simplify the code and reduce size. Add a few more test
cases for when a 0x prefix is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:31 +0000 (09:03 -0600)]
lib: Comment the base parameter with simple_strtoul/l()
This parameter is not documented properly since it does not cover the
meaning when the base is 0. Update this in both functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:30 +0000 (09:03 -0600)]
global: Convert simple_strtoul() with decimal to dectoul()
It is a pain to have to specify the value 10 in each call. Add a new
dectoul() function and update the code to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:29 +0000 (09:03 -0600)]
global: Convert simple_strtoul() with hex to hextoul()
It is a pain to have to specify the value 16 in each call. Add a new
hextoul() function and update the code to use it.
Add a proper comment to simple_strtoul() while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:28 +0000 (09:03 -0600)]
hash: Ensure verification hex pairs are terminated
This function seems to assume that the chr[] variable contains zeros at
the start, which is not always true. Use strlcpy() to be safe.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 07:05:16 +0000 (15:05 +0800)]
x86: crownbay: Use external graphics card by default
The board routes the Integrated Graphics Device (IGD) to an LVDS
panel, which is less popular than a PCIe based graphics card.
Disable the IGD so that it does not show up in the PCI configuration
space as a VGA display controller, so we can use an external PCIe
graphics card with whatever cable we have.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 07:05:15 +0000 (15:05 +0800)]
x86: queensbay: Return directly if IGD / SDVO were already disabled
Initialize 'igd' and 'sdvo' to NULL so that we just need to test
them against NULL later, to be compatible with that case that IGD
and SDVO devices were already in disabled state.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 09:45:22 +0000 (17:45 +0800)]
x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE
For FSP1, there is no such INIT_PHASE_END_FIRMWARE.
Move board_final_cleanup() to fsp2 directory.
Fixes:
7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 09:45:21 +0000 (17:45 +0800)]
x86: fsp: Don't program MTRR for DRAM for FSP1
There are several outstanding issues as to why this does not apply
to FSP1:
* For FSP1, the system memory and reserved memory used by FSP are
already programmed in the MTRR by FSP.
* The 'mtrr_top' mistakenly includes TSEG memory range that has the
same RES_MEM_RESERVED resource type. Its address is programmed
and reported by FSP to be near the top of 4 GiB space, which is
not what we want for SDRAM.
* The call to mtrr_add_request() is not guaranteed to have its size
to be exactly the power of 2. This causes reserved bits of the
IA32_MTRR_PHYSMASK register to be written which generates #GP.
For FSP2, it seems this is necessary as without this, U-Boot boot
process on Chromebook Coral goes very slowly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 2 Aug 2021 12:54:23 +0000 (08:54 -0400)]
Merge tag 'efi-2021-10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-10-rc2
Documentation:
* handle 'make htmldocs' warnings as errors
* add missing board/ti/index.rst
Bug fixes:
* avoid buffer overrun in TrueType console
* lib: disable CONFIG_SPL_HEXDUMP by default
Tom Rini [Mon, 2 Aug 2021 12:53:58 +0000 (08:53 -0400)]
Merge tag 'mmc-2021-7-30' of https://source.denx.de/u-boot/custodians/u-boot-mmc
pl180_mmci update and cleanup
fix rpmb routing memory alignment
Bin Meng [Sat, 31 Jul 2021 08:45:28 +0000 (16:45 +0800)]
x86: cmd: hob: Fix display of resource type for system memory
The resource type for system memory is currently displayed as
"unknown", which is wrong.
Fixes:
51af144eb7a0 ("x86: Allow showing details about a HOB entry")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:27 +0000 (16:45 +0800)]
x86: cmd: hob: Fix the command usage and help messages
At present the hob command usage and help messages are messed up
in a single line. They should be separated.
This was a regression introduced when [seq] and [-v] were added
to the command.
Fixes:
d11544dfa9f4 ("x86: hob: Add way to show a single hob entry")
Fixes:
51af144eb7a0 ("x86: Allow showing details about a HOB entry")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:26 +0000 (16:45 +0800)]
x86: mtrr: Abort if requested size is not power of 2
The size parameter of mtrr_add_request() and mtrr_set_next_var()
shall be power of 2, otherwise the logic creates a mask that does
not meet the requirement of IA32_MTRR_PHYSMASK register.
Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:25 +0000 (16:45 +0800)]
x86: mtrr: Skip MSRs that were already programmed in mtrr_commit()
At present mtrr_commit() programs the MTRR MSRs starting from
index 0, which may overwrite MSRs that were already programmed
by previous boot stage or FSP.
Switch to call mtrr_set_next_var() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:24 +0000 (16:45 +0800)]
x86: mtrr: Do not clear the unused ones in mtrr_commit()
Current mtrr_commit() logic assumes that MTRR MSRs are programmed
consecutively from index 0 to its maximum number, and whenever it
detects an unused one, it clears all other MTRRs starting from that
one. However this may not always be the case.
In fact, the clear is not much helpful because these MTRRs come out
of reset as disabled already. Drop the clear codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 04:00:23 +0000 (12:00 +0800)]
x86: dts: Define a default TSC timer frequency
If for some reason, TSC timer frequency cannot be determined from
hardware, nor is it specified in the device tree, U-Boot will panic
resulting in endless reset during boot.
Let's define a default TSC timer frequency using the Kconfig value
CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
/include/ otherwise the macro is not pre-processed).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 04:00:22 +0000 (12:00 +0800)]
x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ
Currently there are two places to specify the x86 TSC timer frequency
with one in Kconfig used for early timer and the other one in device
tree used when the frequency cannot be determined from hardware.
This may potentially create an inconsistent config where the 2 values
do not match. Let's use the one specified in Kconfig in the device
tree as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 27 Jul 2021 15:15:39 +0000 (23:15 +0800)]
x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROM
These 2 options are no longer needed as now binman is used to build
u-boot.rom.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 27 Jul 2021 13:30:02 +0000 (21:30 +0800)]
x86: crownbay: Adjust VGA rom address
binman complains when binary blobs are present:
Node '/binman/rom/intel-vga': Offset 0xfff90000 (
4294508544) overlaps
with previous entry '/binman/rom/u-boot-dtb-with-ucode' ending at
0xfff9204c (
4294516812)
Adjust VGA rom address to 0xfffa0000 so that u-boot.rom image can be
successfully built again.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Shevchenko [Fri, 30 Jul 2021 20:15:44 +0000 (23:15 +0300)]
x86: tangier: Fix DMA controller IRQ polarity in CSRT
IRQ polarity in CSRT has the same definition as by ACPI specification
chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes:
5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 29 Jul 2021 12:18:23 +0000 (20:18 +0800)]
x86: dts: Add "m25p,fast-read" to SPI flash node
Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should
have "m25p,fast-read" property present in their DT nodes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 10:28:57 +0000 (18:28 +0800)]
x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS
Since commit
71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
SPI flash on Intel Crown Bay board does not work anymore.
Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to
the spi-nor core.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 10:28:56 +0000 (18:28 +0800)]
spi: ich: Limit slave->max_read_size
Since commit
43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
(in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller
in software sequencer mode.
ICH controller can only transfer a small number of bytes at once.
Before commit
43c145b8b3ee, the logic happens to make sure data.nbytes
is limited to slave->max_write_size but after commit
43c145b8b3ee
data.nbytes is no longer limited because slave->max_read_size is not
initialized with a valid number.
Fixes:
43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Mon, 2 Aug 2021 06:21:12 +0000 (08:21 +0200)]
efi_loader: typo cerificate
%s/cerificate/certificate/
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 1 Aug 2021 21:29:20 +0000 (23:29 +0200)]
doc: add graphviz imagemagick as build dependencies
'make htmldocs' requires graphviz and imagemagick (at least with Sphinx
3.5.4).
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 1 Aug 2021 20:11:39 +0000 (22:11 +0200)]
doc: handle 'make htmldocs' warnings as errors
Parameter -W for sphinx-build turns build warnings into errors. This helps
us to avoid bad patches passing Gitlab CI.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 1 Aug 2021 20:09:44 +0000 (22:09 +0200)]
doc: add missing board/ti/index.rst
Commit
8baeeecbe305 ("doc: board: Move j721e document to doc/board/ti/
directory") introduced 'make htmldocs' build errors due to a missing
file board/ti/index.rst.
Fixes:
8baeeecbe305 ("doc: board: Move j721e document to doc/board/ti/ directory")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Sun, 1 Aug 2021 18:41:22 +0000 (14:41 -0400)]
Merge tag 'dm-pull-1aug21' of https://source.denx.de/u-boot/custodians/u-boot-dm
sandbox TPM-emulator improvements
rST documentation and fixes for moveconfig
handle empty 'ranges' property in dtoc
patman warning for invalid tag
clean-ups to 'fdt add' command
Simon Glass [Thu, 29 Jul 2021 01:23:11 +0000 (19:23 -0600)]
dtoc: Support widening a bool value
At present if we see 'ranges' property (with no value) we assume it is a
boolean, as per the devicetree spec.
But another node may define 'ranges' with a value, forcing us to widen it
to an int array. At present this is not supported and causes an error.
Fix this and add some test cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
Simon Glass [Thu, 29 Jul 2021 01:23:10 +0000 (19:23 -0600)]
dtoc: Fix widening an int array to an int
An int array can hold a single int so we should not need to do anything
in the widening operation. However due to a quirk in the code, an int[3]
widened with an int produced an int[4]. Fix this and add a test.
Fix a comment typo while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
Simon Glass [Thu, 29 Jul 2021 01:23:09 +0000 (19:23 -0600)]
dtoc: Rename is_wider_than() to reduce confusion
The current name is confusing because the logic is actually backwards from
what you might expect. Rename it to needs_widening() and update the
comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 21:14:39 +0000 (15:14 -0600)]
sandbox: Reduce keyed autoboot delay
The autoboot tests are a recent addition to U-Boot, providing much-needed
coverage in this area.
A side effect of the keyed autoboot test is that this feature is enabled
in sandbox always. This changes the autoboot prompt and confuses the
pytests. Some tests become slower, for example the vboot tests take about
27s now instead of 3s.
We don't actually need this feature enabled to be able to run the tests.
Add a switch to allow sandbox to turn it on and off as needed. Use this
in the one test that needs it.
Add a command-line flag in case this is desired in normal use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes:
25c8b9f298e ("test: add first autoboot unit tests")
Reviewed-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
Simon Glass [Thu, 22 Jul 2021 03:35:53 +0000 (21:35 -0600)]
moveconfig: Update to newer kconfiglib
Some of the more advanced features of this tool don't work anymore since
kconfiglib was update. Update the code accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 22 Jul 2021 03:35:52 +0000 (21:35 -0600)]
doc: Fix up outdated moveconfig docs
The examples here are a bit messed up since the command does not match
the documentation. Use a different example instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 22 Jul 2021 03:35:51 +0000 (21:35 -0600)]
doc: Add docs for the moveconfig tool
Move these docs into htmldocs so they can be read there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 22 Jul 2021 03:35:50 +0000 (21:35 -0600)]
doc: Move coccinelle into its own section
This tool has nothing to do with testing. It is for refactoring code
automatically using a 'semantic patch' tool.
Create a new section for 'refactoring' and move it into there. It is
likely that other topics may fall under the same heading, such as
using moveconfig and search/replace tools.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 22 Jul 2021 03:35:49 +0000 (21:35 -0600)]
doc: Create an intro section for testing
At present this information is hidden away. Make it more visible by
putting it first, in an intro section.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Patrick Delaunay [Thu, 22 Jul 2021 14:51:42 +0000 (16:51 +0200)]
patman: add warning for invalid tag
Add a error in patman tool when the commit message contents an invalid
tag "Serie-.*" instead of "Series-.*".
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 21 Jul 2021 20:55:26 +0000 (14:55 -0600)]
fdt: Show the type of devicetree with fdt addr
It seems useful to show whether the address of the Control or Working
devicetree is being shown. Add support for this. Drop the confusing 0x
prefix since the command itself only accepts hex.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 21 Jul 2021 20:55:25 +0000 (14:55 -0600)]
fdt: Tidy up the code a bit with fdt addr
Clean up the code a little before changing it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:18:06 +0000 (14:18 -0600)]
sandbox: tpm: Support extending a PCR multiple times
It is fairly easy to handle this case and it makes the emulator more
useful, since PCRs are commonly extended several times.
Add support for this, using U-Boot's sha256 support.
For now sandbox only supports a single PCR, but that is enough for the
tests that currently exist.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:18:05 +0000 (14:18 -0600)]
sandbox: tpm: Correct handling of SANDBOX_TPM_PCR_NB
This is the number of PCRs, so the current check is off by one. Also the
map itself should not be checked, just the resulting pcr_index, to avoid
confusing people who read the code.
Fix these problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:18:04 +0000 (14:18 -0600)]
sandbox: tpm: Support storing device state in tpm2
At present the tpm2 emulator does not support storing the device state.
Add this so we can handle the normal vboot flow through the sandbox
executables (VPL->SPL etc.) with the TPM contents staying in place.
Note: sandbox has not yet been converted to use livetree for the state
information, since livetree does not yet support writing to the tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:18:03 +0000 (14:18 -0600)]
sandbox: tpm: Support nvdata in TPM2
Add support for this feature in the TPM2 emulator, to support Chromium OS
vboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:18:02 +0000 (14:18 -0600)]
sandbox: tpm: Track whether the state is valid
Add checking as to whether the current TPM state is valid, so we can
implement reading/writing the state.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:18:01 +0000 (14:18 -0600)]
sandbox: tpm: Finish comments for struct sandbox_tpm2
Tidy up the missing comments for this struct.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:18:00 +0000 (14:18 -0600)]
sandbox: tpm: Correct handling of get-capability
This function current handles the kernel case incorrectly. Fix it, and
use the shorter TPM_HDR_LEN while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:17:59 +0000 (14:17 -0600)]
sandbox: tpm: Support the define-space command
Add support for this command, moving away from the previous approach of
hard-coding the initial data in the driver, now that the kernel-space data
has to be set up by the higher-level vboot code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:17:58 +0000 (14:17 -0600)]
sandbox: tpm: Tidy up reading and writing of device state
At present this code assumes that the TPM data has been read but this may
not be the case. Refactor the code to use a separate pointer so we know
the current state of the data.
Add error checking for the data size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 18 Jul 2021 20:17:57 +0000 (14:17 -0600)]
sandbox: tpm: Split out common nvdata code
We want to support nvdata in TPM2 as well. To avoid code duplicating the
associated code, move it into a common file.
Drop the special-case logic for the kernel space. This can be handled by
the higher-level code now, i.e. in vboot itself.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tim Harvey [Fri, 16 Jul 2021 22:44:12 +0000 (15:44 -0700)]
common: board_r: print error if binman_init fails
Display an error if binman_init fails.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Heinrich Schuchardt [Wed, 28 Jul 2021 08:52:53 +0000 (10:52 +0200)]
doc: riscv: flashing SiFive boards
We should not use /dev/sda and /dev/sdb in our examples. Users might
inadvertently mess up their workstation. Use /dev/sdX instead.
Remove console output like '# ' and '> ' which makes copying hard.
Set example language to bash for correct syntax-highlighting.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
iewed-by: Bin Meng <bmeng.cn@gmail.com>
Heinrich Schuchardt [Sat, 24 Jul 2021 15:35:46 +0000 (17:35 +0200)]
lib: disable CONFIG_SPL_HEXDUMP by default
CONFIG_HEXDUMP is needed to display UEFI variables using 'printenv -e'.
Enabling CONFIG_SPL_HEXDUMP only makes sense for debugging purposes.
Hence CONFIG_SPL_HEXDUMP should not be enabled by default.
The following boards currently have CONFIG_SPL_HEXDUMP=y. This includes
boards that don't use SPL at all.
axm_defconfig
imx8mm-cl-iot-gate_defconfig
imx8mm_venice_defconfig
imxrt1020-evk_defconfig
imxrt1050-evk_defconfig
kontron_sl28_defconfig
kp_imx53_defconfig
lx2160ardb_tfa_stmm_defconfig
mt7622_rfb_defconfig
octeon_ebb7304_defconfig
octeon_nic23_defconfig
qemu_arm64_defconfig
qemu_arm_defconfig
qemu-riscv32_defconfig
qemu-riscv32_smode_defconfig
qemu-riscv64_defconfig
qemu-riscv64_smode_defconfig
qemu-x86_64_defconfig
qemu-x86_defconfig
sandbox64_defconfig
sandbox_defconfig
stm32mp15_basic_defconfig
stm32mp15_trusted_defconfig
synquacer_developerbox_defconfig
taurus_defconfig
xilinx_versal_virt_defconfig
The patch only keeps it enabled on
sandbox_spl_defconfig
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 28 Feb 2021 20:42:51 +0000 (21:42 +0100)]
video: buffer overrun in TrueType console
When scrolling the TrueType console a buffer overrun occurs.
Fixes:
a29b012037cc ("video: Add a console driver that uses TrueType fonts")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sun, 1 Aug 2021 00:51:24 +0000 (20:51 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi
- Move the PSCI runtime code for H3/A23/A33 into SRAM
- Pick the environment from the actual MMC boot device (SD card vs.
eMMC)
- Plus a small improvement from Icenowy, just for good measure.
Icenowy Zheng [Thu, 22 Jul 2021 06:30:03 +0000 (14:30 +0800)]
sunxi: decide the inclusion of SCP by SCP_ADDR existence
There are more Allwinner SoCs that do not have a SCP now.
When there's no SCP_ADDR macro defined, we can assume there's no SCP
available.
Drop the scp part of FIT description when SCP_ADDR does not exist.
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Mon, 19 Apr 2021 03:21:41 +0000 (22:21 -0500)]
sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2
So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure
monitor code (providing PSCI runtime services). And while those SoCs do
not have the secure SRAM B like older SoCs, there is enough (secure)
SRAM A2 to put the monitor code and data in there instead.
Follow the design of 64-bit SoCs and use the first part for the monitor,
and the last 16 KiB for the SCP firmware. With this change, the monitor
no longer needs to reserve a region in DRAM.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: amend commit message, fix R40 and V3s build]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Mon, 19 Apr 2021 03:16:21 +0000 (22:16 -0500)]
sunxi: Select environment MMC based on boot device
Currently, the environment is always stored in eMMC if eMMC is enabled
in the config. This means images written to SD and eMMC will cross-
contaminate their environments unless the configuration is changed.
By dropping the device number from the environment location string and
implementing mmc_get_env_dev, we will always use the environment from
the boot device when booting from SD/eMMC.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tom Rini [Sat, 31 Jul 2021 12:18:14 +0000 (08:18 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- kwboot / kwbimage improvements reducing image size (Pali & Marek)
- a37xx: pinctrl: Correct PWM pins definitions (Marek)
- Convert the Dreamplug Ethernet and SATA to Driver Model (Tony)
- serial: a37xx: DEBUG_UART improvements / fixes (Pali)
Pali Rohár [Mon, 26 Jul 2021 12:58:59 +0000 (14:58 +0200)]
serial: a37xx: Do not call get_ref_clk() in _debug_uart_init()
Static inline function _debug_uart_init() should avoid calling external
(non-inline) functions. Therefore do not call get_ref_clk() in
_debug_uart_init() and reimplement its functionality without external
function calls.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>