Kuldeep Singh [Wed, 22 Jul 2020 09:35:44 +0000 (15:05 +0530)]
configs: ls2088a: Restore CONFIG_ENV_ADDR to IFC-NOR
Restore CONFIG_ENV_ADDR value to fix boot hang with IFC-NOR
which is default boot source.
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Zhao Qiang [Tue, 14 Jul 2020 05:53:36 +0000 (13:53 +0800)]
arm: dts: ls1028a: Add dspi flash device node to qds
Add dspi flash device node to fsl-ls1028a-qds.dtsi
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Zhao Qiang [Fri, 10 Jul 2020 08:55:20 +0000 (16:55 +0800)]
configs: lx2160a: Enable Watchdog support
Enable support to compile SBSA driver.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Zhao Qiang [Fri, 10 Jul 2020 08:55:19 +0000 (16:55 +0800)]
arm64: lx2160a: dts: Add watchdog node
Add watchdog node which is sbsa into lx2160a dtsi
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Zhao Qiang [Fri, 10 Jul 2020 08:55:18 +0000 (16:55 +0800)]
Watchdog: introduce ARM SBSA watchdog driver
According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal
(WS0) is for alerting the system by interrupt, the second one (WS1) is a
real hardware reset.
More details about the hardware specification of this device:
ARM DEN0029B - Server Base System Architecture (SBSA)
This driver can operate ARM SBSA Generic Watchdog as a single stage
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Hou Zhiqiang [Thu, 9 Jul 2020 15:31:42 +0000 (23:31 +0800)]
pci: layerscape: Add specific config entry for RC and EP mode driver
Add Root Complex and Endpoint mode specific config entries, such that
it's feasible to enable the RC and/or EP mode driver indepently.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:41 +0000 (23:31 +0800)]
pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2
Add the PCIe EP mode support for lx2160a-v2 platform.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:40 +0000 (23:31 +0800)]
pci: layerscape: Modify the ls_pcie_dump_atu function
Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:39 +0000 (23:31 +0800)]
pci_ep: layerscape: Add the SRIOV VFs of PF support
Add the INBOUND configuration for VFs of PF.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:38 +0000 (23:31 +0800)]
pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode
Due to the ls2085a and ls2080a use different way to set the BAR size,
so add the BAR size init code here.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:37 +0000 (23:31 +0800)]
pci_ep: layerscape: Add the workaround for errata A-009460
The VF_BARn_REG register's Prefetchable and Type bit fields
are overwritten by a write to VF's BAR Mask register.
workaround: Before writing to the VF_BARn_MASK_REG register,
write 0b to the PCIE_MISC_CONTROL_1_OFF register.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:36 +0000 (23:31 +0800)]
pcie_ep: layerscape: Add the multiple function support
Add the multiple function support for Layerscape platform, some PEXs
of Layerscaple platform have more than one PF.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:35 +0000 (23:31 +0800)]
armv8: dts: ls1046a: Add the PCIe EP node
Add the PCIe EP node for ls1046a.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:34 +0000 (23:31 +0800)]
pci_ep: Add the init function
Some EP deivces need to initialize before RC scan it, e.g. NXP
layerscape platform, so add the init function in pci_ep uclass.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:33 +0000 (23:31 +0800)]
pci: layerscape: Split the EP and RC driver
Split the RC and EP driver, and reimplement the EP driver base on
the EP framework.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Wasim Khan [Thu, 9 Jul 2020 08:51:08 +0000 (14:21 +0530)]
arm: dts: lx2160a: Increase configuration window size
lx2160a rev2 requires 4KB space for type0 and 4KB
space for type1 iATU window. Increase configuration
size to 8KB to have sufficient space for type0
and type1 window.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Manish Tomar [Wed, 8 Jul 2020 09:25:03 +0000 (14:55 +0530)]
configs:ls1046afrwy: Add tfa secure boot defonfig
Add TFA secure boot defconfig and Enables secure boot related
configs in it.
Signed-off-by: Manish Tomar <manish.tomar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Thu, 2 Jul 2020 03:13:04 +0000 (11:13 +0800)]
freescale: ls1043aqds: drop ifdef CONFIG_SYS_I2C
- Drop ifdef CONFIG_SYS_I2C to initialize
baudrate of i2c
- Drop warning of i2c_early_init_f as follows,
warning: implicit declaration of function 'i2c_early_init_f'; did you
mean 'arch_early_init_r'? [-Wimplicit-function-declaration]
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Thu, 2 Jul 2020 03:13:03 +0000 (11:13 +0800)]
freescale: ls1043aqds: enable secure system counter
Enable secure system counter in board_early_init_f for udelay()
to fix a bug that always return 0 by timer_read_counter()
when boot from qspi(No TFA)
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Thu, 2 Jul 2020 03:13:02 +0000 (11:13 +0800)]
freescale: ls1046aqds: drop ifdef CONFIG_SYS_I2C
- Drop ifdef CONFIG_SYS_I2C to initialize
baudrate of i2c
- Drop warning of i2c_early_init_f as follows,
warning: implicit declaration of function 'i2c_early_init_f'; did you
mean 'arch_early_init_r'? [-Wimplicit-function-declaration]
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Thu, 2 Jul 2020 03:13:01 +0000 (11:13 +0800)]
freescale: ls1046aqds: enable secure system counter
Enable secure system counter in board_early_init_f for udelay()
to fix a bug that always return 0 by timer_read_counter()
when boot from qspi(No TFA)
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Thu, 2 Jul 2020 03:13:00 +0000 (11:13 +0800)]
i2c: mxc: move i2c_early_init_f to common function
Move i2c_early_init_f to common function
to initialize baudrate of i2c
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Sat, 27 Jun 2020 20:58:53 +0000 (22:58 +0200)]
crypto/fsl: add RNG support
Register the random number generator with the rng subsystem in u-boot.
This way it can be used by EFI as well as for the 'rng' command.
Signed-off-by: Michael Walle <michael@walle.cc>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Sat, 27 Jun 2020 20:58:52 +0000 (22:58 +0200)]
crypto/fsl: instantiate the RNG with prediciton resistance
If it is already instantiated tear it down first and then reinstanciate
it again with prediction resistance.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Sat, 27 Jun 2020 20:58:51 +0000 (22:58 +0200)]
crypto/fsl: don't regenerate secure keys
The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a
POR. Otherwise the RNG4 will throw an error.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Sat, 27 Jun 2020 20:58:50 +0000 (22:58 +0200)]
crypto/fsl: support newer SEC modules
Since Era 10, the version registers changed. Add the version registers
and use them on newer modules.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Sat, 27 Jun 2020 20:58:49 +0000 (22:58 +0200)]
crypto/fsl: export caam_get_era()
We need the era in other modules, too. For example, to get the RNG
version.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Sat, 27 Jun 2020 20:58:48 +0000 (22:58 +0200)]
crypto/fsl: make SEC%u status line consistent
Align the status line with all the other output in U-Boot.
Before the change:
DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
SEC0: RNG instantiated
WDT: Started with servicing (60s timeout)
After the change:
DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
SEC0: RNG instantiated
WDT: Started with servicing (60s timeout)
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Heinrich Schuchardt [Sat, 27 Jun 2020 08:13:55 +0000 (10:13 +0200)]
crypto/fsl: unused value in caam_hash_update()
The value 0 assigned to final is overwritten before ever being used.
Remove the assignment.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Heinrich Schuchardt [Sat, 27 Jun 2020 08:08:49 +0000 (10:08 +0200)]
crypto/fsl: correct printf() statement.
The sequence of arguments should match the format string.
For printing unsigned numbers we should use %u.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Hou Zhiqiang [Thu, 25 Jun 2020 14:23:53 +0000 (22:23 +0800)]
arm64: ls1043a: Remove the workaround of erratum A-009929
The workaround has been implemented in PBI phase, so remove
the duplicated implementation from U-Boot.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Thu, 25 Jun 2020 07:26:22 +0000 (12:56 +0530)]
configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN value
Previous attempt to increase CONFIG_SYS_MALLOC_LEN was done in commit
c084a8edf4e2 ("configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size")
which increased malloc memory to ~1M.
PFE firmware alone requires 3M of dynamic memory allocation and
therefore, increase the config value to a larger value i.e 5M. This size
should be enough as of now to accommodate further memory requirements.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Yangbo Lu [Wed, 17 Jun 2020 10:09:00 +0000 (18:09 +0800)]
configs: lx2160aqds: enable CONFIG_BOARD_EARLY_INIT_R
Enable CONFIG_BOARD_EARLY_INIT_R for SDHC adapter card
identification and configuration.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Yangbo Lu [Wed, 17 Jun 2020 10:08:59 +0000 (18:08 +0800)]
board: fsl: lx2160aqds: identify SDHC adapter during board init
Add support for SDHC adapter identification and configuration
during board init.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Yangbo Lu [Wed, 17 Jun 2020 10:08:58 +0000 (18:08 +0800)]
Move eSDHC adapter card identification to board files
The eSDHC adapter card identification and multiplexing configuration
through FPGA had been implemented in both common mmc driver and
fsl_esdhc driver. However it is proper to move these code to board
files and do it during board initialization. The FPGA registers are
also board specific.
This patch is to move eSDHC adapter card identification and
multiplexing configuration from mmc driver to specific board files.
And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
[Rebased, Removed T1040QDS change as board does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Yangbo Lu [Wed, 17 Jun 2020 10:08:57 +0000 (18:08 +0800)]
Drop global data sdhc_adapter for powerpc
The sdhc_adapter of global data has not been used, and we
do not have to use it as global data even we may need it
in the future.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Yuantian Tang [Wed, 10 Jun 2020 08:13:50 +0000 (16:13 +0800)]
armv8: ls1028ardb: add xspi parameter to qixis command
Add xspi boot source to qixis command to let the soc boot from
flex-nor flash chip.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Chaitanya Sakinam [Tue, 9 Jun 2020 10:51:48 +0000 (16:21 +0530)]
armv8: ls1012a: RGMII ports require internal delay
The correct setting for the RGMII ports on LS1012ARDB is to
enable delay on both Rx and Tx so the interface mode used should
be PHY_INTERFACE_MODE_RGMII_ID
Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Udit Agarwal [Mon, 8 Jun 2020 13:25:44 +0000 (18:55 +0530)]
include/configs: ls1012a: Remove fdt_high env variable
Remove "fdt_high" environment variable to use the bootm_size
to safely contain a kernel, device tree and initrd for
relocation.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Zhao Qiang [Mon, 8 Jun 2020 03:28:25 +0000 (11:28 +0800)]
config: lx2160/2a: enable dspi
Enable dspi in lx2160aqds tfa defconfig
Enable CONFIG_SPI_FLASH_SST/EON in config file.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Zhao Qiang [Mon, 8 Jun 2020 03:28:24 +0000 (11:28 +0800)]
armv8: dts: fsl-lx2160a: add flash node under dspi to qds dts
Add flash node under dspi into fsl-lx2160a-qds.dtsi
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Thu, 4 Jun 2020 19:05:33 +0000 (21:05 +0200)]
crypto/fsl: fix unaligned access
On aarch64 running with dcache off, will result in an unaligned access
exception:
=> dcache off
=> hash sha1 $kernel_addr_r 100
"Synchronous Abort" handler, esr 0x96000061
elr:
00000000960317d8 lr :
00000000960316a4 (reloc)
elr:
00000000fbd787d8 lr :
00000000fbd786a4
[..]
The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit
aligned pointer. Remove the unused u64 element from the union to drop
the minimal alignment to 32 bit. Also remove the union, because it is
no more needed.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Thu, 4 Jun 2020 10:42:14 +0000 (18:42 +0800)]
I2C: ls1043a, ls1046a: enable SYS_I2C_MXC
This enables SYS_I2C_MXC to fix a bug that
failed to boot from sd card with
image u-boot-with-spl-pbl.bin
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:36 +0000 (21:53 +0200)]
armv8: layerscape: rework spin table
There are two issues:
(1) The spin table doesn't convert the endianness of the jump address.
Although there is code for it, the result isn't used at all (x0).
(2) If something goes wrong, the function returns. But that doesn't
make sense at all.
Use the actual converted jump address as destination to fix. If
there is an error, jump to a trap loop. And rearrange the code exception
level switching code to make it smaller and clearer.
This reduces the size of the spin table code section from 696 bytes to
424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696
bytes to 632 bytes.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:35 +0000 (21:53 +0200)]
armv8: layerscape: relocate spin table if EFI_LOADER is enabled
On ARM64, a 64kb region is reserved for the runtime services code.
Unfortunately, this code overlaps with the spin table code, which also
needs to be reserved. Thus now that the code is relocatable, allocate a
new page from EFI, copy the spin table code into it, update any pointers
to the old region and the start the secondary CPUs.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:34 +0000 (21:53 +0200)]
armv8: layerscape: clean exported symbols in spintable.S
Add a new variable secondary_boot_code_start, which holds a pointer to
the start of the spin table code. This will help to relocate the code
section. While at it, move the size variable from the end to the
beginning so there is a common section for the variables. Remove any
other symbols.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:33 +0000 (21:53 +0200)]
armv8: layerscape: drop first .ltorg directive in spintable.S
Now that the spin table is in a separate module, this is no longer
necessary. Drop it.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:32 +0000 (21:53 +0200)]
armv8: layerscape: make wake_secondary_core_n() static
This function is not used outside the module. Make it static.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:31 +0000 (21:53 +0200)]
armv8: layerscape: simplify get_spin_tbl_addr() calls
There is no need to cast around. Assign the address to the local
variable and use it.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:30 +0000 (21:53 +0200)]
armv8: layerscape: remove determine_mp_bootpg()
Only the PowerPC architecture needs this function. Remove it.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:29 +0000 (21:53 +0200)]
armv8: layerscape: fix alignment for spin table
Fix the alignment so it will match the comments. The spin table has to
be 8 byte aligned, so ".align 3" is enough.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:28 +0000 (21:53 +0200)]
armv8: layerscape: load function pointer using ADR
Don't use LDR to load a pointer to a function. This will generate a
literal which cannot be relocated. Use ADR which is PC-relative and
therefore can easily be relocated.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:27 +0000 (21:53 +0200)]
armv8: layerscape: move spin table into own module
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary
CPUs are brought up in main u-boot. This will make it possible to only
compile the spin table code for the main u-boot and omit it in SPL.
This saves about 720 bytes in the SPL.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:26 +0000 (21:53 +0200)]
armv8: layerscape: properly use CPU_RELEASE_ADDR
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.
Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:25 +0000 (21:53 +0200)]
armv8: layerscape: pretty print info about SMP cores
Make the print of the starting address a debug output and pretty print
the info about online cores.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:24 +0000 (21:53 +0200)]
armv8: layerscape: fix spin-table support
Spin tables are broken with bootefi. This is because - in contrast to
the booti call chain - there is no call to smp_kick_all_cpus(). Due to
this missing call the secondary CPUs are never released from their "wait
for interrupt state", see secondary_boot_func() in lowlevel.S.
Originally, this "wait for interrupt" is there to make sure, the spin
table is cleared before the secondary cores read it for the first time.
But the boot flow for the layerscape architecture is different from
that. The CPUs are release from their BootROM _after_ U-Boot's
spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c.
Thus, there is no need to wait for this interrupt and no need for
kicking all cores on cpu_release. An atomic 64bit write to the
spin-table and a "sev" is sufficient.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Thu, 28 May 2020 06:12:53 +0000 (11:42 +0530)]
net: pfe_eth: Use spi_flash_read API to access flash memory
Current PFE firmware access spi-nor memory directly. New spi-mem
framework does not support direct memory access. So, let's use
spi_flash_read API to access memory instead of directly using it.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
hui.song [Wed, 20 May 2020 10:40:19 +0000 (18:40 +0800)]
dm: armv8: gpio: include <asm/arch/gpio.h> for fsl-layerscape
Enable the gpio feature on fsl-layerscape platform.
Signed-off-by: hui.song <hui.song_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
hui.song [Wed, 20 May 2020 10:40:18 +0000 (18:40 +0800)]
armv8: gpio: add gpio feature
add one struct mpc8xxx_gpio_plat to enable gpio feature.
Signed-off-by: hui.song <hui.song_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Era Tiwari [Fri, 15 May 2020 07:18:39 +0000 (12:48 +0530)]
configs: ls1088ardb: Add support for usb boot target
LS1088A-RDB has MMC, SCSI, DHCP as boot targets,
but the USB support was missing.
Add support for USB as Boot_targets_devices.
Signed-off-by: Era Tiwari <era.tiwari@nxp.com>
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Sat, 9 May 2020 23:20:11 +0000 (01:20 +0200)]
armv8: ls1028a: move FSL_LAYERSCAPE to kconfig
CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to
define it per board; the ls1028a_common.h is really board dependent and
only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE
when ARCH_LS1028A is selected.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Vladimir Oltean [Mon, 4 May 2020 08:24:26 +0000 (11:24 +0300)]
fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delays
Communication with some SPI slaves just won't cut it if these delays
(before the beginning, and after the end of a transfer) are not added to
the Chip Select signal.
These are a straight copy from Linux:
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
drivers/spi/spi-fsl-dspi.c
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Tom Rini [Fri, 24 Jul 2020 12:43:08 +0000 (08:43 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Fix SiFive HiFive Unleashed board booting failure problem.
- Enable SiFive fu540 PWM driver.
- Support SiFive fu540: SPI boot.
- Update OpenSBI used for RISC-V CI testing.
- Revert "riscv: Allow use of reset drivers".
- Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"".
- sysreset: syscon:
- Don't assume default value for offset and mask property.
- Support value property.
- qemu: Add syscon reboot and poweroff support.
- Fix SIFIVE debug serial dependency.
- Fix linking error when building u-boot-spl with no SMP support.
- AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg.
- Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi
- SiFive fu540 avoid using hardcoded ram base and size.
Tom Rini [Fri, 24 Jul 2020 12:42:06 +0000 (08:42 -0400)]
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"
This reverts commit
5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to
56d37f1c564107e27d873181d838571b7d7860e7.
Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/
711313649
Signed-off-by: Tom Rini <trini@konsulko.com>
Bin Meng [Mon, 20 Jul 2020 06:06:35 +0000 (23:06 -0700)]
ram: sifive: Avoid using hardcoded ram base and size
At present the SiFive FU540 RAM driver uses hard-coded memory base
address and size to initialize the DDR controller. This may not be
true when this driver is used on another board based on FU540.
Update the driver to read the memory information from DT and use
that during the initialization.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Bin Meng [Mon, 20 Jul 2020 06:06:34 +0000 (23:06 -0700)]
riscv: dts: hifive-unleashed-a00: Make memory node available to SPL
Make memory node available to SPL in prepration to updates to SiFive
DDR RAM driver to read memory information from DT.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Rick Chen [Fri, 17 Jul 2020 08:24:44 +0000 (16:24 +0800)]
riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc reg
Use fdtdec_get_addr_size_auto_noparent to read the "reg" property
instead of fdtdec_get_addr. This will increase the compatibility
of dtb parsing.
Signed-off-by: Rick Chen <rick@andestech.com>
Acked-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Leo Liang <ycliang@andestech.com>
Leo Yu-Chi Liang [Mon, 29 Jun 2020 08:27:28 +0000 (16:27 +0800)]
riscv: Fix linking error when building u-boot-spl with no SMP support
Switch off SMP support when building u-boot-spl would cause linking error as follow:
undefined reference to 'secondary hart relocate' and 'smp_call_function'.
Add macro to wrap up proper code region that needs SMP configuration on.
Signed-off by: Leo Liang <ycliang@andestech.com>
Cc: rick@andestech.com
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Michal Simek [Fri, 10 Jul 2020 10:41:13 +0000 (12:41 +0200)]
serial: Fix SIFIVE debug serial dependency
The commit
4cc24aeaf420 ("serial: Add missing Kconfig dependencies for
debug consoles") has added incorrect dependency for SIFIVE debug uart which
should depend on SIFIVE driver instead of PL01x.
Fixes:
4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Bin Meng [Tue, 23 Jun 2020 05:29:45 +0000 (22:29 -0700)]
riscv: qemu: Add syscon reboot and poweroff support
This adds syscon reboot and poweroff support to QEMU RISC-V.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Bin Meng [Tue, 23 Jun 2020 05:29:43 +0000 (22:29 -0700)]
sysreset: syscon: Support value property
Per the DT binding, <mask> and <value> property can have either one
or both, and if <value> is missing, <mask> should be used, which is
what current U-Boot sysreset_syscon driver supports.
This adds support to the <value> property to the driver, and <mask>
semantics is updated to really be a mask to the value if both exist.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Bin Meng [Tue, 23 Jun 2020 05:29:42 +0000 (22:29 -0700)]
sysreset: syscon: Don't assume default value for offset and mask property
Per the DT binding, <offset> is a required property. Let's abort
the probe if it is missing. For the <mask> property, current codes
assume a default value of zero, which is not correct either.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Bin Meng [Mon, 20 Jul 2020 03:06:46 +0000 (20:06 -0700)]
Revert "Revert "riscv: sifive: fu540: Add gpio-restart support""
This reverts commit
23da3c682a84a2ad67a67287979dd4f5259ff607.
Now the build failure of sifive_fu540_defconfig board has been fixed,
revert this "revert patch".
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Bin Meng [Mon, 20 Jul 2020 03:06:45 +0000 (20:06 -0700)]
Revert "riscv: Allow use of reset drivers"
This reverts commit
958a3f464c7f8ef7e10db9feb663e9e80445ce2f.
A more appropriate change below is already in mainline.
Commit
fd31e4fd184f ("riscv: Do not build reset.c if SYSRESET is on")
Revert this patch, so that U-Boot can be built successfully for
SiFive Fu540 board.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Bin Meng [Mon, 20 Jul 2020 03:52:23 +0000 (20:52 -0700)]
azure: gitlab: travis: Update OpenSBI used for RISC-V testing
Change to use OpenSBI release v0.8 generic platform images for QEMU
RISC-V CI testing for azure, gitlab and travis-ci.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Jagan Teki [Wed, 15 Jul 2020 10:09:03 +0000 (15:39 +0530)]
sifive: fu540: Enable SF distro bootcmd
Enable SPI flash(SF) distro boot command in Sifive FU540.
This distro boot will read the boot script at specific
location at the flash and start sourcing the same.
Included the SF device at the last of the target devices
list since all the rest of the devices on the list have
more possibility to boot the distribution due to the
size of the SPI flash is concern.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Jagan Teki [Wed, 15 Jul 2020 10:09:02 +0000 (15:39 +0530)]
sifive: fu540: Add boot flash script offset, size
HiFive-Unleashed-A00 has SPI flash with 32MiB size.
So, let's use the script offset at the end of 4K.
This way it cannot overlap any offsets being used
by software components in flash layout.
So, SF distrocmd will pick the script at desired
script address and run.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Jagan Teki [Wed, 15 Jul 2020 10:09:01 +0000 (15:39 +0530)]
sifive: fu540: Mark the default env as SPI flash
Mark the default U-Boot environment as SPI flash since
this is an on board flash device.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Jagan Teki [Wed, 15 Jul 2020 10:09:00 +0000 (15:39 +0530)]
env: Enable SPI flash env for SiFive FU540
SPI flash device on HiFive Unleashed has 32MiB Size.
This patch adds SPI flash environment after U-Boot proper
partition with a size of 128KiB.
SPI flash partition layout(32MiB):
0 - 34 : reserved for GPT header
35 - 39 : unused
40 - 2087 : loader1 (SPL, FSBL)
2088 - 10279 : loader2 (U-Boot proper, U-Boot)
10280 - 10535 : environment
10536 - 65494 : rootfs
65528 - 65536 : distro script
Note: the loader1 must start from 40th sector even though
there are 6 free sectors prior since 40th sector is nearest
flash sector boundary.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Jagan Teki [Wed, 15 Jul 2020 10:08:59 +0000 (15:38 +0530)]
sifive: fu540: Add Booting from SPI
Add booting from SPI for SiFive Unleashed board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Jagan Teki [Wed, 15 Jul 2020 10:08:58 +0000 (15:38 +0530)]
sifive: fu540: Add runtime boot mode detection
Add support to detect boot mode at runtime for
SiFive FU540 boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Pragnesh Patel [Fri, 29 May 2020 06:44:52 +0000 (12:14 +0530)]
riscv: sifive: fu540: Enable SiFive PWM driver
This patch enables SiFive PWM driver for the SiFive
Unleashed board.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Bin Meng [Mon, 20 Jul 2020 06:17:07 +0000 (23:17 -0700)]
riscv: Make SiFive HiFive Unleashed board boot again
Commit
40686c394e53 ("riscv: Clean up IPI initialization code")
caused U-Boot failed to boot on SiFive HiFive Unleashed board.
The codes inside arch_cpu_init_dm() may call U-Boot timer APIs
before the call to riscv_init_ipi(). At that time the timer register
base (e.g.: the SiFive CLINT device in this case) is unknown yet.
It might be the name riscv_init_ipi() that misleads people to only
consider it is related to IPI, but in fact the timer capability is
provided by the same SiFive CLINT device that provides the IPI.
Timer capability is needed for both UP and SMP.
Considering that the original refactor does have benefits, that it
makes the IPI code more similar to U-Boot initialization idioms.
It also removes some quite ugly macros. Let's do the minimal revert
instead of a complete revert, plus a fixes to arch_cpu_init_dm() to
consider the SPL case.
Fixes:
40686c394e53 ("riscv: Clean up IPI initialization code")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Leo Liang <ycliang@andestech.com>
Tom Rini [Thu, 23 Jul 2020 19:56:06 +0000 (15:56 -0400)]
Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm
binman support for FIT
new UCLASS_SOC
patman switch 'test' command
minor fdt fixes
patman usability improvements
Tom Rini [Thu, 23 Jul 2020 12:57:35 +0000 (08:57 -0400)]
Merge tag 'efi-2020-10-rc1-5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc1 (5)
The series provides bug fixes for:
* crash in OS when accessing UEFI variables
* returning from UEFI fit images to U-Boot
* error handling for variable services provided by OP-TEE
* error handling in EFI_FILE_PROTOCOL.Read()
* missing function documentation
The first patches needed to use intermediate certificates for
secure boot are added. (The rest of the series requires
updating sbsigntool in our CI systems.)
Logging is enabled in the bootefi command.
Tom Rini [Wed, 22 Jul 2020 15:30:52 +0000 (11:30 -0400)]
Merge tag 'u-boot-rockchip-
20200722' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New rk3326 board: Hardkernel Odroid Go2;
- Update board config and dts for RockPI 4/N8/N10;
- Update led boot on support for roc-rk3399-pc;
- Enable SPI Flash suppor for rk3328 rock64 board;
- Update rockchip pcie phy to use generic framework;
Jagan Teki [Tue, 21 Jul 2020 15:28:09 +0000 (20:58 +0530)]
rockchip: rock-p-n8/n10: Disable RAM_ROCKCHIP_DEBUG
Disable ram rockchip debug driver for ROCKPi N8/N10 boards
since we have verified ram in many instances with respective
U-Boot versions.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:28:08 +0000 (20:58 +0530)]
arm64: dts: rockchip: Add u-boot, spl-boot-order for ROCKPi N10
Add u-boot,spl-boot-order for ROCKPi N10, so-that it can able
to boot from eMMC and SDMMC in order.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:28:07 +0000 (20:58 +0530)]
rockchip: rock-pi-n10: Enable PCI/NVME
Enable PCI/NVME for M.2 Slot on RockPI-4 boards.
=> nvme info
Device 0: Vendor: 0x144d Rev: 4L1QCXB7 Prod: S35FNX0J623292
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (
250069680 x 512)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Suniel Mahesh [Tue, 21 Jul 2020 15:24:43 +0000 (20:54 +0530)]
rockchip: rock-pi-n8: Enable on board devices
Enable common on board devices for ROCKPi N8.
- USB 2.0 Host
- USB 2.0 OTG/Gadget
- HDMI Out
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Suniel Mahesh [Tue, 21 Jul 2020 15:24:42 +0000 (20:54 +0530)]
rockchip: evb_rk3288: Add console settings
Add console settings like stdin, stdout and stderr as
usbkbd and vidconsole respectively for evb-rk3288 targets.
This would certainly help to detect the attached video
devices (like HDMI) and print the console messages on display.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Suniel Mahesh [Tue, 21 Jul 2020 15:24:41 +0000 (20:54 +0530)]
rockchip: rock-pi-n10: Enable on board devices
Enable common on board devices for ROCKPi N10.
- USB 2.0 Host
- USB 3.0 Host
- USB 3.0 Gadget
- HDMI Out
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:24:40 +0000 (20:54 +0530)]
arm64: dts: rockchip: Add PCIe for RockPI N10
This patch adds support to enable PCIe for RockPI N10.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:24:39 +0000 (20:54 +0530)]
arm: dts: rockchip: Add HDMI out for RockPI N8/N10
This patch adds support to enable HDMI out for
N10 and N8 combinations SBCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:24:38 +0000 (20:54 +0530)]
ARM: dts: rockchip: Add USB for RockPI N8/N10
Radxa dalang carrier board has 2x USB 2.0 and 1x USB 3.0
ports.
This patch adds support to enable all these USB ports for
N10 and N8 combinations SBCs.
Note that the USB 3.0 port on RockPI N8 combination works
as USB 2.0 OTG since it is driven from RK3288.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:24:37 +0000 (20:54 +0530)]
ARM: dts: rockchip: Add usb host0 ohci node for rk3288
rk3288 and rk3288w have a usb host0 ohci controller.
Although rk3288 ohci doesn't actually work on hardware, but
rk3288w ohci can work well.
So add usb host0 ohci node in rk3288 dtsi and the quirk in
ohci platform driver will disable ohci on rk3288.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Suniel Mahesh [Tue, 21 Jul 2020 15:24:36 +0000 (20:54 +0530)]
arm: dts: rockchip: Sync rk3288 dtsi from linux
This sync has changes required to use HDMI CEC pin in U-Boot.
Sync dts from linux v5.8-rc5 commit:
"ARM: dts: rockchip: define the two possible rk3288 CEC pins"
(sha1:
838980dd04e994bf81cf104fa01ae60802146b39)
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:24:35 +0000 (20:54 +0530)]
ARM: dts: rockchip: Sync ROCKPi N8/N10 dts(i) from Linux
Sync ROCKPi N8/N10 dts(i) changes from Linux.
commit <
afd9eb880414> ("ARM: dts: rockchip: Add Radxa Rock Pi N8 initial
support")
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:06:04 +0000 (20:36 +0530)]
rockchip: roc-rk3399-pc: Set LED only during POR and pwr_key=y
ROC-RK3399-PC has specific set of configurations for
on-board led setup.
Due to easiness for user to know the state of the board
roc-rk339-pc board code will setup the low power led
on/off, and waiting for user to press power key and then
glow full power led.
All this needs to happen only during power-on-reset not
for soft reset or WDT.
Also, it is not a proper usage to ask the user to press
the Power key if the board connected remotely, so add
the environment variable 'pwr_key' to check as well.
So, user need to press Power key only
- during POR
- pwr_key=y
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 21 Jul 2020 15:06:03 +0000 (20:36 +0530)]
rockchip: Separate the reset cause from display cpuinfo
reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed.
Other than cpuinfo, reset cause can also be using during
bootcount for checking the specific reset cause and glow
the led based on the reset cause.
So, let's separate the reset cause code from cpuinfo, and
add a check to build it for rk3399, rk3288 since these two
soc are supporting reset cause as of now.
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>