Alyssa Rosenzweig [Sun, 3 Sep 2023 19:36:33 +0000 (15:36 -0400)]
asahi: Conditionally expose cube arrays
With =deqp. I don't want this exposed before geometry shaders since we run dEQP
(GLES) far more than Piglit (GL), and we need geometry shaders to get adequate
regression testing via dEQP-GLES.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 3 Sep 2023 19:22:51 +0000 (15:22 -0400)]
asahi: Handle linear 1D Arrays
Lowered to linear 2D Arrays, handle them like that. Fixes 1D Array case of
arb_shader_image_size-builtin.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 3 Sep 2023 19:22:22 +0000 (15:22 -0400)]
asahi: Forbid linear 1D Array images
Porbably a theoretical case, but these fall down the 2D path so better not allow
it at any rate.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Fri, 18 Aug 2023 23:05:36 +0000 (19:05 -0400)]
agx: Run opt_idiv_const after lowering texture
Shaves 10 instructions off the cube map array lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Fri, 18 Aug 2023 23:04:08 +0000 (19:04 -0400)]
agx: Lower coordinates for cube map array images
Annoyingly different from texture coordinates.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 17 Aug 2023 17:03:03 +0000 (13:03 -0400)]
agx: Handle cube arrays when clamping arrays
Need to adjust the component.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 20:27:08 +0000 (16:27 -0400)]
ail: Force page-alignment for layered attachments
When rendering to a layered depth/stencil attachment, we specify the layer
stride in pages. That means that depth/stencil targets must be page-aligned to
be rendered to correctly.
If we're merely sampling, not rendering, we do not need the extra alignment. So
we add a flag to handle this case so we keep passing the generated ail tests.
Fixes KHR-GLES31.core.texture_cube_map_array.color_depth_attachments
Similarly, we page-align colour attachments. I don't have a good theoretical
justification for this part, but it seems to be necessary and layered rendering
fails otherwise. Possibly the PBE requires page-aligned layers unconditionally?
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 17 Aug 2023 17:03:31 +0000 (13:03 -0400)]
asahi: Translate cube array dimension
Yet another enum.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 14:10:17 +0000 (10:10 -0400)]
agx: Add unit test for cmp+sel fusing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 13:45:06 +0000 (09:45 -0400)]
agx: Add unit test for if_cmp fusing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 14:19:19 +0000 (10:19 -0400)]
agx: Fuse compares into selects
This lets us save a LOT of instructions at the cost of increased register
pressure. However, on my shader-db, this is still coming out ahead since no
shaders are hurt for thread count/spills, and only 1/10 of the shaders helped
for instruction count are hurt for register pressure. The shaders most hurt
for pressure have very low pressure (7 -> 15 is the worst case) and you need a
certain number of registers to use a 4 source instruction at all. Analyzing the
hurt shaders, nothing concerns me too much ... this isn't as bad as I feared.
So I think at this point it's worth ripping off the bandage, given the massive
potential for instruction count win. This is a big improvement for some of the
shaders I'm working on for my $SECRET_PROJECT.
total instructions in shared programs: 1784943 -> 1775169 (-0.55%)
instructions in affected programs: 644211 -> 634437 (-1.52%)
helped: 3498
HURT: 38
Instructions are helped.
total bytes in shared programs:
11720734 ->
11643224 (-0.66%)
bytes in affected programs: 4370986 -> 4293476 (-1.77%)
helped: 3572
HURT: 36
Bytes are helped.
total halfregs in shared programs: 474094 -> 475165 (0.23%)
halfregs in affected programs: 12821 -> 13892 (8.35%)
helped: 65
HURT: 247
Halfregs are HURT.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 13:58:04 +0000 (09:58 -0400)]
agx: Fuse conditions into if's
Simple greedy thing that has the potential to inflate register pressure but
reduces instructions. Thanks to the recent loop work that turns if { break }
into while_icmp, this also implicitly handles fusing conditions into loops,
which is what actually prompted this.
Surprisingly, this helps register pressure on my shader-db (no change to thread
count), I guess by eliminating the boolean temps in case where the sources are
used multiple times.
total instructions in shared programs: 1786561 -> 1784943 (-0.09%)
instructions in affected programs: 128557 -> 126939 (-1.26%)
helped: 474
HURT: 13
Instructions are helped.
total bytes in shared programs:
11733236 ->
11720734 (-0.11%)
bytes in affected programs: 976034 -> 963532 (-1.28%)
helped: 521
HURT: 13
Bytes are helped.
total halfregs in shared programs: 474245 -> 474094 (-0.03%)
halfregs in affected programs: 1869 -> 1718 (-8.08%)
helped: 28
HURT: 7
Halfregs are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 13:44:51 +0000 (09:44 -0400)]
agx: Generate unfused comparison pseudo ops
So we can optimize them easier.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 13:40:54 +0000 (09:40 -0400)]
agx: Add pseudo-instructions for icmp/fcmp
Easier to optimize with.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 22:39:37 +0000 (18:39 -0400)]
agx: Only use nest by 1 for loops w/o continue
Apple doesn't do this, but it should be equivalent and it makes it easier to see
that we can use while_icmp for break_if_icmp in loops that don't use continue
(which Apple does do). So, the effect of this commit is to use while_icmp for
most breaks, which saves an instruction.
total instructions in shared programs: 1764199 -> 1764076 (<.01%)
instructions in affected programs: 24149 -> 24026 (-0.51%)
helped: 78
HURT: 0
Instructions are helped.
total bytes in shared programs:
11609306 ->
11608322 (<.01%)
bytes in affected programs: 164604 -> 163620 (-0.60%)
helped: 78
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 22:39:11 +0000 (18:39 -0400)]
agx: Add helper to determine if a NIR loop uses continue
We need to emit extra instructions to handle continues, but if we don't have
any, we can omit those.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 22:17:10 +0000 (18:17 -0400)]
agx: Omit while_icmp without continue
The only role of the while_icmp at the end of a NIR loop is to make continue
jumps work. If, after emitting the loop, we learn that there are no continues,
there is no need to insert a while_icmp since it would be a no-op anyway.
total instructions in shared programs: 1764311 -> 1764199 (<.01%)
instructions in affected programs: 26321 -> 26209 (-0.43%)
helped: 82
HURT: 0
Instructions are helped.
total bytes in shared programs:
11609978 ->
11609306 (<.01%)
bytes in affected programs: 178842 -> 178170 (-0.38%)
helped: 82
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 22:11:32 +0000 (18:11 -0400)]
agx: Omit push_exec at top level
In general, loops need a push_exec at the start for correctness. However, a
push_exec at the top level (non-nested) is a no-op, so we can omit and save a
few cycles.
total instructions in shared programs: 1764350 -> 1764311 (<.01%)
instructions in affected programs: 7339 -> 7300 (-0.53%)
helped: 36
HURT: 0
Instructions are helped.
total bytes in shared programs:
11610212 ->
11609978 (<.01%)
bytes in affected programs: 48638 -> 48404 (-0.48%)
helped: 36
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 21:01:54 +0000 (17:01 -0400)]
agx: Detect conditional breaks
Search for code like
if ... {
break
}
and replace with a break_if pseudo-instruction for optimized handling, since the
break_if lowering is better than the original code.
total instructions in shared programs: 1764596 -> 1764350 (-0.01%)
instructions in affected programs: 24540 -> 24294 (-1.00%)
helped: 78
HURT: 0
Instructions are helped.
total bytes in shared programs:
11611196 ->
11610212 (<.01%)
bytes in affected programs: 166458 -> 165474 (-0.59%)
helped: 78
HURT: 0
Bytes are helped.
shader-db probably understates the benefit here, since this optimizes the body
of loops.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 21:01:43 +0000 (17:01 -0400)]
agx: Use agx_first_instr
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 21:01:00 +0000 (17:01 -0400)]
agx: Add agx_first/last_instr helpers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 19:12:00 +0000 (15:12 -0400)]
agx: Add break_if_*cmp instructions
To faciliate break optimizations. We use a more efficient lowering than the
literal transition of the NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 18:57:44 +0000 (14:57 -0400)]
agx: Split nest instruction into begin_cf + break
We use it for two different things. Pseudo-instructions are cheap, split it up
for easier optimization passes. This also fixes the schedule classes.. we can
move the cf_begin around if we want, it's inert.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 18:52:40 +0000 (14:52 -0400)]
agx: Lower nest later
As part of pseudo op lowering. Simpler and will simplify control flow opts.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 21:12:04 +0000 (17:12 -0400)]
agx: Expand nest
For breaking out of deeper control flow.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 18:50:43 +0000 (14:50 -0400)]
agx: Lower pseudo-ops later
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 18:40:25 +0000 (14:40 -0400)]
agx: Remove logical_end instructions
They're more trouble than they're worth for us. They were originally lifted
unthinkingly from ACO, where I assume they're necessary for software CF
lowering, but they're just an inconvenient convenience for us. Remove em.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 3 Sep 2023 14:14:14 +0000 (10:14 -0400)]
asahi: Force translucency for ignored render targets
If we bound 4 render targets but we only write to 1 of them, the other 3 need
their contents preserved. This requires either properly configuring HSR to
implement colour masking (TODO) or using the big hammer of setting TRANSLUCENT.
This patch picks the latter for now.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sat, 2 Sep 2023 20:30:43 +0000 (16:30 -0400)]
agx: Lower pack_32_4x8_split
Fixes test_integer_ops integer_dot_product.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Fri, 1 Sep 2023 09:52:14 +0000 (18:52 +0900)]
asahi: Allow no16 flag for disk cache
The debug flags are already plumbed into driver_flags for the disk
cache, so we just need to actually allow some flags instead of bailing
out of the disk cache init.
We only care about no16 for production right now, and it's probably a
good idea to disable disk caching during most debug sessions, so
allowlist only that one.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:42:48 +0000 (15:42 +0900)]
driconf: Disable fp16 for browsers
There are way too many broken WebGL apps using the wrong precision
qualifiers, which causes anything from jittery geometry to complete
breakage (e.g. QuakeJS and other games).
In addition, a Firefox bug is breaking basic canvas rendering for the
same reason (mozilla bug #1845309).
Let's just disable fp16 for browsers. There is no hope of getting all
this broken stuff fixed.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:42:04 +0000 (15:42 +0900)]
asahi: Add and support the no_fp16 driconf flag
This is the driconf equivalent of our debug no16 flag, which disables
fp16 support to work around apps using bad GLSL precision qualifiers.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:40:27 +0000 (15:40 +0900)]
asahi: Add scaffolding for supporting driconf options
It's time to start using some of these, so add the required scaffolding
to be able to have driver-specific driconf handling for us.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:39:19 +0000 (21:39 +0900)]
asahi: Fix VDM pipeline field width
The lower bits have a special meaning, like on the other pipelines.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:36:43 +0000 (21:36 +0900)]
asahi: decode: Do not assert on buffer overruns
This kills the hypervisor, let's just print and return.
Also flush after decoding, so that if something else goes wrong at least
we get the logs up to that point.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:33:18 +0000 (21:33 +0900)]
asahi: decode: Implement VDM call/ret
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:32:44 +0000 (21:32 +0900)]
asahi: cmdbuf: Identify call/ret bits
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Fri, 1 Sep 2023 10:42:50 +0000 (19:42 +0900)]
asahi: Allocate staging resources as staging
We were never setting the flag, which made these resources
write-combine...
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sat, 15 Apr 2023 23:49:47 +0000 (19:49 -0400)]
agx: Schedule for register pressure
Since we register allocate in SSA, the number of registers required (register
demand) equals to the maximum number of simultaneous live values (register
pressure). So if we can reduce register pressure, we are guaranteed to reduce
register demand. Even an ineffective heuristic like randomly swapping
instructions can only reduce pressure as long as it's conservative.
This implements one such heuristic: in each block, schedule backwards, selecting
the free instruction that looks like it will reduce liveness the most. In other
words, the greedy algorithm to reduce register pressure. At the end of the
block, if we haven't actually reduced pressure, we bail. This isn't optimal, but
it's well-motivated and optimally handles special cases (like 0-source
instructions).
This is based on the scheduler I originally wrote for Mali.
In my Dolphin ubershader branch, this improved performance at native 4K by 10fps
(105fps->115fps) when I measured together with some other optimizations. On top
of my current next (which notably includes nir_opt_sink improvements), this
commit alone goes (53fps->54fps) which is considerably less impressive :-p
shader-db results are a win, but not as large as we might hope. Instruction
count win seems to be from the smaller live ranges being easier on RA (fewer
swaps / moves). The two shaders affected for thread count are from fifa mobile,
which go from 640 threads ->
1024 (full occupancy). In other words... this heuristic does an excellent job in
a small subset of shaders. The Dolphin ubershader win was real, though :~)
Note these shader-db wins are on top of a branch with the nir_opt_sink
improvements. Without that, the stats are much better... The schedulers have
some overlap, but they're better together.
total instructions in shared programs: 1766635 -> 1763496 (-0.18%)
instructions in affected programs: 445855 -> 442716 (-0.70%)
helped: 1963
HURT: 350
Instructions are helped.
total bytes in shared programs:
11597648 ->
11586924 (-0.09%)
bytes in affected programs: 3106230 -> 3095506 (-0.35%)
helped: 2003
HURT: 374
Bytes are helped.
total halfregs in shared programs: 504609 -> 481980 (-4.48%)
halfregs in affected programs: 138322 -> 115693 (-16.36%)
helped: 3405
HURT: 311
Halfregs are helped.
total threads in shared programs:
18839936 ->
18840704 (<.01%)
threads in affected programs: 1280 -> 2048 (60.00%)
helped: 2
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:12:46 +0000 (19:12 -0400)]
agx: Include schedule class in the opcode info
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:19:07 +0000 (19:19 -0400)]
agx: Add schedule-specialized get_sr variants
Some special registers imply scheduling constraints. We want to have a single
scheduling class per instruction in the IR, so fork off various get_sr variants
depending on what kind of SR we're reading, and validate that we use the right
kind.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:05:47 +0000 (19:05 -0400)]
agx: Annotate opcodes with a scheduling class
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 20 Aug 2023 17:43:38 +0000 (13:43 -0400)]
agx/validate: Print to stderr
Otherwise unusable.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 20 Aug 2023 17:10:43 +0000 (13:10 -0400)]
agx: Fix jmp_exec_none encoding
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 20:01:24 +0000 (16:01 -0400)]
asahi: Fixes for clang-warnings
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Christian Gmeiner [Thu, 24 Aug 2023 15:49:16 +0000 (17:49 +0200)]
agx/lower_address: Remove not used has_offset
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Christian Gmeiner [Thu, 24 Aug 2023 09:01:10 +0000 (11:01 +0200)]
agx/lower_address: Use intrinsics_pass
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Neal Gompa [Wed, 23 Aug 2023 17:02:37 +0000 (13:02 -0400)]
asahi: Fix 32-bit x86 build with correct data type for overflow error message
Currently, when building on 32-bit x86, we get compilation errors
due to data type mis-matches in the format string.
This should fix the issue.
Signed-off-by: Neal Gompa <neal@gompa.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Wed, 30 Aug 2023 09:13:56 +0000 (11:13 +0200)]
rusticl: enable asahi
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 10:21:33 +0000 (12:21 +0200)]
rusticl/memory: fallback if allocating linear images fails
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 09:57:02 +0000 (11:57 +0200)]
asahi: handle images in is_format_supported
Some frontends differentiate between textures and images more explicitly
than st/mesa. So we might end up with PIPE_BIND_SHADER_IMAGE but not
PIPE_BIND_SAMPLER_VIEW in is_format_supported.
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 09:52:50 +0000 (11:52 +0200)]
asahi: gracefully handle allocating linear images
Frontends might try to allocate linear textures or images, we should
gracefully return NULL so frontends can do fallback paths.
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Wed, 30 Aug 2023 09:21:13 +0000 (11:21 +0200)]
asahi: implement clear_buffer
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 3 Feb 2023 17:42:50 +0000 (18:42 +0100)]
asahi: implement set_global_binding
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 12:53:56 +0000 (14:53 +0200)]
asahi: implement get_compute_state_info
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 18:33:42 +0000 (20:33 +0200)]
asahi: handle load_global_invocation_id_zero_base
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 15:09:14 +0000 (17:09 +0200)]
asahi: handle load_workgroup_size
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 13:02:41 +0000 (15:02 +0200)]
asahi: handle kernels
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 22:51:11 +0000 (00:51 +0200)]
asahi: lower hadd
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 3 Feb 2023 17:42:36 +0000 (18:42 +0100)]
asahi: fetch available system memory
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Connor Abbott [Fri, 25 Aug 2023 10:47:29 +0000 (12:47 +0200)]
vk/graphics_state: Fix copying MS locations pipeline state
Copying the state below overwrote the ms.sample_locations we set,
so our new_sample_locations was never actually used and we were
accidentally doing a shallow copy. Turnip passes a stack-allocated
old_state, so this resulted in invalid stack pointers.
Fixes:
f497cc9d56e ("vk/graphics_state: Add helpers for pre-baking state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25031>
Eric Engestrom [Mon, 4 Sep 2023 11:40:18 +0000 (12:40 +0100)]
ci: skip containers & build jobs when disabling a farm
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25032>
Danylo Piliaiev [Fri, 14 Jul 2023 14:41:48 +0000 (16:41 +0200)]
tu/a7xx: Disable LRZ
Even with GMEM disabled LRZ is still interacted with in some cases.
So it has to be completely disabled until it is fixed.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 10 Jul 2023 13:07:39 +0000 (15:07 +0200)]
tu/a7xx: Fix CmdDrawIndirectByteCountEXT
On a7xx DI_SRC_SEL_AUTO_INDEX is used instead of DI_SRC_SEL_AUTO_XFB.
On a7xx the counter value and offset are shifted right by 2, so
the vertexStride should also be in units of dwords.
CTS doesn't test this though.
Fixes:
dEQP-VK.transform_feedback.simple.draw_indirect_*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 4 Jul 2023 13:11:58 +0000 (15:11 +0200)]
tu/a7xx: Fix 3d blits after multiview usage
Fixes cts tests:
dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Thu, 22 Jun 2023 10:30:42 +0000 (12:30 +0200)]
tu/a7xx: Fix occlusion query
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Mark Collins [Tue, 6 Jun 2023 10:27:20 +0000 (10:27 +0000)]
tu/a7xx: Adapt r3d blits for A7xx
As r3d_ops emits sysmem draws directly, it needs to be manually
updated to emit the A7XX commands instead of A6XX.
VK-CTS tests success on A630 + A740:
dEQP-VK.api.copy_and_blit.core.blit_image.*
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 31 May 2023 12:29:41 +0000 (14:29 +0200)]
tu/a7xx: Fix flat shading
dEQP-VK.rasterization.flatshading.* are passing.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 30 May 2023 13:03:23 +0000 (15:03 +0200)]
tu/a7xx: Fix multiview
dEQP-VK.multiview.* mostly works, fails seem to be caused by lack of
3d blits.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 30 May 2023 13:02:28 +0000 (15:02 +0200)]
tu/a7xx: Fix tesselation shaders
dEQP-VK.tessellation.* are passing now.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 30 May 2023 13:00:43 +0000 (15:00 +0200)]
tu/a7xx: Fix geometry shaders
dEQP-VK.geometry.* are passing now
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 23 May 2023 16:44:58 +0000 (18:44 +0200)]
freedreno/fdl: Set LOSSLESSCOMPEN for image when ubwc is enabled on a7xx
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 19 Apr 2023 17:18:13 +0000 (19:18 +0200)]
tu: Basic a7xx support
Works:
- sysmem rendering
Doesn't work:
- gmem rendering
- 3d blits
- TESS and GS
Wild Life Extreme benchmarks runs without issues, most Sascha Willems
Vulkan demos are working.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 19 Apr 2023 17:05:00 +0000 (19:05 +0200)]
tu/common: Generalize TU_GENX macro
Now it doesn't require generated macro.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 3 May 2023 17:32:20 +0000 (19:32 +0200)]
ir3/a7xx: Disable shared consts for a7xx
a7xx introduced a new way to upload shared consts with old one
becoming unavailable, use fallback mechanism until we implement
the new shared consts.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 3 May 2023 17:27:45 +0000 (19:27 +0200)]
ir3/a7xx: Use ccinv for data synchronization
Fixes a lot of tests in dEQP-VK.memory_model.* e.g.:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.buffer.guard_local.buffer.comp
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 3 May 2023 17:25:06 +0000 (19:25 +0200)]
ir3/a7xx: Add ccinv instruction
_Presumably_ invalidates workgroup-wide cache for image/buffer data access.
so while "fence" is enough to synchronize data access inside a workgroup,
for cross-workgroup synchronization we have to invalidate that cache.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 24 Apr 2023 14:39:44 +0000 (16:39 +0200)]
ir3/a7xx: insert lock/unlock at the end of every compute shader
Add (ss)(sy) in all cases until.
TODO: Set sync flags depending on real need.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 19 Apr 2023 17:08:00 +0000 (19:08 +0200)]
ir3/a7xx: Don't multiply global mem instruction's offset by 4
a7xx global memory instructions don't have implied shift.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 3 May 2023 17:39:46 +0000 (19:39 +0200)]
ir3/a7xx: cat5 mode1 has swapped tex/samp ids
Though blob is not seen to even use mode1 on a740, it uses
S2EN variant instead.
Fixes:
dEQP-VK.binding_model.descriptor_buffer.multiple.*
dEQP-VK.binding_model.descriptor_buffer.embedded_imm_samplers.*
dEQP-VK.pipeline.monolithic.descriptor_limits.compute_shader.*
Adapted from Jonathan Marek's changes.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 9 Jun 2023 10:58:55 +0000 (12:58 +0200)]
isaspec: Make possible to obtain gpu_id in <expr> blocks
Done with ISA_GPU_ID() macro. This makes possible to use
gpu generation in to select between overrides.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 17 Apr 2023 13:39:09 +0000 (15:39 +0200)]
freedreno/computerator: Fix remaining issues with A7XX
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 4 Sep 2023 15:53:09 +0000 (17:53 +0200)]
ir3/tests: Use fd_dev_info to infer GPU generation
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 17 Apr 2023 13:38:00 +0000 (15:38 +0200)]
freedreno: Fully define a730 and a740 device properties
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 2 May 2023 11:26:06 +0000 (13:26 +0200)]
freedreno: Add a list of raw magic regs
The set of magic regs is different between generations and even
sub-gens. Adding a new one and/or emitting one on specific generation
takes much more code than necessary. Doing this in a single place is
much nicer.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 11 Aug 2023 13:30:47 +0000 (15:30 +0200)]
freedreno/registers: Generate python files with reg offsets
This would allow us to use register names in python scripts.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 11 Aug 2023 13:10:59 +0000 (15:10 +0200)]
freedreno/registers: Refactor gen_header.py to allow more options
We want it to also generate .py files with reg definitions.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Lionel Landwerlin [Sat, 2 Sep 2023 15:53:13 +0000 (18:53 +0300)]
intel/nir: rerun lower_tex if it lowers something
nir_lower_tex can lower tg4 coords into tg4 offset which on DG2+ we
also need to lower into constant offsets.
Unfortunately the nir_lower_tex pass is not able to lower the
instructions it itself generates, so the easy fix for when
nir_lower_tex lowers tg4 coords into tg4 offsets is to rerun the pass.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9735
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25015>
Vlad Schiller [Mon, 21 Aug 2023 05:34:36 +0000 (06:34 +0100)]
pvr: Implement VK_KHR_format_feature_flags2
This commit will implement and set VK_KHR_format_feature_flags2
instead of the old ones.
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24929>
Samuel Pitoiset [Wed, 30 Aug 2023 12:08:09 +0000 (14:08 +0200)]
radv/amdgpu: do not copy the original chain link for IBs
Otherwise, if a secondary CS is grown and then executed without IB2,
the INDIRECT_BUFFER packet would have been copied but it shouldn't.
This fixes a regression that introduced GPU hangs with
gl_vk_meshlet_cadscene on RDNA2.
Fixes:
df0c742543d ("radv/amdgpu: rework growing a CS with the chained IB path slightly")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
Samuel Pitoiset [Fri, 25 Aug 2023 15:26:30 +0000 (17:26 +0200)]
radv/amdgpu: fix executing secondaries without IB2
If a secondary cmdbuf has been grown and is executed without IB2
(eg. on compute queue or when it's not allowed), the ib size ptr
contains chaining info, which means the IB size was wrong.
This fixes CPU crashes when running gl_vk_meshlet_cadscene.
Fixes:
277b2afd708 ("radv/amdgpu: add support for executing DGC cmdbuf with RADV_DEBUG=noibs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
Lionel Landwerlin [Fri, 11 Aug 2023 09:19:28 +0000 (12:19 +0300)]
intel/measure: track batch buffer sizes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Lionel Landwerlin [Fri, 11 Aug 2023 09:14:32 +0000 (12:14 +0300)]
anv: reuse cmd_buffer::total_batch_size
This was left unused after
624ac55721 ("anv: move total_batch_size to
anv_batch"). We're now going to use it to store the total amount of
commands written in a command buffer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Lionel Landwerlin [Fri, 11 Aug 2023 09:04:18 +0000 (12:04 +0300)]
anv: rename total_batch_size
This name is confusing, the real thing it represents is the allocated
amount of batch space.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Chris Spencer [Tue, 29 Aug 2023 19:26:20 +0000 (20:26 +0100)]
anv/android: Enable shared presentable image support
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24941>
Chris Spencer [Tue, 29 Aug 2023 21:16:45 +0000 (22:16 +0100)]
android: Add explanatory comment to u_gralloc
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24941>
Dmitry Osipenko [Fri, 1 Sep 2023 00:36:15 +0000 (03:36 +0300)]
util/cache_test: Add test for get/put() with disabled cache
The disk_cache_create() now always returns valid cache even when disk
cache is disabled. In a case of disabled cache, the disk cache is NO-OP.
Test whether get/put() work as expected for the disabled cache.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dmitry Osipenko [Fri, 1 Sep 2023 00:13:11 +0000 (03:13 +0300)]
util/cache_test: Fix disabled cache test using SHADER_CACHE_DISABLE_BY_DEFAULT
Previous commit decoupled EGL_ANDROID_blob_cache from the disk cache
and haven't updated the SHADER_CACHE_DISABLE_BY_DEFAULT test-case that
is failing because now cache is always created even if disk cache is
disabled, such cache is NO-OP in this case. Fix the failing test.
Fixes:
39f26642 ("util: Decouple disk cache from EGL_ANDROID_blob_cache")
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dmitry Osipenko [Fri, 1 Sep 2023 00:03:22 +0000 (03:03 +0300)]
util/cache_test: Re-add test for disabled cache
Test for disabled cache was removed when we decoupled
EGL_ANDROID_blob_cache from the disk cache because test was failing
since it became outdated. Add the updated test.
Fixes:
39f26642 ("util: Decouple disk cache from EGL_ANDROID_blob_cache")
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dave Airlie [Wed, 30 Aug 2023 01:56:56 +0000 (11:56 +1000)]
llvmpipe/cs: further cleanups after tgsi removal.
These was still a few more places that could be polished better.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25045>