Ye Li [Sat, 7 Aug 2021 08:00:48 +0000 (16:00 +0800)]
arm: imx8ulp: Enable full L2 cache in SPL
SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.
So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:47 +0000 (16:00 +0800)]
arm: imx8ulp: soc: Change to use CMC1 to get bootcfg
CMC1 also has a MR register for bootcfg
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:46 +0000 (16:00 +0800)]
drivers: mmc: fsl_esdhc_imx: support i.MX8ULP
i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:45 +0000 (16:00 +0800)]
arm: imx8ulp: add clock support
Add i.MX8ULP clock support
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:44 +0000 (16:00 +0800)]
driver: serial: fsl_lpuart: support i.MX8ULP
i.MX8ULP lpuart has same register layout as i.MX7ULP and i.MX8
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:43 +0000 (16:00 +0800)]
pinctrl: Add pinctrl driver for imx8ulp
Add pinctrl driver for i.MX8ULP
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:42 +0000 (16:00 +0800)]
net: fec_mxc: support i.MX8ULP
Support i.MX8ULP in fec_mxc
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Ye Li [Sat, 7 Aug 2021 08:00:41 +0000 (16:00 +0800)]
driver: misc: Add MU and S400 API to communicate with Sentinel
Add MU driver and S400 API. Need enable MISC driver to work
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:40 +0000 (16:00 +0800)]
arm: imx: move container Kconfig under mach-imx
Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig
public to both.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:39 +0000 (16:00 +0800)]
arm: imx8ulp: add container support
i.MX8ULP support using ROM API to load container image,
it use same ROM API as i.MX8MN/MP, and use same container format
as i.MX8QM/QXP.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:38 +0000 (16:00 +0800)]
arm: imx: parse-container: guard included header files
Guard included sci.h with CONFIG_AHAB_BOOT to avoid build failure
for i.MX8ULP
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:37 +0000 (16:00 +0800)]
arm: imx8: Move container image header file to mach-imx
Since the container is shared among i.MX platforms, move its header file
to mach-imx
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:36 +0000 (16:00 +0800)]
arm: imx8: Move container parser and image to mach-imx common folder
Since we will re-use the container parser on imx8ulp, move the codes
to mach-imx
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:35 +0000 (16:00 +0800)]
arm: imx: basic i.MX8ULP support
Add basic i.MX8ULP support
For the MMU part, Using a simple way the calculate the MMU size to avoid
default heavy calcaulation. And align address and size in the table
settings to 2MB or 4GB as much as possible. So we can reduce the 4K page
allocations in MMU table which will spends much time in create the
page table
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:34 +0000 (16:00 +0800)]
imx: imx8ulp: add get reset cause
Add get reset cause function to show what triggerred reset.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:33 +0000 (16:00 +0800)]
arm: imx8ulp: support print cpu info
Support print cpu info. the clock function has not been added, it will
be added in following patches.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:32 +0000 (16:00 +0800)]
arm: imx: sys_proto: move boot mode define to common header
These defines could be reused by i.MX8ULP, so move them
to common header.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:31 +0000 (16:00 +0800)]
arm: imx: add i.MX8ULP cpu type and helper
Add i.MX8ULP cpu type and helpers.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:30 +0000 (16:00 +0800)]
arm: imx: add i.MX8ULP basic Kconfig option
Add i.MX8ULP related basic Kconfig option, which will be used later.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:40 +0000 (15:19 -0700)]
board: gateworks: venice: add board model to dt
Add the specific board model from EEPROM config to the device-tree to
make it easier to access from Linux userspace.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:33 +0000 (15:19 -0700)]
configs: imx8mm_venice_defconfig: remove unused SPL features
remove unused SPL features to shink the size of the SPL which
otherwise would no longer fit into IMX8M Mini OCRAM.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Fabio Estevam [Thu, 18 Feb 2021 02:39:28 +0000 (23:39 -0300)]
mx28evk: Convert to driver model
Make the conversion to driver model as it is mandatory.
Successfully tested booting Linux from the SD card.
Dropped support for networking and splash screen as these need
to be properly converted to DM and tested.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Sebastian Reichel [Wed, 4 Aug 2021 16:22:54 +0000 (18:22 +0200)]
board: ge: bx50v3: Add PCIe reset to DT
Add PCIe reset gpio to the Bx50v3 devicetree and get get rid of
CONFIG_PCIE_IMX_PERST_GPIO.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Fabio Estevam [Fri, 30 Jul 2021 00:24:58 +0000 (21:24 -0300)]
mx7dsabresd: Select CONFIG_IMX_HAB
Select CONFIG_IMX_HAB so that the "hab_status" command
becomes available, which is useful for checking if the
chip has been correctly setup to run in secure boot mode.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:41 +0000 (15:19 -0700)]
board: gateworks: venice: add imx8mm-gw7902 support
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- LTE CAT M1 modem
- USB 2.0 HUB
- M.2 Socket with USB2.0, PCIe, and dual-SIM
- IMX8M FEC
- PCIe based GbE
- RS232/RS485/RS422 serial transceiver
- GPS
- CAN bus
- WiFi / Bluetooth
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- PMIC
Do the following to add support for it:
- add dts
- add PMIC config
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:39 +0000 (15:19 -0700)]
board: gateworks: venice: add board model/serial# to env
Add board model/serial# strings to env. Move the creation of the strings
to gsc_read() and the display of the info into gsc_info() so they are
available to U-Boot proper.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:38 +0000 (15:19 -0700)]
board: gateworks: venice: use bus numbers vs names
replace looking up i2c bus name by bus number and define bus numbers and
eeprom address with #defines.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:37 +0000 (15:19 -0700)]
board: gateworks: venice: get mem size from dt
Get mem size from dt which SPL updated per EEPROM config.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:36 +0000 (15:19 -0700)]
arm: dts: imx8mm-venice-gw7901: use common u-boot dtsi
Use the common imx8mm-u-boot.dtsi
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:35 +0000 (15:19 -0700)]
arm: dts: imx8mm-venice-gw700x: fix fifo-depth phy props
Replace the deprecated 'tx-fifo-depth' and 'rx-fifo-depth' properties
not supported by U-Boot drivers/net/phy/dp83867.c with the proper
'ti,fifo-depth' property.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Tue, 27 Jul 2021 22:19:34 +0000 (15:19 -0700)]
arm: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12
is the power-enable to the TPS25821 Source controller and power switch
responsible for monitoring the CC pins and enabling VBUS. Therefore
GPIO1_12 must always be enabled and the vbus output enable from the
IMX8MM can be ignored.
To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the
TPS25821 and change the regulator output to GPIO1_10 which is
unconnected.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Fabio Estevam [Mon, 26 Jul 2021 19:01:48 +0000 (16:01 -0300)]
warp: Use the correct symbol for CONFIG_IMX_HAB
The intention of commit
d714a75fd4dc ("imx: replace CONFIG_SECURE_BOOT
with CONFIG_IMX_HAB") was to convert from CONFIG_SECURE_BOOT to
CONFIG_IMX_HAB, but it replaced with an extra "_" character.
Fix it by using the correct CONFIG_IMX_HAB symbol.
Fixes:
d714a75fd4dc ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:46 +0000 (10:40 -0700)]
imx: ventana: add support for GW54xx-G revision
The GW54xx-G revision has the foolowing changes:
- replaces the EOL GbE PHY with an updated part (requires an enable pin)
- replaces the EOL analog video decoder with an updated part
(requires dt prop)
- add power control to miniPCIe socket
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:45 +0000 (10:40 -0700)]
imx: ventana: add support for GW53xx-G revision
The GW53xx-G revision has the foolowing changes:
- replaces the EOL GbE PHY with an updated part (requires an enable pin)
- replaces the EOL analog video decoder with an updated part
(requires dt prop)
- add power control to miniPCIe socket
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:44 +0000 (10:40 -0700)]
imx: ventana: add GW5913 support
The GW5913 is a Single Board Computer based on the NXP i.MX6Q/DL SoC
with the following features:
- DDR3 DRAM
- NAND FLASH (256MiB or 2048MiB)
- Gateworks System Periperhal Controller
- front panel LED's
- front panel pushbutton
- Digital I/O connector (I2C/GPIO/UART)
- u-blox Zoe-M8Q GPS
- 1x RJ45 GbE
- 1x MiniPCIe socket with PCIe USB 2.0 and nanoSIM socket
- Passive PoE and wide-range DC power supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:43 +0000 (10:40 -0700)]
imx: ventana: add GW5912 support
The GW5912 is a Single Board Computer based on the NXP i.MX6Q/DL SoC
with the following features:
- DDR3 DRAM
- NAND FLASH (256MiB or 2048MiB)
- microSD socket
- Gateworks System Periperhal Controller
- front panel LED's
- front panel pushbutton
- RS232 connector (2x UARTs)
- CAN/RS485 connector
- Digital I/O connector (I2C/GPIO)
- SPI connector
- u-blox Zoe-M8Q GPS
- LIS2DE12 Accellerometer
- 1x FEC GbE RJ45 with 802.3at Active PoE
- 1x PCI GbE RJ45 with Passive PoE
- 5x MiniPCIe socket with PCIe/USB 2.0
- 1x MiniPCIe socket with PCIe/USB 2.0 and SIM socket
- Aux power input with wide-range DC power supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:42 +0000 (10:40 -0700)]
imx: ventana: add GW5910 support
The GW5910 is a Single Board Computer based on the NXP i.MX6Q/DL SoC
with the following features:
- DDR3 DRAM
- NAND FLASH (256MiB or 2048MiB)
- microSD socket
- Gateworks System Periperhal Controller
- front panel LED's
- front panel pushbutton
- RS232 connector (2x UARTs)
- Digital I/O connector (I2C/GPIO)
- SPI connector
- u-blox Zoe-M8Q GPS
- LIS2DE12 Accellerometer
- TI CC1352 ARM Cortex-M4 multiprotocol sub-1GHz / 2.4GHz wireless MCU
- On-board brcmfmac WiFi and BT module
- RGMII RJ45 GbE
- 1x MiniPCIe socket with PCIe/USB 2.0
- 1x MiniPCIe socket with USB 2.0 and nanoSIM socket
- Passive PoE and wide-range DC power supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:41 +0000 (10:40 -0700)]
imx: ventana: use dt for hwmon
Use dt-bindings for GSC hwmon devices.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:40 +0000 (10:40 -0700)]
imx: ventana: remove hard-coded flexcan standby pin
Flexcan pinmux is configured in kernel dt.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:39 +0000 (10:40 -0700)]
imx: ventana: remove hard-coded analog video codec enable
Analog video codec enable is configured in kernel dt.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:38 +0000 (10:40 -0700)]
imx: ventana: remove hard-coded USB OTG pinmux
pinmux is now done via dt. Add missing OTG_OC pinmux for boards that
use it.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:37 +0000 (10:40 -0700)]
imx: ventana: remove hard-coded PCI reset
PCIe reset configuration is handled via dt now.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:36 +0000 (10:40 -0700)]
imx: ventana: fix UMS support
The Gateworks Ventana boards have always had usb0=usbh1 and usb1=usbotg
because OTG is often subloaded on these boards and a bit in the EEPROM
which flagging that OTG is subloaded is used to remove the dt node via the
alias.
U-Boot DM_USB UMS requires the usb0 alias be assigned to the usbotg
so fix the usb0 alias in order for UMS to work.
Fixes
72c46327f03f: ("imx: ventana: enable dm support for USB")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:35 +0000 (10:40 -0700)]
imx: ventana: remove hard-coded USB HUBRST# gpio config
The USB HUB reset is handled via dt now.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:34 +0000 (10:40 -0700)]
imx: ventana: replace hard-coded LED config with dt based config
Use device-tree LED config instead of hard-coded board-specific config.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:33 +0000 (10:40 -0700)]
imx: ventana: remove nand field from common ventana struct
NAND fdt fixups can be performed without knowing if NAND is present.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:32 +0000 (10:40 -0700)]
imx: ventana: move wdog/uhs-i board/revision dt fixups
Move board/revision specific dt fixups for WDOG and UHS-I features
so that we can call them early for U-Boot control dt as well.
Additionally drop a deprected non-mainline dt-prop fixup regarding
HDMI input format.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 24 Jul 2021 17:40:31 +0000 (10:40 -0700)]
imx: ventana: ignore EEPROM config when checking for NAND support
EEPROM bits no longer indicate support for NAND so instead use
hard-coded value from board config struct.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Oleksandr Suvorov [Fri, 23 Jul 2021 06:39:49 +0000 (09:39 +0300)]
board: colibri_vf: fix compiling warning
This patch fixes the following compiler warning:
=============
board/toradex/colibri_vf/colibri_vf.c: In function 'ft_board_setup':
board/toradex/colibri_vf/colibri_vf.c:436:6: warning: unused variable 'ret' [-Wunused-variable]
=============
Fixes:
be3f1a56bf8 ("video: fsl_dcu_fb: add DM_VIDEO support")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Ming Liu [Fri, 23 Jul 2021 06:39:48 +0000 (09:39 +0300)]
board: colibri_imx6: add board_fit_config_name_match to support FIT in SPL
Only one dtb is currently supported, so match with imx6-colibri.
Signed-off-by: Ming Liu <ming.liu@toradex.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Oleksandr Suvorov [Fri, 23 Jul 2021 06:39:47 +0000 (09:39 +0300)]
board: colibri-imx8x: update building documentation
Update the documentation on how to build the u-boot image for
Colibri iMX8QXP, adding support of V1.0D revision of the module.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Stefan Agner [Fri, 23 Jul 2021 06:39:46 +0000 (09:39 +0300)]
board: toradex: make USB PID from config block optional
If config block support is enabled, USB gadget modes unconditionally
use Toradex Product ID as USB PID. Some applications might prefer a
different and/or static USB PID. Add a Kconfig configuration option
to descide whether to use USB PID from config block or the fallback
config option CONFIG_G_DNL_PRODUCT_NUM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Stefan Agner [Fri, 23 Jul 2021 06:39:45 +0000 (09:39 +0300)]
board: colibri_imx7: use SDP if USB serial downloader has been used
In case USB serial downloader has been used to load U-Boot start the
serial download protocol (SDP) emulation. This allows to download
complete images such as Toradex Easy Installer over USB SDP as well.
This code uses the boot ROM provided boot information to reliably
detect USB serial downloader.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Fabio Estevam [Mon, 19 Jul 2021 20:15:14 +0000 (17:15 -0300)]
mx6cuboxi: Fix the console variable
Do not pass the console baudrate to the 'console' variable
to avoid the baudrate being passed twice when extlinux.conf
contains the standard: console=${console},${baudrate} format.
cat /proc/cmdline
root=PARTUUID=
00000000-01 rootwait rw console=ttymxc0,115200,115200
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Fabio Estevam [Mon, 19 Jul 2021 20:15:13 +0000 (17:15 -0300)]
mx6cuboxi: Fix the mmc device for the rootfs
After the conversion to DM_MMC, the rootfs becomes mmc 1, so
adjust it accordingly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Fabio Estevam [Thu, 18 Feb 2021 02:39:27 +0000 (23:39 -0300)]
imx28-evk: Import devicetree file from Linux
Import the imx28-evk devicetree files from Linux kernel
version 5.11-rc7.
This is in preparation for converting the mx28evk_defconfig
target to driver model.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tom Rini [Thu, 5 Aug 2021 01:18:33 +0000 (21:18 -0400)]
Merge branch '2021-08-04-assorted-minor-fixes'
- Assorted fixes
Adarsh Babu Kalepalli [Mon, 24 May 2021 08:05:39 +0000 (13:35 +0530)]
cmd:(cosmetic)Mentioned in 'chpart' command HELP text that it is for MTD devices
Modified the help text of 'chpart' command ,mentioning that it is
for MTD devices.
Signed-off-by: Adarsh Babu Kalepalli <opensource.kab@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adarsh Babu Kalepalli [Wed, 30 Jun 2021 18:27:45 +0000 (23:57 +0530)]
cmd:Elaborate 'blkcache' cmd HELP statement
HELP description is provided for ‘configure’ sub-command
of ‘blkcache’.
Signed-off-by: Adarsh Babu Kalepalli <opensource.kab@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Thu, 29 Jul 2021 18:27:17 +0000 (20:27 +0200)]
config: MPC8548CDS: eliminate symbol CONFIG_SYS_ID_EEPROM
Symbol CONFIG_SYS_ID_EEPROM is defined in include/configs/MPC8548CDS.h
but never used. Remove it here and from the whitelist.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Tue, 27 Jul 2021 17:01:44 +0000 (13:01 -0400)]
doc: Add basic information about running CI tests
Start out by documenting general expectations on when CI is run, how
anyone can run Azure pipelines, and how GitLab CI pipelines can be run.
Signed-off-by: Tom Rini <trini@konsulko.com>
Campbell Suter [Fri, 30 Apr 2021 04:45:46 +0000 (16:45 +1200)]
fs/squashfs: Fix some hardlinks reading the wrong inode
In SquashFS, the contents of a directory is stored by
squashfs_directory_entry structures which contain the file's name, inode
and position within the filesystem.
The inode number is not stored directly; instead each directory has one
or more headers which set a base inode number, and files store the
offset from that to the file's inode number.
In mksquashfs, each inode is allocated a number in the same order as
they are written to the directory table; thus the offset from the
header's base inode number to the file's inode number is usually
positive.
Hardlinks are simply stored with two directory entries referencing the
same file. This means the second entry will thus have an inode number
much lower than the surrounding files. Since the header's base inode
number comes from the first entry that uses the header, this delta will
usually be negative.
Previously, U-Boot's squashfs_directory_entry.inode_offset field was
declared as an unsigned value. Thus when a negative value was found, it
would either resolve to an invalid inode number or to that of an
unrelated file.
A squashfs image to test this can be created like so:
echo hi > sqfs_test_files/001-root-file
mkdir sqfs_test_files/002-subdir
touch sqfs_test_files/002-subdir/003-file
ln sqfs_test_files/{001-root-file,002-subdir/004-link}
mksquashfs sqfs_test_files/ test.sqfs -noappend
Note that squashfs sorts the files ASCIIbetacally, so we can use the
names to control the order they appear in. The ordering is important -
the first reference to the file must have a lower inode number than the
directory in which the second reference resides, and the second
reference cannot be the first file in the directory.
Listing this sample image in U-Boot results in:
=> sqfsls virtio 2 002-subdir
0 003-file
Inode not found.
0 004-link
Signed-off-by: Campbell Suter <campbell@snapit.group>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
John Keeping [Tue, 20 Apr 2021 18:19:44 +0000 (19:19 +0100)]
fit: Fix verification of images with external data
The "-E" option to mkimage generates a FIT with external data using the
data-size and data-offset properties which must both be ignored when
verifying a signature.
Add "data-offset" to the list of excluded properties for signature
verification; since the line is now too long, re-format the list to
one-per-line and make it static since the data is constant.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 15 Jul 2021 18:24:25 +0000 (14:24 -0400)]
CI: Update to LLVM-12
The current stable release of LLVM is 12, update to that. While at it,
fix that we had not correctly upgraded to LLVM 11 previously.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 3 Aug 2021 18:06:41 +0000 (14:06 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-spi
- SPI-NOR fix (Big Meng)
- XMC XM25QH64C flash (Reto Schneider)
Tom Rini [Tue, 3 Aug 2021 13:07:01 +0000 (09:07 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-samsung
Bin Meng [Fri, 30 Jul 2021 07:20:17 +0000 (15:20 +0800)]
mtd: spi-nor: Mask out fast read if not requested in DT
The DT bindings of "jedec,spi-nor" [1] defines "m25p,fast-read" property
to indicate that "fast read" opcode can be used to read data from the
chip instead of the usual "read" opcode.
If this property is not present in DT, mask out fast read in
spi_nor_init_params(). This change mirrors the same logic in
spi_nor_info_init_params() in drivers/mtd/spi-nor/core.c in
the Linux kernel v5.14-rc3.
[1] Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml in the kernel tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Bin Meng [Fri, 30 Jul 2021 07:20:16 +0000 (15:20 +0800)]
mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()
The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's
hwcaps, and only looks to the controller on what can be supported.
The flash's hwcaps needs to be AND'ed before checking.
Fixes:
71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Bin Meng [Wed, 28 Jul 2021 12:50:14 +0000 (20:50 +0800)]
spi: spi-mem-nodm: Fix read data size issue
When slave drivers don't set the max_read_size, the spi-mem should
directly use data.nbytes and not limit to any size. But current
logic will limit to the max_write_size.
This commit mirrors the same changes in the dm version done in
commit
535b1fdb8e5e ("spi: spi-mem: Fix read data size issue").
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reto Schneider [Thu, 17 Jun 2021 16:26:51 +0000 (18:26 +0200)]
mtd: spi-nor-ids: Add support for XMC XM25QH64C
This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA
smart gateway.
Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Tue, 3 Aug 2021 01:35:50 +0000 (21:35 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
Tom Rini [Mon, 2 Aug 2021 17:32:20 +0000 (13:32 -0400)]
Merge branch '2021-08-02-numeric-input-cleanups'
- Merge in a series that cleans up and makes more consistent how we deal
with numeric input on the CLI. This saves a few bytes in a lot of
places.
Simon Glass [Sat, 24 Jul 2021 15:03:38 +0000 (09:03 -0600)]
lib: Allow using 0x when a decimal value is requested
U-Boot mostly uses hex for value input, largely because addresses are much
easier to understand in hex.
But in some cases a decimal value is requested, such as where the value is
small or hex does not make sense in the context. In these cases it is
sometimes useful to be able to provide a hex value in any case, if only to
resolve any ambiguity.
Add this functionality, for increased flexibility.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:37 +0000 (09:03 -0600)]
doc: Add a note about number representation
Mention the default base of U-Boot in the command-line section. Add
examples for decimal and octal.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:36 +0000 (09:03 -0600)]
doc: Convert command-line info to rST
Take this part of the README and put it into rST format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:35 +0000 (09:03 -0600)]
lib: Move common digit-parsing code into a function
The code to convert a character into a digit is repeated twice in this
file. Factor it out into a separate function. This also makes the code a
little easier to read.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:34 +0000 (09:03 -0600)]
lib: Add octal tests for simple_strtoul/l()
This function support decoding octal but no tests are included yet.
Add some.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:33 +0000 (09:03 -0600)]
lib: Add tests for simple_strtoull()
Add some tests that check the behaviour of this function. These are the
same as for simple_strtoul() but with a few longer values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:32 +0000 (09:03 -0600)]
lib: Drop unnecessary check for hex digit
If we see 0x then we can assume this is the start of a hex value. It
does not seem necessary to check for a hex digit after that since it will
happen when parsing the value anyway.
Drop this check to simplify the code and reduce size. Add a few more test
cases for when a 0x prefix is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:31 +0000 (09:03 -0600)]
lib: Comment the base parameter with simple_strtoul/l()
This parameter is not documented properly since it does not cover the
meaning when the base is 0. Update this in both functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:30 +0000 (09:03 -0600)]
global: Convert simple_strtoul() with decimal to dectoul()
It is a pain to have to specify the value 10 in each call. Add a new
dectoul() function and update the code to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:29 +0000 (09:03 -0600)]
global: Convert simple_strtoul() with hex to hextoul()
It is a pain to have to specify the value 16 in each call. Add a new
hextoul() function and update the code to use it.
Add a proper comment to simple_strtoul() while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:28 +0000 (09:03 -0600)]
hash: Ensure verification hex pairs are terminated
This function seems to assume that the chr[] variable contains zeros at
the start, which is not always true. Use strlcpy() to be safe.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 07:05:16 +0000 (15:05 +0800)]
x86: crownbay: Use external graphics card by default
The board routes the Integrated Graphics Device (IGD) to an LVDS
panel, which is less popular than a PCIe based graphics card.
Disable the IGD so that it does not show up in the PCI configuration
space as a VGA display controller, so we can use an external PCIe
graphics card with whatever cable we have.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 07:05:15 +0000 (15:05 +0800)]
x86: queensbay: Return directly if IGD / SDVO were already disabled
Initialize 'igd' and 'sdvo' to NULL so that we just need to test
them against NULL later, to be compatible with that case that IGD
and SDVO devices were already in disabled state.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 09:45:22 +0000 (17:45 +0800)]
x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE
For FSP1, there is no such INIT_PHASE_END_FIRMWARE.
Move board_final_cleanup() to fsp2 directory.
Fixes:
7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 09:45:21 +0000 (17:45 +0800)]
x86: fsp: Don't program MTRR for DRAM for FSP1
There are several outstanding issues as to why this does not apply
to FSP1:
* For FSP1, the system memory and reserved memory used by FSP are
already programmed in the MTRR by FSP.
* The 'mtrr_top' mistakenly includes TSEG memory range that has the
same RES_MEM_RESERVED resource type. Its address is programmed
and reported by FSP to be near the top of 4 GiB space, which is
not what we want for SDRAM.
* The call to mtrr_add_request() is not guaranteed to have its size
to be exactly the power of 2. This causes reserved bits of the
IA32_MTRR_PHYSMASK register to be written which generates #GP.
For FSP2, it seems this is necessary as without this, U-Boot boot
process on Chromebook Coral goes very slowly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 2 Aug 2021 12:54:23 +0000 (08:54 -0400)]
Merge tag 'efi-2021-10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-10-rc2
Documentation:
* handle 'make htmldocs' warnings as errors
* add missing board/ti/index.rst
Bug fixes:
* avoid buffer overrun in TrueType console
* lib: disable CONFIG_SPL_HEXDUMP by default
Tom Rini [Mon, 2 Aug 2021 12:53:58 +0000 (08:53 -0400)]
Merge tag 'mmc-2021-7-30' of https://source.denx.de/u-boot/custodians/u-boot-mmc
pl180_mmci update and cleanup
fix rpmb routing memory alignment
Bin Meng [Sat, 31 Jul 2021 08:45:28 +0000 (16:45 +0800)]
x86: cmd: hob: Fix display of resource type for system memory
The resource type for system memory is currently displayed as
"unknown", which is wrong.
Fixes:
51af144eb7a0 ("x86: Allow showing details about a HOB entry")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:27 +0000 (16:45 +0800)]
x86: cmd: hob: Fix the command usage and help messages
At present the hob command usage and help messages are messed up
in a single line. They should be separated.
This was a regression introduced when [seq] and [-v] were added
to the command.
Fixes:
d11544dfa9f4 ("x86: hob: Add way to show a single hob entry")
Fixes:
51af144eb7a0 ("x86: Allow showing details about a HOB entry")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:26 +0000 (16:45 +0800)]
x86: mtrr: Abort if requested size is not power of 2
The size parameter of mtrr_add_request() and mtrr_set_next_var()
shall be power of 2, otherwise the logic creates a mask that does
not meet the requirement of IA32_MTRR_PHYSMASK register.
Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:25 +0000 (16:45 +0800)]
x86: mtrr: Skip MSRs that were already programmed in mtrr_commit()
At present mtrr_commit() programs the MTRR MSRs starting from
index 0, which may overwrite MSRs that were already programmed
by previous boot stage or FSP.
Switch to call mtrr_set_next_var() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:24 +0000 (16:45 +0800)]
x86: mtrr: Do not clear the unused ones in mtrr_commit()
Current mtrr_commit() logic assumes that MTRR MSRs are programmed
consecutively from index 0 to its maximum number, and whenever it
detects an unused one, it clears all other MTRRs starting from that
one. However this may not always be the case.
In fact, the clear is not much helpful because these MTRRs come out
of reset as disabled already. Drop the clear codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 04:00:23 +0000 (12:00 +0800)]
x86: dts: Define a default TSC timer frequency
If for some reason, TSC timer frequency cannot be determined from
hardware, nor is it specified in the device tree, U-Boot will panic
resulting in endless reset during boot.
Let's define a default TSC timer frequency using the Kconfig value
CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
/include/ otherwise the macro is not pre-processed).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 04:00:22 +0000 (12:00 +0800)]
x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ
Currently there are two places to specify the x86 TSC timer frequency
with one in Kconfig used for early timer and the other one in device
tree used when the frequency cannot be determined from hardware.
This may potentially create an inconsistent config where the 2 values
do not match. Let's use the one specified in Kconfig in the device
tree as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 27 Jul 2021 15:15:39 +0000 (23:15 +0800)]
x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROM
These 2 options are no longer needed as now binman is used to build
u-boot.rom.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 27 Jul 2021 13:30:02 +0000 (21:30 +0800)]
x86: crownbay: Adjust VGA rom address
binman complains when binary blobs are present:
Node '/binman/rom/intel-vga': Offset 0xfff90000 (
4294508544) overlaps
with previous entry '/binman/rom/u-boot-dtb-with-ucode' ending at
0xfff9204c (
4294516812)
Adjust VGA rom address to 0xfffa0000 so that u-boot.rom image can be
successfully built again.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Shevchenko [Fri, 30 Jul 2021 20:15:44 +0000 (23:15 +0300)]
x86: tangier: Fix DMA controller IRQ polarity in CSRT
IRQ polarity in CSRT has the same definition as by ACPI specification
chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes:
5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 29 Jul 2021 12:18:23 +0000 (20:18 +0800)]
x86: dts: Add "m25p,fast-read" to SPI flash node
Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should
have "m25p,fast-read" property present in their DT nodes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>