Bas Nieuwenhuizen [Fri, 3 Nov 2017 23:14:55 +0000 (00:14 +0100)]
radv: Optimize calling radv_save_descriptors.
uint32_t data[MAX_SETS * 2] = {}; was getting executed before
the exit and took significant amounts of time. By having the
check outside the function, we skip the execution of the clear.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 4 Nov 2017 14:19:02 +0000 (15:19 +0100)]
radv: Use an array to store descriptor sets.
The vram_list linked list resulted in lots of pointer chasing.
Replacing this with an array instead improves descriptor set
allocation CPU usage by 3x at least (when also considering the free),
because it had to iterate through 300-400 sets on average.
Not a huge improvement as the pre-improvement CPU usage was only
about 2.3% in the busiest thread.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Pierre Moreau [Mon, 2 Oct 2017 18:57:11 +0000 (20:57 +0200)]
nv50,nvc0: Display shared memory usage in pipe_debug_message
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Pierre Moreau [Mon, 2 Oct 2017 18:57:10 +0000 (20:57 +0200)]
nv50,nvc0: Copy shared memory per block to the program info structure and back
In OpenCL/CUDA kernels, shared memory usage can be defined within the
kernel code. Those usage will only be picked up while parsing the
SPIR-V, during the translation phase of the program.
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Pierre Moreau [Mon, 2 Oct 2017 18:57:09 +0000 (20:57 +0200)]
nv50/ir: Store shared memory per block in nv50_ir_prog_info
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Anuj Phogat [Tue, 12 Sep 2017 23:05:06 +0000 (16:05 -0700)]
i965/gen10: Implement Wa3DStateMode
This workaround doesn't fix any of the piglit hangs we've seen
on CNL. But it might be fixing something we haven't tested yet.
V2: Remove the bits enabling Float blend optimization. It is
enabled through CACHE_MODE_SS register.
Update the comment.
Move gen10 if block on top of gen9 if block.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Anuj Phogat [Tue, 31 Oct 2017 16:28:09 +0000 (09:28 -0700)]
i965/gen10: Enable float blend optimization
This optimization is enabled for previous generations too.
See Mesa commit
c17e214a6b
On CNL this bit has been moved to CACHE_MODE_SS register.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Anuj Phogat [Mon, 11 Sep 2017 20:03:31 +0000 (13:03 -0700)]
i965/gen10: Implement WaForceRCPFEHangWorkaround
This workaround doesn't fix any of the piglit hangs we've seen
on CNL. But it might be fixing something we haven't tested yet.
V2: Add the check for Post Sync Operation.
Update the workaround comment.
Use braces around if-else.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Anuj Phogat [Sat, 9 Sep 2017 00:23:28 +0000 (17:23 -0700)]
i965/gen10: Implement WaSampleOffsetIZ workaround
There are few other (duplicate) workarounds which have similar recommendations:
WaFlushHangWhenNonPipelineStateAndMarkerStalled
WaCSStallBefore3DSamplePattern
WaPipeControlBefore3DStateSamplePattern
WaPipeControlBefore3DStateSamplePattern has some extra recommendations if
driver is using mid batch context restore. Ignoring it for now because We're
not doing mid-batch context restore in Mesa.
This workaround doesn't fix any of the piglit hangs we've seen
on CNL. But it might be fixing something we haven't tested yet.
V2: Use brw_load_register_imm32() to program CACHE_MODE_0.
Get rid of brw_flush_gpu_caches().
V3: Make the workaround helper functions static.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by :Nanley Chery <nanley.g.chery@intel.com>
Anuj Phogat [Thu, 26 Oct 2017 18:03:13 +0000 (11:03 -0700)]
i965/gen10: Don't set Antialiasing Enable in 3DSTATE_RASTER if num_samples > 1
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Thu, 26 Oct 2017 18:02:36 +0000 (11:02 -0700)]
i965/gen10: Don't set Smooth Point Enable in 3DSTATE_SF if num_samples > 1
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Andrey Grodzovsky [Thu, 2 Nov 2017 14:50:39 +0000 (10:50 -0400)]
winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.
Fixes reverted patch f03b7c9 by doing VMID reservation per
process and not per context.
Also updates required amdgpu libdrm version since the change
involved interface updates in amdgpu libdrm.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Lionel Landwerlin [Tue, 25 Jul 2017 16:21:22 +0000 (17:21 +0100)]
i965: perf: list registers to program for queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 25 Jul 2017 16:19:08 +0000 (17:19 +0100)]
i965: perf: factorize code for availability
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 25 Jul 2017 16:17:48 +0000 (17:17 +0100)]
i965: perf: make revision variable available
This will be used in the next commit to build up register programming.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Nicolai Hähnle [Tue, 1 Aug 2017 10:44:34 +0000 (12:44 +0200)]
glsl: fix interpolateAtXxx(some_vec[idx], ...) with dynamic idx
The dynamic index of a vector (not array!) is lowered to a sequence of
conditional assignments. However, the interpolate_at_* expressions
require that the interpolant is an l-value of a shader input.
So instead of doing conditional assignments of parts of the shader input
and then interpolating that (which is nonsensical), we interpolate the
entire shader input and then do conditional assignments of the interpolated
result.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Nicolai Hähnle [Wed, 14 Jun 2017 10:43:10 +0000 (12:43 +0200)]
glsl: allow any l-value of an input variable as interpolant in interpolateAt*
The intended rule has been clarified in GLSL 4.60, Section 8.13.2
(Interpolation Functions):
"For all of the interpolation functions, interpolant must be an l-value
from an in declaration; this can include a variable, a block or
structure member, an array element, or some combination of these.
Component selection operators (e.g., .xy) may be used when specifying
interpolant."
For members of interface blocks, var->data.must_be_shader_input must be
determined on-the-fly after lowering interface blocks, since we don't want
to disable varying packing for an entire block just because one input in it
is used in interpolateAt*.
v2: keep setting must_be_shader_input in ast_function (Ian)
v3: follow the relaxed rule of GLSL 4.60
v4: only apply the relaxed rules to desktop GL
(the ES WG decided that the relaxed rules may apply in a future version
but not retroactively; see also
dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_centroid.negative.*)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101378
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Dave Airlie [Fri, 3 Nov 2017 02:58:25 +0000 (12:58 +1000)]
nir/serialize: fix build with gcc 4.4.7
I had to build on RHEL6 today, and noticed this.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 26 May 2017 01:27:22 +0000 (11:27 +1000)]
i915g: remove some unknown cap warnings.
Dave Airlie [Fri, 26 May 2017 01:24:59 +0000 (11:24 +1000)]
i915g: make gears run again.
We need to validate some structs exist before we dirty the states, and
avoid the problem in some other places.
Fixes:
e027935a7 ("st/mesa: don't update unrelated states in non-draw calls such as Clear")
Timothy Arceri [Thu, 2 Nov 2017 02:37:46 +0000 (13:37 +1100)]
ac: remove the remaining duplicate llvm types
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 02:34:13 +0000 (13:34 +1100)]
ac: remove usused v4f32
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 02:24:27 +0000 (13:24 +1100)]
ac: add v2f32 to the common code and make use of it
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 02:22:24 +0000 (13:22 +1100)]
ac: use the ac f16 llvm type
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 02:19:52 +0000 (13:19 +1100)]
ac: use the ac f32 llvm type
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 02:13:07 +0000 (13:13 +1100)]
ac: use the ac f64 llvm type
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 02:09:31 +0000 (13:09 +1100)]
ac: use the common v8i32 llvm type
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 02:06:20 +0000 (13:06 +1100)]
ac: use the common v4i32 llvm type
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 02:02:54 +0000 (13:02 +1100)]
ac: add v3i32 to the common code and make use of it
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 01:59:00 +0000 (12:59 +1100)]
ac: add v2i32 to the common code and use it
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 01:45:29 +0000 (12:45 +1100)]
ac: use the ac i64 llvm type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 01:44:08 +0000 (12:44 +1100)]
ac: remove unused i16 llvm type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 01:42:34 +0000 (12:42 +1100)]
ac: use the ac ivoidt llvm type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 01:41:09 +0000 (12:41 +1100)]
ac: use the ac i8 llvm type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 01:39:48 +0000 (12:39 +1100)]
ac: use the ac i1 llvm type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 2 Nov 2017 01:30:33 +0000 (12:30 +1100)]
ac: use the ac i32 llvm type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 1 Nov 2017 01:43:46 +0000 (12:43 +1100)]
ac/radeonsi: add support for tex instr without a derefence
These are produced by nir_lower_bitmap(), adding the missing derefence
would cause other issues that need to be hacked around such as
skipping sampler lowering and uniform location assignment, so this
change seems the correct way to go.
Fixes 194 piglit crashes on radeonsi using NIR.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 1 Nov 2017 01:43:45 +0000 (12:43 +1100)]
nir: skip lowering sampler if there is no dereference
This avoids a crash on the output of nir_lower_bitmap().
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Thu, 31 Mar 2016 06:17:35 +0000 (16:17 +1000)]
r600: add support for early depth/stencil.
This add support for the early depth/stencil property found
on image shaders.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 31 Mar 2016 06:06:37 +0000 (16:06 +1000)]
r600: add support for emitting RAT instructions to the assembler.
This adds support for emitting RAT instructions to the assembler.
RAT instructions are used to implement image accessors.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 31 Mar 2016 06:04:55 +0000 (16:04 +1000)]
r600: add support for mark bit to the assembler.
This adds support to the assembler for the mark bit
on the export word1.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 31 Mar 2016 05:56:40 +0000 (15:56 +1000)]
r600: add support for valid pixel mode on CF clauses
This just adds support to the assembler for setting the valid
pixel mode on the CF clause.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 31 Mar 2016 05:52:52 +0000 (15:52 +1000)]
r600: add support for some ALU sources.
These special ALU sources provide the shader engine,
simd and hw wave ids.
These are required for images support.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Tue, 31 Oct 2017 08:58:00 +0000 (09:58 +0100)]
radv: use the optimal packets order for dispatch calls
This should reduce the time where compute units are idle, mainly
for meta operations because they use a bunch of compute shaders.
This seems to have a really minor positive effect for Talos, at least.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Timothy Arceri [Mon, 30 Oct 2017 04:11:10 +0000 (15:11 +1100)]
nir: add tess patch support to nir_remove_unused_varyings()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dylan Baker [Tue, 31 Oct 2017 18:49:07 +0000 (11:49 -0700)]
es2api/ABI-check: Add es3.x symbols
Currently this ABI check only checks for es2 symbols, but es3.x symbols
are also exposed. Exposing these symbols is recommended by Khronos, and
as such the test should accept that as ABI.
see: https://lists.freedesktop.org/archives/mesa-stable/2016-June/004545.html
for the discussion about exposing these symbols
cc: Ian Romanick <idr@freedesktop.org>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Dylan Baker [Tue, 31 Oct 2017 18:04:27 +0000 (11:04 -0700)]
meson: Set c visibility args for wayland-drm
Because otherwise gbm will expose wayland symbols that it shouldn't.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-and-Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Timothy Arceri [Wed, 1 Nov 2017 05:20:36 +0000 (16:20 +1100)]
st/glsl_to_nir: pass gl_shader_program to st_finalize_nir()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Bas Nieuwenhuizen [Wed, 1 Nov 2017 08:26:48 +0000 (09:26 +0100)]
radv: Don't expose heaps with 0 memory.
It confuses CTS. This pregenerates the heap info into the
physical device, so we can use it for translating contiguous
indices into our "standard" ones.
This also makes the WSI a bit smarter in case the first preferred
heap does not exist.
Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: <mesa-stable@lists.freedesktop.org>
Dylan Baker [Sat, 21 Oct 2017 00:49:42 +0000 (17:49 -0700)]
gbm: Don't traverse backwards for includes
This is just a bad idea and should be avoided. Instead, make the #include
flat and fix the build systems to pass the proper -I flags
v2: - add an inc_wayland_drm instead passing a path to
include_directories (Emil)
- update commit message (Emil)
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com> (v1)
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
Dylan Baker [Sat, 21 Oct 2017 00:08:25 +0000 (17:08 -0700)]
automake: Remove unused include path
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Marek Olšák [Tue, 31 Oct 2017 17:45:18 +0000 (18:45 +0100)]
radeonsi: remove 'Authors:' comments
It's inaccurate. Instead, see the copyright and use "git log" and
"git blame" to know the authorship.
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Wed, 1 Nov 2017 15:02:34 +0000 (08:02 -0700)]
intel/fs: Don't allocate a param array for zero push constants
Thanks to the ralloc invariant of "any pointer returned from ralloc can
be used as a context", calling ralloc_size with a size of zero will
cause it to allocate at least a header. If we don't have any push
constants, then NULL is perfectly acceptable (and even preferred).
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Jason Ekstrand [Wed, 1 Nov 2017 14:57:21 +0000 (07:57 -0700)]
intel/fs: Alloc pull constants off mem_ctx
It doesn't actually matter since the only user of push constants, i965,
ralloc_steals it back to NULL but it's more consistent and probably
fixes memory leaks in some error cases.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Dylan Baker [Wed, 1 Nov 2017 23:14:34 +0000 (16:14 -0700)]
Revert "meson: bump libdrm version required by amdgpu"
This reverts commit
d364684711a5894fd3221191811d56713d6abdee.
The commit that bumped the autotools version was reverted, so lets
revert the meson version to match.
fixes:
1f2640bfa940362c7550cdd065d37555f21c8ae8
"Revert "winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.""
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tim Rowley [Wed, 1 Nov 2017 18:22:47 +0000 (13:22 -0500)]
gallivm: allow arch rounding with avx512
Fixes piglit vs-roundeven-{float,vec[234]} with simd16 VS.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Wladimir J. van der Laan [Sat, 28 Oct 2017 13:57:14 +0000 (15:57 +0200)]
etnaviv: Allow clearing constant buffer using buffer==NULL user_buffer==NULL
Prevents an assertion when using GALLIUM_HUD with ioquake3,
when cso_restore_constant_buffer_slot0 restores an empty
constant buffer in slot 0.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Wladimir J. van der Laan [Sat, 28 Oct 2017 14:01:49 +0000 (16:01 +0200)]
etnaviv: Don't flush on transfer when UNSYNCHRONIZED
Structure code to only flush when we will potentially call cpu_prep. This
prevents spurious flushes in applications that heavily rely on u_uploader.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Wladimir J. van der Laan [Wed, 1 Nov 2017 10:17:53 +0000 (11:17 +0100)]
etnaviv: don't do resolve-in-place without valid TS
GC3000 resolve-in-place assumes that the TS state is configured.
If it is not, this will result in MMU errors. This is especially
apparent when using glGenMipmaps().
Fixes:
78ade659569e ("etnaviv: Do GC3000 resolve-in-place when possible")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Samuel Pitoiset [Tue, 31 Oct 2017 09:29:47 +0000 (10:29 +0100)]
radv: make radv_bind_descriptor_set() static
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Wed, 1 Nov 2017 23:54:56 +0000 (23:54 +0000)]
radv: make sure we set buffers as shareable properly.
This should make sure we don't treat exports buffers as local
bos.
Fixes:
a639d40f13 (radv: add support for local bos. (v3))
Tested-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dylan Baker [Thu, 26 Oct 2017 22:32:09 +0000 (15:32 -0700)]
svga: Use __asm__ instead of asm
__asm__ is portable, and allows the svga driver to be compiled with the
c99 standard instead of requiring the gnu99 standard.
I have compile tested this with GCC and Clang on Linux.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 1 Nov 2017 20:42:11 +0000 (21:42 +0100)]
Revert "winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx."
This reverts commit
f03b7c9ad92c1656a221297819fbc6d065cc0af7.
The libdrm interface is wrong.
Lionel Landwerlin [Sat, 30 Sep 2017 13:43:06 +0000 (14:43 +0100)]
intel: decoder: enable decoding a single field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 30 Sep 2017 13:41:20 +0000 (14:41 +0100)]
intel: decoder: expose missing find_enum()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 30 Sep 2017 12:48:36 +0000 (13:48 +0100)]
intel: decoder: extract field value computation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 30 Sep 2017 11:48:48 +0000 (12:48 +0100)]
intel: decoder: rename field() to field_value()
We would like to avoid collisions with variables named field.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Thu, 28 Sep 2017 01:37:20 +0000 (02:37 +0100)]
intel: decoder: rename internal function to free name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Thu, 28 Sep 2017 01:36:30 +0000 (02:36 +0100)]
intel: decoder: simplify field_is_header()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 27 Sep 2017 19:57:28 +0000 (20:57 +0100)]
intel: common: make intel utils available from C++
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 27 Sep 2017 17:57:58 +0000 (18:57 +0100)]
intel: decoder: remove unused platform field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Thu, 1 Jun 2017 14:23:38 +0000 (15:23 +0100)]
intel: error-decode: implement a rolling window of programs
If we have more programs than what we can store,
aubinator_error_decode will assert. Instead let's have a rolling
window of programs.
v2: Fix overflowing issues (Eric Engestrom)
v3: Go through programs starting at idx_program (Scott)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Brian Paul [Wed, 1 Nov 2017 12:17:03 +0000 (06:17 -0600)]
gallium: increase pipe_sampler_view::target bitfield size for MSVC
MSVC treats enums as being signed. The 4-bit target field isn't large
enough to correctly store the value 8 (for PIPE_TEXTURE_CUBE_ARRAY).
The bitfield value 0x8 was being interpreted as -8 so matching the
target with PIPE_TEXTURE_CUBE_ARRAY in switch statements, etc. was
failing.
To keep the structure size the same, we reduce the format field from
16 bits to 15. There don't appear to be any other enum bitfields
which need to be adjusted.
This fixes a number of Piglit cube map array tests.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Eric Engestrom [Tue, 31 Oct 2017 18:47:00 +0000 (18:47 +0000)]
mapi: fix .so path in ABI-check
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Lionel Landwerlin [Mon, 25 Sep 2017 23:54:49 +0000 (00:54 +0100)]
intel: decoder: extract instruction/structs length
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 23 Sep 2017 23:44:57 +0000 (00:44 +0100)]
intel: decoder: pack iterator variable declarations
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 23 Sep 2017 23:43:09 +0000 (00:43 +0100)]
intel: decoder: simplify creation of struct when 0-allocated
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 23 Sep 2017 20:32:10 +0000 (21:32 +0100)]
intel: decoder: add destructor for gen_spec
This makes use of ralloc to simplify the destruction. We can also
store instructions in hash tables.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 23 Sep 2017 20:30:56 +0000 (21:30 +0100)]
intel: decoder: expose helper to test header fields
These fields are of little importance as they're used to recognize
instructions.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Thu, 3 Aug 2017 13:50:35 +0000 (14:50 +0100)]
intel: decoder: don't read qword outside instruction/struct limit
We used to print invalid data when the last field was being clamped to
32bits due to Dword Length of the whole instruction. Here is an
example where the decoder read part of the next instruction instead of
stopping at the 32bit limit:
0x000ce0b4: 0x10000002: MI_STORE_DATA_IMM
0x000ce0b4: 0x10000002 : Dword 0
DWord Length: 2
Store Qword: 0
Use Global GTT: false
0x000ce0b8: 0x00045010 : Dword 1
Core Mode Enable: 0
Address: 0x00045010
0x000ce0bc: 0x00000000 : Dword 2
0x000ce0c0: 0x00000000 : Dword 3
Immediate Data:
8791026489807077376
With this change we have the proper value :
0x000ce0b4: 0x10000002: MI_STORE_DATA_IMM (4 Dwords)
0x000ce0b4: 0x10000002 : Dword 0
DWord Length: 2
Store Qword: 0
Use Global GTT: false
0x000ce0b8: 0x00045010 : Dword 1
Core Mode Enable: 0
Address: 0x00045010
0x000ce0bc: 0x00000000 : Dword 2
0x000ce0c0: 0x00000000 : Dword 3
Immediate Data: 0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 21:33:28 +0000 (22:33 +0100)]
intel: decoder: split out getting the next field and decoding it
Due to the new way we handle fields, we need *not* to forget the first
field when decoding instructions. The issue was that the advance
function was called first and skipped the first field.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 21:32:25 +0000 (22:32 +0100)]
intel: decoder: move field name copy
This should be inside the function that actually decodes fields.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 21:30:14 +0000 (22:30 +0100)]
intel: decoder: reorder iterator init function
Making the next change more readable.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 18:33:09 +0000 (19:33 +0100)]
intel: common: print out all dword with field spanning multiple dwords
For example, we were skipping Dword 3 in this PIPE_CONTROL :
0x000ce130: 0x7a000004: PIPE_CONTROL
DWord Length: 4
0x000ce134: 0x00000010 : Dword 1
Flush LLC: false
Destination Address Type: 0 (PPGTT)
LRI Post Sync Operation: 0 (No LRI Operation)
Store Data Index: 0
Command Streamer Stall Enable: false
Global Snapshot Count Reset: false
TLB Invalidate: false
Generic Media State Clear: false
Post Sync Operation: 0 (No Write)
Depth Stall Enable: false
Render Target Cache Flush Enable: false
Instruction Cache Invalidate Enable: false
Texture Cache Invalidation Enable: false
Indirect State Pointers Disable: false
Notify Enable: false
Pipe Control Flush Enable: false
DC Flush Enable: false
VF Cache Invalidation Enable: true
Constant Cache Invalidation Enable: false
State Cache Invalidation Enable: false
Stall At Pixel Scoreboard: false
Depth Cache Flush Enable: false
0x000ce138: 0x00000000 : Dword 2
Address: 0x00000000
0x000ce140: 0x00000000 : Dword 4
Immediate Data: 0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 18:31:08 +0000 (19:31 +0100)]
intel: decoder: build sorted linked lists of fields
The xml files don't always have fields in order. This might confuse
our parsing of the commands. Let's have the fields in order. To do
this, the easiest way it to use a linked list. It also helps a bit
with the iterator.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Fri, 22 Sep 2017 17:00:25 +0000 (18:00 +0100)]
intel: common: expose gen_spec fields
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Eric Engestrom [Tue, 31 Oct 2017 17:35:16 +0000 (17:35 +0000)]
travis: build meson first for quicker feedback
Meson is much quicker to build Mesa, giving quicker feedback if
executed first.
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Tue, 31 Oct 2017 16:25:52 +0000 (16:25 +0000)]
meson: bump libdrm version required by amdgpu
Fixes:
f03b7c9ad92c1656a221 "winsys/amdgpu: Add R600_DEBUG flag to
reserve VMID per ctx."
Cc: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Jordan Justen [Sat, 25 Feb 2017 10:30:06 +0000 (02:30 -0800)]
i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false
(Apologies for the double negative.)
For now, the shader cache is disabled by default on i965 to allow us
to verify its stability.
In other words, to enable the shader cache on i965, set
MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then
the shader cache will be disabled.
We use the build-id of i965_dri.so for the timestamp, and the pci
device id for the device name.
v2:
* Simplify code by forcing link to include build id sha. (Matt)
v3:
* Don't use a for loop with snprintf for bin to hex. (Matt)
* Assume fixed length render and timestamp string to further simplify
code.
Cc: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 18 Oct 2017 22:04:37 +0000 (15:04 -0700)]
dri drivers: Always add the sha1 build-id
v4:
* Add Android build changes. (Emil)
Cc: Dylan Baker <dylanx.c.baker@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sat, 14 Oct 2017 05:04:52 +0000 (22:04 -0700)]
disk_cache: Fix issue reading GLSL metadata
This would cause the read of the metadata content to fail, which would
prevent the linking from being skipped.
Seen on Rocket League with i965 shader cache.
Fixes:
b86ecea3446e "util/disk_cache: write cache item metadata to disk"
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 28 Mar 2017 18:48:55 +0000 (11:48 -0700)]
glsl/shader_cache: Save fs (BlendSupport) metadata
Fixes many GL 4.5 CTS blend tests, such as:
* GL45-CTS.blend_equation_advanced.extension_directive_enable
* GL45-CTS.blend_equation_advanced.extension_directive_warn
* GL45-CTS.blend_equation_advanced.blend_all.GL_MULTIPLY_KHR_all_qualifier
* GL45-CTS.blend_equation_advanced.blend_specific.GL_COLORBURN_KHR
v2:
* Directly save the BlendSupport field to avoid potentially including
a pointer in the future in the structure is updated. (tarceri)
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Sun, 26 Feb 2017 01:36:28 +0000 (17:36 -0800)]
i965: Initialize sha1 hash of dri config options
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sat, 25 Feb 2017 10:37:57 +0000 (02:37 -0800)]
i965: Don't link when the program was found in the disk cache
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Thu, 19 Oct 2017 02:25:48 +0000 (19:25 -0700)]
i965: add cache fallback support using serialized nir
If the i965 gen program cannot be loaded from the cache, then we
fallback to using a serialized nir program.
This is based on "i965: add cache fallback support" by Timothy Arceri
<timothy.arceri@collabora.com>. Tim's version was written to fallback
to compiling from source, and therefore had to be much more complex.
After Connor and Jason implemented nir serialization, I was able to
rewrite and greatly simplify this patch.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Mon, 23 Jan 2017 21:35:51 +0000 (08:35 +1100)]
i965: add support for cached shaders with xfb qualifiers
For now this disables the shader cache when transform feedback is
enabled via the GL API as we don't currently allow for it when
generating the sha for the shader.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sat, 19 Nov 2016 05:16:08 +0000 (16:16 +1100)]
mesa/glsl: add api_enabled flag to gl_transform_feedback_info
This will be used to disable the shader cache when xfb is enabled
via the api as we don't currently allow for it when generating the
sha for the shader.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Thu, 2 Mar 2017 00:52:23 +0000 (16:52 -0800)]
i965: Add shader cache support for compute
v2:
* Use MAYBE_UNUSED. (Matt)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 29 Nov 2016 01:25:54 +0000 (12:25 +1100)]
i965: add shader cache support for tess stages
v2:
* Use MAYBE_UNUSED. (Matt)
[jordan.l.justen@intel.com: *_cached_program => brw_disk_cache_*_program]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 29 Nov 2016 01:24:54 +0000 (12:24 +1100)]
i965: add shader cache support for geometry shaders
v2:
* Use MAYBE_UNUSED. (Matt)
[jordan.l.justen@intel.com: *_cached_program => brw_disk_cache_*_program]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>