Florian Hahn [Tue, 7 Nov 2017 10:43:56 +0000 (10:43 +0000)]
[AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors
Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE
unpredicated ADD/SUB instructions.
Patch by Sander De Smalen.
Reviewed by: rengolin
Differential Revision: https://reviews.llvm.org/D39087
llvm-svn: 317564
Tamas Berghammer [Tue, 7 Nov 2017 10:39:22 +0000 (10:39 +0000)]
Support scoped enums in the DWARF AST parser
Subscribers: JDevlieghere
Differential Revision: https://reviews.llvm.org/D39545
llvm-svn: 317563
Pavel Labath [Tue, 7 Nov 2017 10:36:42 +0000 (10:36 +0000)]
test: Clean up finalize_build_dictionary
We only support API>=16 now, so we don't need to check the API level of
the android device.
llvm-svn: 317562
Pavel Labath [Tue, 7 Nov 2017 10:36:36 +0000 (10:36 +0000)]
"Fix" concurrent events test for arm
Summary:
The test incremented an atomic varible to trigger the watchpoint event.
On arm64 this compiled to a ldaxr/stlxr loop, with the watchpoint being
triggered in the middle of the loop. Hitting the watchpoint resets the
exclusive monitor, and forces the process to loop one more time, hitting
the watchpoint again, etc.
While it would be nice if the debugger was able to resume from this
situation, this is not trivial, and is not what this test is about.
Therefore, I propose to change this to a simple store to a normal
variable (which should still trip the watchpoint everywhere, but without
atomic loops) and file a bug to investigate the possibilities of
handling the watchpoints in atomic loops in a more reasonable way.
Reviewers: clayborg
Subscribers: aemerson, kristof.beyls, lldb-commits
Differential Revision: https://reviews.llvm.org/D39680
llvm-svn: 317561
Kristof Beyls [Tue, 7 Nov 2017 10:34:34 +0000 (10:34 +0000)]
[GlobalISel] Enable legalizing non-power-of-2 sized types.
This changes the interface of how targets describe how to legalize, see
the below description.
1. Interface for targets to describe how to legalize.
In GlobalISel, the API in the LegalizerInfo class is the main interface
for targets to specify which types are legal for which operations, and
what to do to turn illegal type/operation combinations into legal ones.
For each operation the type sizes that can be legalized without having
to change the size of the type are specified with a call to setAction.
This isn't different to how GlobalISel worked before. For example, for a
target that supports 32 and 64 bit adds natively:
for (auto Ty : {s32, s64})
setAction({G_ADD, 0, s32}, Legal);
or for a target that needs a library call for a 32 bit division:
setAction({G_SDIV, s32}, Libcall);
The main conceptual change to the LegalizerInfo API, is in specifying
how to legalize the type sizes for which a change of size is needed. For
example, in the above example, how to specify how all types from i1 to
i8388607 (apart from s32 and s64 which are legal) need to be legalized
and expressed in terms of operations on the available legal sizes
(again, i32 and i64 in this case). Before, the implementation only
allowed specifying power-of-2-sized types (e.g. setAction({G_ADD, 0,
s128}, NarrowScalar). A worse limitation was that if you'd wanted to
specify how to legalize all the sized types as allowed by the LLVM-IR
LangRef, i1 to i8388607, you'd have to call setAction 8388607-3 times
and probably would need a lot of memory to store all of these
specifications.
Instead, the legalization actions that need to change the size of the
type are specified now using a "SizeChangeStrategy". For example:
setLegalizeScalarToDifferentSizeStrategy(
G_ADD, 0, widenToLargerAndNarrowToLargest);
This example indicates that for type sizes for which there is a larger
size that can be legalized towards, do it by Widening the size.
For example, G_ADD on s17 will be legalized by first doing WidenScalar
to make it s32, after which it's legal.
The "NarrowToLargest" indicates what to do if there is no larger size
that can be legalized towards. E.g. G_ADD on s92 will be legalized by
doing NarrowScalar to s64.
Another example, taken from the ARM backend is:
for (unsigned Op : {G_SDIV, G_UDIV}) {
setLegalizeScalarToDifferentSizeStrategy(Op, 0,
widenToLargerTypesUnsupportedOtherwise);
if (ST.hasDivideInARMMode())
setAction({Op, s32}, Legal);
else
setAction({Op, s32}, Libcall);
}
For this example, G_SDIV on s8, on a target without a divide
instruction, would be legalized by first doing action (WidenScalar,
s32), followed by (Libcall, s32).
The same principle is also followed for when the number of vector lanes
on vector data types need to be changed, e.g.:
setAction({G_ADD, LLT::vector(8, 8)}, LegalizerInfo::Legal);
setAction({G_ADD, LLT::vector(16, 8)}, LegalizerInfo::Legal);
setAction({G_ADD, LLT::vector(4, 16)}, LegalizerInfo::Legal);
setAction({G_ADD, LLT::vector(8, 16)}, LegalizerInfo::Legal);
setAction({G_ADD, LLT::vector(2, 32)}, LegalizerInfo::Legal);
setAction({G_ADD, LLT::vector(4, 32)}, LegalizerInfo::Legal);
setLegalizeVectorElementToDifferentSizeStrategy(
G_ADD, 0, widenToLargerTypesUnsupportedOtherwise);
As currently implemented here, vector types are legalized by first
making the vector element size legal, followed by then making the number
of lanes legal. The strategy to follow in the first step is set by a
call to setLegalizeVectorElementToDifferentSizeStrategy, see example
above. The strategy followed in the second step
"moreToWiderTypesAndLessToWidest" (see code for its definition),
indicating that vectors are widened to more elements so they map to
natively supported vector widths, or when there isn't a legal wider
vector, split the vector to map it to the widest vector supported.
Therefore, for the above specification, some example legalizations are:
* getAction({G_ADD, LLT::vector(3, 3)})
returns {WidenScalar, LLT::vector(3, 8)}
* getAction({G_ADD, LLT::vector(3, 8)})
then returns {MoreElements, LLT::vector(8, 8)}
* getAction({G_ADD, LLT::vector(20, 8)})
returns {FewerElements, LLT::vector(16, 8)}
2. Key implementation aspects.
How to legalize a specific (operation, type index, size) tuple is
represented by mapping intervals of integers representing a range of
size types to an action to take, e.g.:
setScalarAction({G_ADD, LLT:scalar(1)},
{{1, WidenScalar}, // bit sizes [ 1, 31[
{32, Legal}, // bit sizes [32, 33[
{33, WidenScalar}, // bit sizes [33, 64[
{64, Legal}, // bit sizes [64, 65[
{65, NarrowScalar} // bit sizes [65, +inf[
});
Please note that most of the code to do the actual lowering of
non-power-of-2 sized types is currently missing, this is just trying to
make it possible for targets to specify what is legal, and how non-legal
types should be legalized. Probably quite a bit of further work is
needed in the actual legalizing and the other passes in GlobalISel to
support non-power-of-2 sized types.
I hope the documentation in LegalizerInfo.h and the examples provided in the
various {Target}LegalizerInfo.cpp and LegalizerInfoTest.cpp explains well
enough how this is meant to be used.
This drops the need for LLT::{half,double}...Size().
Differential Revision: https://reviews.llvm.org/D30529
llvm-svn: 317560
Haojian Wu [Tue, 7 Nov 2017 10:21:02 +0000 (10:21 +0000)]
[clangd] Add ErrorCode enum class.
Summary: Avoid using magic number in the code everywhere.
Reviewers: sammccall
Reviewed By: sammccall
Subscribers: ilya-biryukov, cfe-commits
Differential Revision: https://reviews.llvm.org/D39718
llvm-svn: 317559
Sjoerd Meijer [Tue, 7 Nov 2017 10:09:45 +0000 (10:09 +0000)]
[docs] Add section 'Half-Precision Floating Point'
This documents the differences/interactions between _Float16 and __fp16
and is a companion change for the _Float16 type implementation (r312794).
Differential Revision: https://reviews.llvm.org/D35295
llvm-svn: 317558
Serguei Katkov [Tue, 7 Nov 2017 09:43:08 +0000 (09:43 +0000)]
[CGP] Disable Select instruction handling in optimizeMemoryInst. NFC
This patch disables the handling of selects in optimization
extensing scope of optimizeMemoryInst.
The optimization itself is disable by default.
The idea here is just to switch optimiztion level step by step.
Specifically, first optimization will be enabled only for Phi nodes,
then select instructions will be added.
In case someone will complain about perfromance it will be easier to
detect what part of optimizations is responsible for that.
Differential Revision: https://reviews.llvm.org/D36073
llvm-svn: 317555
Peter Smith [Tue, 7 Nov 2017 09:40:05 +0000 (09:40 +0000)]
[docs][ARM] Add HowTo for cross compiling and testing compiler-rt builtins
This document contains information on how to cross-compile the compiler-rt
builtins library for several flavours of Arm target and how to test the
libraries using qemu.
Differential Revision: https://reviews.llvm.org/D39600
llvm-svn: 317554
Sam McCall [Tue, 7 Nov 2017 08:57:54 +0000 (08:57 +0000)]
[clangd] fix MSVC build errors
llvm-svn: 317553
Haojian Wu [Tue, 7 Nov 2017 08:53:37 +0000 (08:53 +0000)]
Add new check in google module for Objective-C code to ensure global variables follow the naming convention of Google Objective-C Style Guide
Summary:
This is a new checker for objc files in clang-tidy.
The new check finds global variable declarations in Objective-C files that are not follow the pattern of variable names in Google's Objective-C Style Guide.
All the global variables should follow the pattern of "g[A-Z].*" (variables) or "k[A-Z].*" (constants). The check will suggest a variable name that follows the pattern
if it can be inferred from the original name.
Patch by Yan Zhang!
Reviewers: benhamilton, hokein, alexfh
Reviewed By: hokein
Subscribers: Eugene.Zelenko, mgorny
Differential Revision: https://reviews.llvm.org/D39391
llvm-svn: 317552
Bjorn Steinbrink [Tue, 7 Nov 2017 08:50:21 +0000 (08:50 +0000)]
[X86] Don't clobber reserved registers with stack adjustments
Summary:
Calls using invoke in funclet based functions are assumed to clobber
all registers, which causes the stack adjustment using pops to consider
all registers not defined by the call to be undefined, which can
unfortunately include the base pointer, if one is needed.
To prevent this (and possibly other hazards), skip reserved registers
when looking for candidate registers.
This fixes issue #45034 in the Rust compiler.
Reviewers: mkuper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39636
llvm-svn: 317551
Craig Topper [Tue, 7 Nov 2017 07:13:07 +0000 (07:13 +0000)]
[X86] Add patterns to fold a 64-bit load into the EVEX vcvtph2ps instructions.
llvm-svn: 317548
Craig Topper [Tue, 7 Nov 2017 07:13:06 +0000 (07:13 +0000)]
[X86] Add patterns for folding a v16i8 with the VEX vcvtph2ps intrinsics.
Disable the peephole pass to prove that the pattern is working.
llvm-svn: 317547
Craig Topper [Tue, 7 Nov 2017 07:13:05 +0000 (07:13 +0000)]
[X86] Add a test for a 128-bit vector load feeding a cvtph2ps intrinsic.
The instruction only loads 64-bits, but we should be able to fold a wider load and let it be narrowed.
llvm-svn: 317546
Craig Topper [Tue, 7 Nov 2017 07:13:04 +0000 (07:13 +0000)]
[X86] Remove alignment from a load in the f16c intrinsic test. The alignment shouldn't be required for load folding.
llvm-svn: 317545
Craig Topper [Tue, 7 Nov 2017 07:13:03 +0000 (07:13 +0000)]
[X86] Add support for using EVEX instructions for the legacy vcvtph2ps intrinsics.
Looks like there's some missed load folding opportunities for i64 loads.
llvm-svn: 317544
Craig Topper [Tue, 7 Nov 2017 07:13:01 +0000 (07:13 +0000)]
[X86] Add AVX512VL command line to f16c intrinsic test to show missed EVEX opportunities for the legacy intrinsics.
llvm-svn: 317543
Craig Topper [Tue, 7 Nov 2017 04:44:22 +0000 (04:44 +0000)]
[X86] Use IMPLICIT_DEF in VEX/EVEX vcvtss2sd/vcvtsd2ss patterns instead of a COPY_TO_REGCLASS.
ExeDepsFix pass should take care of making the registers match.
llvm-svn: 317542
Craig Topper [Tue, 7 Nov 2017 04:44:21 +0000 (04:44 +0000)]
[X86] Remove 'Requires' from instructions with no patterns. NFC
llvm-svn: 317541
NAKAMURA Takumi [Tue, 7 Nov 2017 02:18:24 +0000 (02:18 +0000)]
ClangdTests/JSONExprTests.cpp: Appease g++-4.8 to move raw string literal out of macro arg.
llvm-svn: 317538
George Karpenkov [Tue, 7 Nov 2017 02:02:10 +0000 (02:02 +0000)]
[analyzer] [NFC] Remove unused typedef from SVals.h
Differential Revision: https://reviews.llvm.org/D39620
llvm-svn: 317537
Rafael Espindola [Tue, 7 Nov 2017 02:00:51 +0000 (02:00 +0000)]
Use Path instead of Config->OutputFile. NFC.
This function is always called with Config->OutputFile. That is not
obvious from reading the function. It should always use Path or take
no argument and always use Config->OutputFile.
llvm-svn: 317536
Davide Italiano [Tue, 7 Nov 2017 00:47:04 +0000 (00:47 +0000)]
[Support/UNIX] posix_fallocate() can fail with EINVAL.
According to the docs on opegroup.org, the function can return
EINVAL if:
The len argument is less than zero, or the offset argument is less
than zero, or the underlying file system does not support this
operation.
I'd say it's a peculiar choice (when EONOTSUPP is right there), but
let's keep POSIX happy for now. This was independently discovered
by Mark Millard (on FreeBSD/ZFS).
Quickly ack'ed by Rui on IRC.
llvm-svn: 317535
Adrian Prantl [Tue, 7 Nov 2017 00:45:34 +0000 (00:45 +0000)]
Make DIExpression::createFragmentExpression() return an Optional.
We can't safely split arithmetic into multiple fragments because we
can't express carry-over between fragments.
llvm-svn: 317534
Alex Lorenz [Tue, 7 Nov 2017 00:31:19 +0000 (00:31 +0000)]
Clarify the error message for unsupported aliases on Darwin
rdar://
35109556
llvm-svn: 317532
Keith Wyss [Tue, 7 Nov 2017 00:28:28 +0000 (00:28 +0000)]
[XRay] Minimal tool to convert xray traces to Chrome's Trace Event Format.
Minimal tool to convert xray traces to Chrome's Trace Event Format.
Summary:
Make use of Chrome Trace Event format's Duration events and stack frame dict to
produce Json files that chrome://tracing can visualize from xray function call
traces. Trace Event format is more robust and has several features like
argument logging, function categorization, multi process traces, etc. that we
can add as needed. Duration events cover an important base case.
Part of this change is rearranging the code so that the TrieNode data structure
can be used from multiple tools and can carry parameterized baggage on the
nodes. I put the actual behavior changes in llvm-xray convert exclusively.
Exploring the trace of instrumented llc was pretty nifty if overwhelming.
I can envision this being very useful for analyzing contention scenarios or
tuning parameters like batch sizes in a producer consumer queue. For more
targeted traces likemthis, let's talk about how we want to approach trace
pruning.
Reviewers: dberris, pelikan
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39362
llvm-svn: 317531
Rui Ueyama [Tue, 7 Nov 2017 00:26:04 +0000 (00:26 +0000)]
Remove dead code.
llvm-svn: 317530
Stephane Sezer [Tue, 7 Nov 2017 00:14:40 +0000 (00:14 +0000)]
Disable tests in lang/c/shared_lib on Windows
Summary: These fail because `-fPIC` is not supported on Windows.
Reviewers: zturner, jingham, clayborg
Reviewed By: clayborg
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D39692
llvm-svn: 317529
Rui Ueyama [Tue, 7 Nov 2017 00:12:05 +0000 (00:12 +0000)]
Report an error if an inferred alignment for a shared symbol is too large.
Differential Revision: https://reviews.llvm.org/D39697
llvm-svn: 317528
Davide Italiano [Tue, 7 Nov 2017 00:09:25 +0000 (00:09 +0000)]
[IPO/LowerTypesTest] Skip blockaddress(es) when replacing uses.
Blockaddresses refer to the function itself, therefore replacing them
would cause an assertion in doRAUW.
Fixes https://bugs.llvm.org/show_bug.cgi?id=35201
This was found when trying CFI on a proprietary kernel by Dmitry Mikulin.
Differential Revision: https://reviews.llvm.org/D39695
llvm-svn: 317527
Matt Arsenault [Tue, 7 Nov 2017 00:06:32 +0000 (00:06 +0000)]
AMDGPU: Remove redundant combine
This combine was already done in two places. The
generic combiner already has done this since
r217610, for adds (with a single use).
This one was added in r303641, and added support for handling
or as well. r313251 later added support to the generic
combine for or. It also turns out the isOrEquivalentToAdd
check is not necessary for this combine.
Additionally, we already reproduce this combine in yet
another place in the backend, although in that version
multiple uses of the add are still folded if it will
allow a fold into the addressing mode. That version needs
to be improved to understand ors though, as well as the
correct legal offsets for private.
llvm-svn: 317526
Rui Ueyama [Tue, 7 Nov 2017 00:04:22 +0000 (00:04 +0000)]
Move MIPS-specific code from Symbols.cpp to MIPS.cpp.
We have a lot of "if (MIPS)" conditions in lld because the MIPS' ABI
is different at various places than other arch's ABIs at where it
don't have to be different, but we at least want to reduce MIPS-ness
from the regular classes.
llvm-svn: 317525
Vedant Kumar [Mon, 6 Nov 2017 23:15:21 +0000 (23:15 +0000)]
[DebugInfo] Unify logic to merge DILocations. NFC.
This makes DILocation::getMergedLocation() do what its comment says it
does when merging locations for an Instruction: set the common inlineAt
scope. This simplifies Instruction::applyMergedLocation() a bit.
Testing: check-llvm, check-clang
Differential Revision: https://reviews.llvm.org/D39628
llvm-svn: 317524
Simon Dardis [Mon, 6 Nov 2017 23:01:46 +0000 (23:01 +0000)]
[Support][Chrono] Use explicit cast of text output of time values.
rL316419 exposed a platform specific issue where the type of the values
passed to llvm::format could be different to the format string.
Debian unstable for mips uses long long int for std::chrono:duration,
while x86_64 uses long int.
For mips, this resulted in the value being corrupted when rendered to a
string. Address this by explicitly casting the result of the duration_cast
to the type specified in the format string.
Reviewers: sammccall
Differential Revision: https://reviews.llvm.org/D39597
llvm-svn: 317523
Adrian Prantl [Mon, 6 Nov 2017 22:49:39 +0000 (22:49 +0000)]
InstCombine: salvage the debug info of DCE'ed add instructions.
rdar://problem/
31209283
llvm-svn: 317522
Craig Topper [Mon, 6 Nov 2017 22:49:04 +0000 (22:49 +0000)]
[X86] Make FeatureAVX512 imply FeatureF16C.
The EVEX to VEX pass is already assuming this is true under AVX512VL. We had special patterns to use zmm instructions if VLX and F16C weren't available.
Instead just make AVX512 imply F16C to make the EVEX to VEX behavior explicitly legal and remove the extra patterns.
All known CPUs with AVX512 have F16C so this should safe for now.
llvm-svn: 317521
Craig Topper [Mon, 6 Nov 2017 22:49:01 +0000 (22:49 +0000)]
[X86] Make FeatureAVX512 imply FeatureFMA.
Previously our VEX patterns were checking Subtarget.hasFMA() which checked FMA || AVX512. So we were behaving as if AVX512 implied it anyway. Which means we'd allow VEX encoded 128/256 FMA when AVX512F was enabled but AVX512VL is off. Regardless of the FMA flag.
EVEX to VEX also transforms scalar EVEX FMA instructions to their VEX versions even without the FMA flag. Similarly for 128/256 under AVX512VL.
So this makes AVX512 imply FeatureFMA to make our current behavior explicit.
All known CPUs that support AVX512 have VEX FMA instructions.
llvm-svn: 317520
Sanjay Patel [Mon, 6 Nov 2017 22:40:09 +0000 (22:40 +0000)]
[ValueTracking] readonly (const) is a requirement for converting sqrt to llvm.sqrt; nnan is not
As discussed in D39204, this is effectively a revert of rL265521 which required nnan
to vectorize sqrt libcalls based on the old LangRef definition of llvm.sqrt. Now that
the definition has been updated so the libcall and intrinsic have the same semantics
apart from potentially setting errno, we can remove the nnan requirement.
We have the right check to know that errno is not set:
if (!ICS.onlyReadsMemory())
...ahead of the switch.
This will solve https://bugs.llvm.org/show_bug.cgi?id=27435 assuming that's being
built for a target with -fno-math-errno.
Differential Revision: https://reviews.llvm.org/D39642
llvm-svn: 317519
Hans Wennborg [Mon, 6 Nov 2017 22:28:02 +0000 (22:28 +0000)]
Revert r317510 "[InstCombine] Pull shifts through a select plus binop with constant"
This broke the CodeGen/Hexagon/loop-idiom/pmpy-mod.ll test on a bunch of buildbots.
> This pulls shifts through a select+binop with a constant where the select conditionally executes the binop. We already do this for just the binop, but not with the select.
>
> This can allow us to get the select closer to other selects to enable removing one.
>
> Differential Revision: https://reviews.llvm.org/D39222
>
> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317510
91177308-0d34-0410-b5e6-
96231b3b80d8
llvm-svn: 317518
Hans Wennborg [Mon, 6 Nov 2017 22:17:23 +0000 (22:17 +0000)]
Revert r316064 "Fix the incorrect detection of ICONV_LIBRARY_PATH"
This broke the use of libxml2 on machines where iconv() is provided by libc.
I'll follow up on the mailing list to discuss how to fix this properly.
> This is introduced in rL308711.
> Check for c library is incorrect here just because libc will be found always
> and it does not mean that iconv is presented.
>
> Thank to Andrew Krasny for narrowing down the root cause.
>
> Reviewers: ecbeckmann
> Reviewed By: ecbeckmann
> Subscribers: mgorny, llvm-commits
> Differential Revision: https://reviews.llvm.org/D38875
llvm-svn: 317517
Devin Coughlin [Mon, 6 Nov 2017 22:12:19 +0000 (22:12 +0000)]
[analyzer] Model correct dispatch_once() 'done' value in BodyFarm
The analyzer's BodyFarm models dispatch_once() by comparing the passed-in
predicate against a known 'done' value. If the predicate does not have that
value, the model updates the predicate to have that value and executes the
passed in block.
Unfortunately, the current model uses the wrong 'done' value: 1 instead of ~0.
This interferes with libdispatch's static inline function _dispatch_once(),
which enables a fast path if the block has already been executed. That function
uses __builtin_assume() to tell the compiler that the done flag is set to ~0 on
exit. When r302880 added modeling of __builtin_assume(), this caused the
analyzer to assume 1 == ~0. This in turn caused the analyzer to never explore any code after a call to dispatch_once().
This patch regains the missing coverage by updating BodyFarm to use the correct
'done' value.
rdar://problem/
34413048
Differential Revision: https://reviews.llvm.org/D39691
llvm-svn: 317516
Jonas Hahnfeld [Mon, 6 Nov 2017 22:06:14 +0000 (22:06 +0000)]
[OMPT] Fix null pointer in parallel/no_thread_num_clause.c
Looks like the implementation of printf on Darwin uses "0x0"
instead of "(nil)" like glibc does.
llvm-svn: 317515
Xinliang David Li [Mon, 6 Nov 2017 21:57:51 +0000 (21:57 +0000)]
Fix comment /NFC
llvm-svn: 317514
Bjorn Pettersson [Mon, 6 Nov 2017 21:46:06 +0000 (21:46 +0000)]
[MIRPrinter] Use %subreg.xxx syntax for subregister index operands
Summary:
Print %subreg.<subregidxname> instead of just the subregister
index when printing immediate operands corresponding to subreg
indices in INSERT_SUBREG, EXTRACT_SUBREG, SUBREG_TO_REG and
REG_SEQUENCE.
Reviewers: qcolombet, MatzeB
Reviewed By: MatzeB
Subscribers: nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D39696
llvm-svn: 317513
Alex Shlyapnikov [Mon, 6 Nov 2017 21:27:06 +0000 (21:27 +0000)]
[LSan] Detect dynamic loader by its base address.
Summary:
Relanding D38600, which was reverted due to various PPC bot failures.
If it breaks something again, please provide some pointers to broken
bots, not just revert it, otherwise it's very hard to reason what's
wrong with this commit.
Whenever possible (Linux + glibc 2.16+), detect dynamic loader module by
its base address, not by the module name matching. The current name
matching approach fails on some configurations.
Reviewers: eugenis
Subscribers: kubamracek, llvm-commits
Differential Revision: https://reviews.llvm.org/D39275
llvm-svn: 317512
Dave Lee [Mon, 6 Nov 2017 21:18:05 +0000 (21:18 +0000)]
Vary Windows toolchain selection by -fuse-ld
Summary:
This change allows binutils to be used for linking with MSVC. Currently, when
using an MSVC target and `-fuse-ld=bfd`, the driver produces an invalid linker
invocation.
Reviewers: rnk, compnerd
Reviewed By: compnerd
Subscribers: smeenai, cfe-commits
Differential Revision: https://reviews.llvm.org/D39509
llvm-svn: 317511
Craig Topper [Mon, 6 Nov 2017 21:07:22 +0000 (21:07 +0000)]
[InstCombine] Pull shifts through a select plus binop with constant
This pulls shifts through a select+binop with a constant where the select conditionally executes the binop. We already do this for just the binop, but not with the select.
This can allow us to get the select closer to other selects to enable removing one.
Differential Revision: https://reviews.llvm.org/D39222
llvm-svn: 317510
Justin Bogner [Mon, 6 Nov 2017 21:06:09 +0000 (21:06 +0000)]
update_mir_test_checks: Be careful about replacing entire vregs
Previously, this could end up replacing a vreg like %14 with
[[VREG1]]4, where VREG1 was the match for %1. That's obviously not
correct, though it hasn't actually come up in any tests I've converted
so far.
llvm-svn: 317509
Graham Yiu [Mon, 6 Nov 2017 21:04:19 +0000 (21:04 +0000)]
Fix buildbot breakages from r317503. Add parentheses to assignment when using result as a condition.
llvm-svn: 317508
Craig Topper [Mon, 6 Nov 2017 21:00:49 +0000 (21:00 +0000)]
[X86] Replace the mask cmpeq/cmple/cmplt/cmpgt/cmpge/cmpneq intrinsics with macros that just pass the right comparison predicate value to the regular cmp intrinsic. Remove mask cmpeq/cmpgt builtins that are now unused.
This shortens the intrinsic headers a little and allows us to get rid of the cmpeq and cmpgt handling from CGBuiltin.cpp.
llvm-svn: 317506
Martin Storsjo [Mon, 6 Nov 2017 20:33:13 +0000 (20:33 +0000)]
[MinGW] Don't autoexport anything from libmsvcrt or libucrtbase
These libraries contain a number of object files with compat wrappers,
in addition to the normal import library entries.
Differential Revision: https://reviews.llvm.org/D39684
llvm-svn: 317505
Martin Storsjo [Mon, 6 Nov 2017 20:33:13 +0000 (20:33 +0000)]
[X86] Add 3dnow and 3dnowa to the list of valid target features
These were missed in SVN r316783, which broke compiling mingw-w64 CRT.
Differential Revision: https://reviews.llvm.org/D39631
llvm-svn: 317504
Graham Yiu [Mon, 6 Nov 2017 20:18:30 +0000 (20:18 +0000)]
Adds code to PPC ISEL lowering to recognize byte inserts from vector_shuffles, and use P9 shift and vector insert byte instructions instead of vperm. Extends tests from vector insert half-word.
Differential Revision: https://reviews.llvm.org/D34497
llvm-svn: 317503
Dehao Chen [Mon, 6 Nov 2017 19:52:49 +0000 (19:52 +0000)]
Include already promoted counts when computing SUM for VP.
Summary: When computing the SUM for indirect call promotion, if the callsite is already promoted in the profile, it will be promoted before ICP. In the current implementation, ICP only sees remaining counts in SUM. This may cause extra indirect call targets being promoted. This patch updates the SUM to include the counts already promoted earlier. This way we do not end up promoting too many indirect call targets.
Reviewers: tejohnson
Reviewed By: tejohnson
Subscribers: llvm-commits, sanjoy
Differential Revision: https://reviews.llvm.org/D38763
llvm-svn: 317502
Stephane Sezer [Mon, 6 Nov 2017 19:25:33 +0000 (19:25 +0000)]
Add a dependency from check-lldb on lld
Summary:
This is required when using the in-tree clang for building tests,
because -fuse-ld=lld is used by default.
Subscribers: mgorny
Differential Revision: https://reviews.llvm.org/D39689
llvm-svn: 317501
Mitch Phillips [Mon, 6 Nov 2017 19:14:09 +0000 (19:14 +0000)]
[cfi-verify] Added a simple check that stops division-by-zero error when no indirect CF instructions are found in the provided file.
llvm-svn: 317500
Guozhi Wei [Mon, 6 Nov 2017 19:09:38 +0000 (19:09 +0000)]
[PPC] Use xxbrd to speed up bswap64
Power doesn't have bswap instructions, so llvm generates following code sequence for bswap64.
rotldi 5, 3, 16
rotldi 4, 3, 8
rotldi 9, 3, 24
rotldi 10, 3, 32
rotldi 11, 3, 48
rotldi 12, 3, 56
rldimi 4, 5, 8, 48
rldimi 4, 9, 16, 40
rldimi 4, 10, 24, 32
rldimi 4, 11, 40, 16
rldimi 4, 12, 48, 8
rldimi 4, 3, 56, 0
But Power9 has vector bswap instructions, they can also be used to speed up scalar bswap intrinsic. With this patch, bswap64 can be translated to:
mtvsrdd 34, 3, 3
xxbrd 34, 34
mfvsrld 3, 34
Differential Revision: https://reviews.llvm.org/D39510
llvm-svn: 317499
Mitch Phillips [Mon, 6 Nov 2017 18:56:36 +0000 (18:56 +0000)]
Make MCAsmBackend and MCCodeEmiiter passed by unique_ptr rval
Summary: Fixes build breakage of llvm-mc-assemble-fuzzer introduced by rL315531.
Reviewers: lhames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39268
llvm-svn: 317498
Michael Kruse [Mon, 6 Nov 2017 17:48:14 +0000 (17:48 +0000)]
[ForwardOpTree] Limit isl operations of known content reload.
Put the analysis part of reloadKnownContent under an isl
max-operations quota scope, as has already been done for
forwardKnownLoad.
This should fix the aosp timeout of "GrTestUtils.cpp".
llvm-svn: 317495
Alex Shlyapnikov [Mon, 6 Nov 2017 17:43:28 +0000 (17:43 +0000)]
[Sanitizers] Check pthread_setcancel{state|type} interceptor arguments for != nullptr.
Summary:
According to man, pthread_setcancelstate's oldstate and
pthread_setcanceltype's oldtype parameters can be nullptr.
Check these parameters for != nullptr before attempting to
access their shadow memory.
Reviewers: dvyukov
Subscribers: kubamracek, llvm-commits
Differential Revision: https://reviews.llvm.org/D39626
llvm-svn: 317494
Jan Korous [Mon, 6 Nov 2017 17:42:17 +0000 (17:42 +0000)]
[Parser] Fix TryParseLambdaIntroducer() error handling
rdar://
35066196
Differential Revision: https://reviews.llvm.org/D39419
llvm-svn: 317493
Matt Arsenault [Mon, 6 Nov 2017 17:04:37 +0000 (17:04 +0000)]
AMDGPU: Select v_mad_u64_u32 and v_mad_i64_i32
llvm-svn: 317492
Sanjay Patel [Mon, 6 Nov 2017 16:52:31 +0000 (16:52 +0000)]
[Analysis] update to use new fast-math API - isFast()
llvm-svn: 317491
Adrian Prantl [Mon, 6 Nov 2017 16:52:05 +0000 (16:52 +0000)]
Canonicalize spelling of long-form-options in dsymutil.rst
llvm-svn: 317490
Sanjay Patel [Mon, 6 Nov 2017 16:27:36 +0000 (16:27 +0000)]
[CodeGen] match new fast-math-flag method: isFast()
This corresponds to LLVM commiti r317488:
If that commit is reverted, this commit will also need to be reverted.
llvm-svn: 317489
Sanjay Patel [Mon, 6 Nov 2017 16:27:15 +0000 (16:27 +0000)]
[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
As discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/107104.html
and again more recently:
http://lists.llvm.org/pipermail/llvm-dev/2017-October/118118.html
...this is a step in cleaning up our fast-math-flags implementation in IR to better match
the capabilities of both clang's user-visible flags and the backend's flags for SDNode.
As proposed in the above threads, we're replacing the 'UnsafeAlgebra' bit (which had the
'umbrella' meaning that all flags are set) with a new bit that only applies to algebraic
reassociation - 'AllowReassoc'.
We're also adding a bit to allow approximations for library functions called 'ApproxFunc'
(this was initially proposed as 'libm' or similar).
...and we're out of bits. 7 bits ought to be enough for anyone, right? :) FWIW, I did
look at getting this out of SubclassOptionalData via SubclassData (spacious 16-bits),
but that's apparently already used for other purposes. Also, I don't think we can just
add a field to FPMathOperator because Operator is not intended to be instantiated.
We'll defer movement of FMF to another day.
We keep the 'fast' keyword. I thought about removing that, but seeing IR like this:
%f.fast = fadd reassoc nnan ninf nsz arcp contract afn float %op1, %op2
...made me think we want to keep the shortcut synonym.
Finally, this change is binary incompatible with existing IR as seen in the
compatibility tests. This statement:
"Newer releases can ignore features from older releases, but they cannot miscompile
them. For example, if nsw is ever replaced with something else, dropping it would be
a valid way to upgrade the IR."
( http://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility )
...provides the flexibility we want to make this change without requiring a new IR
version. Ie, we're not loosening the FP strictness of existing IR. At worst, we will
fail to optimize some previously 'fast' code because it's no longer recognized as
'fast'. This should get fixed as we audit/squash all of the uses of 'isFast()'.
Note: an inter-dependent clang commit to use the new API name should closely follow
commit.
Differential Revision: https://reviews.llvm.org/D39304
llvm-svn: 317488
Sam McCall [Mon, 6 Nov 2017 15:50:35 +0000 (15:50 +0000)]
[clangd] Squash namespace warning
llvm-svn: 317487
Sam McCall [Mon, 6 Nov 2017 15:40:30 +0000 (15:40 +0000)]
Adds a json::Expr type to represent intermediate JSON expressions.
Summary:
This form can be created with a nice clang-format-friendly literal syntax,
and gets escaping right. It knows how to call unparse() on our Protocol types.
All the places where we pass around JSON internally now use this type.
Object properties are sorted (stored as std::map) and so serialization is
canonicalized, with optional prettyprinting (triggered by a -pretty flag).
This makes the lit tests much nicer to read and somewhat nicer to debug.
(Unfortunately the completion tests use CHECK-DAG, which only has
line-granularity, so pretty-printing is disabled there. In future we
could make completion ordering deterministic, or switch to unittests).
Compared to the current approach, it has some efficiencies like avoiding copies
of string literals used as object keys, but is probably slower overall.
I think the code/test quality benefits are worth it.
This patch doesn't attempt to do anything about JSON *parsing*.
It takes direction from the proposal in this doc[1], but is limited in scope
and visibility, for now.
I am of half a mind just to use Expr as the target of a parser, and maybe do a
little string deduplication, but not bother with clever memory allocation.
That would be simple, and fast enough for clangd...
[1] https://docs.google.com/document/d/1OEF9IauWwNuSigZzvvbjc1cVS1uGHRyGTXaoy3DjqM4/edit
+cc d0k so he can tell me not to use std::map.
Reviewers: ioeric, malaperle
Subscribers: bkramer, ilya-biryukov, mgorny, klimek
Differential Revision: https://reviews.llvm.org/D39435
llvm-svn: 317486
Simon Pilgrim [Mon, 6 Nov 2017 15:28:25 +0000 (15:28 +0000)]
[X86][SSE] Merge combineExtractVectorElt_SSE into combineExtractVectorElt. NFCI.
We still early-out for X86ISD::PEXTRW/X86ISD::PEXTRB so no actual change in behaviour, but it'll make it easier to add support in a future patch.
llvm-svn: 317485
Jonas Hahnfeld [Mon, 6 Nov 2017 15:13:06 +0000 (15:13 +0000)]
[OMPT] Fix callback.h for tests for changes in TR6
This was also lost in the last commit.
llvm-svn: 317484
Alexey Bataev [Mon, 6 Nov 2017 14:52:57 +0000 (14:52 +0000)]
[SLP] Test for PR35047, NFC.
llvm-svn: 317482
Simon Pilgrim [Mon, 6 Nov 2017 14:34:19 +0000 (14:34 +0000)]
[X86][SSE] Combine EXTRACT_VECTOR_ELT with combineExtractWithShuffle before XFormVExtractWithShuffleIntoLoad
combineExtractWithShuffle can handle more complex shuffles/bitcasts than we can with the equivalent code in XFormVExtractWithShuffleIntoLoad.
Mainly a compile time improvement now (combineExtractWithShuffle combines will have always failed late on inside XFormVExtractWithShuffleIntoLoad), and will let us merge combineExtractVectorElt_SSE in a future commit.
llvm-svn: 317481
Jonas Hahnfeld [Mon, 6 Nov 2017 14:33:09 +0000 (14:33 +0000)]
[OMPT] Improve cast that was lost on commit, NFC.
llvm-svn: 317480
Yaxun Liu [Mon, 6 Nov 2017 14:32:33 +0000 (14:32 +0000)]
[AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment
Differential Revision: https://reviews.llvm.org/D39657
llvm-svn: 317479
Florian Hahn [Mon, 6 Nov 2017 14:26:04 +0000 (14:26 +0000)]
[Polly] Fix using order, as this caused a test failure (NFC)
Summary:
Without this patch, clang-format in check-polly fails for me, with current master:
```
FAILED: cd build/tools/polly && build/bin/clang-format -sort-includes -style=llvm llvm/tools/polly/include/polly/ScopPass.h | diff -u llvm/tools/polly/include/polly/ScopPass.h -
--- llvm/tools/polly/include/polly/ScopPass.h 2017-11-06 14:05:49.
885345000 +0000
+++ - 2017-11-06 14:07:24.
956241758 +0000
@@ -40,12 +40,12 @@
} // namespace polly
namespace llvm {
+using polly::SPMUpdater;
using polly::Scop;
using polly::ScopAnalysisManager;
using polly::ScopAnalysisManagerFunctionProxy;
using polly::ScopInfo;
using polly::ScopStandardAnalysisResults;
-using polly::SPMUpdater;
template <>
class InnerAnalysisManagerProxy<ScopAnalysisManager, Function>::Result {
```
Reviewers: grosser, Meinersbur, bollu
Reviewed By: Meinersbur
Subscribers: llvm-commits, pollydev
Differential Revision: https://reviews.llvm.org/D39683
llvm-svn: 317478
Jonas Paulsson [Mon, 6 Nov 2017 13:10:31 +0000 (13:10 +0000)]
[SystemZ] implement hasDivRemOp()
SystemZ can do division and remainder in a single instruction for scalar
integer types, which are now reflected by returning true in this hook for
those cases.
Review: Ulrich Weigand
llvm-svn: 317477
Yaxun Liu [Mon, 6 Nov 2017 13:01:33 +0000 (13:01 +0000)]
[AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit
The backend assumes pointer in default addr space is 32 bit, which is not
true for the new addr space mapping and causes assertion for unresolved
functions.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D39643
llvm-svn: 317476
Simon Dardis [Mon, 6 Nov 2017 12:59:53 +0000 (12:59 +0000)]
[mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version
Previously, the 'movep' instruction was defined for microMIPS32r3 and
shared that definition with microMIPS32R6. 'movep' was re-encoded for
microMIPS32r6, so this patch provides the correct encoding.
Secondly, correct the encoding of the 'rs' and 'rt' operands which have
an instruction specific encoding for the registers those operands accept.
Finally, correct the decoding of the 'dst_regs' operand which was extracting
the relevant field from the instruction, but was actually extracting the
field from the alreadly extracted field.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D39495
llvm-svn: 317475
Pavel Labath [Mon, 6 Nov 2017 12:34:27 +0000 (12:34 +0000)]
Extend android xfail in TestTopLevelExprs
The test fails on API level 19 as well. I'm going to assume that it
fails on every API level below 23.
llvm-svn: 317474
Daniel Jasper [Mon, 6 Nov 2017 12:11:51 +0000 (12:11 +0000)]
[clang-format] Handle unary operator overload with arguments and specifiers
Before:
int operator++(int)noexcept;
After:
int operator++(int) noexcept;
Patch by Igor Sugak. Thank you!
llvm-svn: 317473
Jonas Devlieghere [Mon, 6 Nov 2017 11:47:24 +0000 (11:47 +0000)]
[docs] Update code block for compatibility with Sphinx 1.5.1
It is currently not possible to build the documentation with cmake and
the same version of Sphinx (1.5.1) used to generate the public facing
documentation on llvm.org. When code blocks cannot be parsed by
Pygments, it generates a warning which is treated as an error.
In addition to being annoying and confusing for developers, this
needlessly increases the bar for newcomers that want to get involved.
This patch removes the language specifier from the affected block. The
result is the same as when parsing fails: the block are not highlighted.
llvm-svn: 317472
Mohammed Agabaria [Mon, 6 Nov 2017 10:56:20 +0000 (10:56 +0000)]
[LV][X86] update the cost of interleaving mem. access of floats
Recommit:
This patch contains update of the costs of interleaved loads of v8f32 of stride 3 and 8.
fixed the location of the lit test it works with make check-all.
Differential Revision: https://reviews.llvm.org/D39403
llvm-svn: 317471
Simon Dardis [Mon, 6 Nov 2017 10:50:04 +0000 (10:50 +0000)]
[mips] Fix PR35140
Mark all symbols involved with TLS relocations as being TLS symbols.
This resolves PR35140.
Thanks to Alex Crichton for reporting the issue!
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D39591
llvm-svn: 317470
Peter Smith [Mon, 6 Nov 2017 10:36:18 +0000 (10:36 +0000)]
[ELF] Fix typo in comment for getISDThunkSec [NFC]
The ISR in the comment should read ISD for InputSectionDescription. The use
of ISR (InputSectionRange) was from the original implementation that did not
use the sections from InputSectionDescription directly.
llvm-svn: 317469
Gabor Horvath [Mon, 6 Nov 2017 10:36:02 +0000 (10:36 +0000)]
[clang-tidy] Support relative paths in run-clang-tidy.py
Unfortunately, these python scripts are not tested currently. I did the testing
manually on LLVM by editing the CMake generated compilation database to
contain relative paths for some of the files.
Differential Revision: https://reviews.llvm.org/D39603
llvm-svn: 317468
Raphael Isemann [Mon, 6 Nov 2017 09:51:39 +0000 (09:51 +0000)]
Fixed dead links in WritingAnLLVMPass.rst
llvm-svn: 317467
Eric Liu [Mon, 6 Nov 2017 09:29:09 +0000 (09:29 +0000)]
[Tooling] Test internal::createExecutorFromCommandLineArgsImpl instead of the wrapper.
llvm-svn: 317466
Uriel Korach [Mon, 6 Nov 2017 09:22:38 +0000 (09:22 +0000)]
[X86][AVX512] Improve lowering of AVX512 test intrinsics
Added TESTM and TESTNM to the list of instructions that already zeroing unused upper bits
and does not need the redundant shift left and shift right instructions afterwards.
Added a pattern for TESTM and TESTNM in iselLowering, so now icmp(neq,and(X,Y), 0) goes folds into TESTM
and icmp(eq,and(X,Y), 0) goes folds into TESTNM
This commit is a preparation for lowering the test and testn X86 intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D38732
llvm-svn: 317465
Uriel Korach [Mon, 6 Nov 2017 08:32:45 +0000 (08:32 +0000)]
[X86] Replace duplicate function call with variable. NFC
Change from:
if (N->getOperand(0).getValueType() == MVT::v8i32 ||
N->getOperand(0).getValueType() == MVT::v8f32)
to:
EVT OpVT = N->getOperand(0).getValueType();
if (OpVT == MVT::v8i32 || OpVT == MVT::v8f32)
Change-Id: I5a105f8710b73a828e6cfcd55fac2eae6153ce25
llvm-svn: 317464
Zvi Rackover [Mon, 6 Nov 2017 08:25:46 +0000 (08:25 +0000)]
X86 ISel: Basic support for variable-index vector permutations
Summary:
Try to lower a BUILD_VECTOR composed of extract-extract chains that can be
reasoned to be a permutation of a vector by indices in a non-constant vector.
We saw this pattern created by ISPC, which resolts to creating it due to the
requirement that shufflevector's mask operand be a *constant* vector.
I didn't check this but we could possibly use this pattern for lowering the X86 permute
C-instrinsics instead of llvm.x86 instrinsics.
This change can be followed by more improvements:
1. Handle vectors with undef elements.
2. Utilize pshufb and zero-mask-blending to support more effiecient
construction of vectors with constant-0 elements.
3. Use smaller-element vectors of same width, and "interpolate" the indices,
when no native operation available.
Reviewers: RKSimon, craig.topper
Reviewed By: RKSimon
Subscribers: chandlerc, DavidKreitzer
Differential Revision: https://reviews.llvm.org/D39126
llvm-svn: 317463
Jina Nahias [Mon, 6 Nov 2017 07:48:58 +0000 (07:48 +0000)]
Revert "adding a pattern for broadcastm"
This reverts commit r317457.
Change-Id: If07f1fca1e3453d16c1dac906e87768661384e91
llvm-svn: 317462
Martin Storsjo [Mon, 6 Nov 2017 07:36:17 +0000 (07:36 +0000)]
[test] Add test files that were missed from SVN r317459
llvm-svn: 317461
Martin Storsjo [Mon, 6 Nov 2017 07:22:17 +0000 (07:22 +0000)]
Update tests for ARMNT/ARM64 reloc names
After ObjectYAML learnt the proper enum names for ARMNT/ARM64
relocations, it no longer accepts the numerical values.
This fixes LLD tests after SVN r317459 in LLVM.
llvm-svn: 317460
Martin Storsjo [Mon, 6 Nov 2017 07:20:58 +0000 (07:20 +0000)]
[ObjectYAML] Map relocation types for COFF ARMNT and ARM64
Differential Revision: https://reviews.llvm.org/D39668
llvm-svn: 317459
Jina Nahias [Mon, 6 Nov 2017 07:09:24 +0000 (07:09 +0000)]
[x86][AVX512] Lowering Broadcastm intrinsics to LLVM IR
This patch, together with a matching clang patch (https://reviews.llvm.org/D38683), implements the lowering of X86 broadcastm intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D38684
Change-Id: I709ac0b34641095397e994c8ff7e15d1315b3540
llvm-svn: 317458
Jina Nahias [Mon, 6 Nov 2017 07:09:09 +0000 (07:09 +0000)]
adding a pattern for broadcastm
Change-Id: I6551fb13879e098aed74de410e29815cf37d9ab5
llvm-svn: 317457
Jina Nahias [Mon, 6 Nov 2017 07:04:12 +0000 (07:04 +0000)]
lowering broadcastm
Change-Id: I0661abea3e3742860e0a03ff9e4fcdc367eff7db
llvm-svn: 317456
Martin Storsjo [Mon, 6 Nov 2017 07:02:33 +0000 (07:02 +0000)]
[COFF] Handle ARM64 in getDefaultType
Differential Revision: https://reviews.llvm.org/D39634
llvm-svn: 317455
Craig Topper [Mon, 6 Nov 2017 05:48:26 +0000 (05:48 +0000)]
[X86] Use EVEX encoded intrinsics for legacy FMA intrinsics when possible.
llvm-svn: 317454