Samuel Pitoiset [Mon, 17 Jul 2017 19:57:27 +0000 (21:57 +0200)]
mesa: add sample_maski() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Mon, 17 Jul 2017 19:54:54 +0000 (21:54 +0200)]
mesa: add KHR_no_error support to glDepthRangeArrayv
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Mon, 17 Jul 2017 19:52:55 +0000 (21:52 +0200)]
mesa: add depth_range_arrayv() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Fri, 28 Jul 2017 15:30:34 +0000 (17:30 +0200)]
dri_interface,egl,gallium: only expose RGBA visuals on Android
X/GLX can't handle them. This removes almost 500 GLX visuals that were
incorrectly exposed.
Add an optional getCapability callback for querying what the loader can do.
I'm not splitting this patch, because it's already too small.
v2: also add the callback to __DRIimageLoaderExtension
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Marek Olšák [Fri, 28 Jul 2017 04:35:41 +0000 (06:35 +0200)]
radeonsi: expose MRT-draw-calls to HUD
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Samuel Pitoiset [Fri, 28 Jul 2017 13:47:22 +0000 (15:47 +0200)]
mesa: clamp viewport values only once when using glViewport()
It's useless to clamp the same values for all viewports.
+7% in the "viewport change" test (drawoverhead benchmark).
v2: - call clamp_viewport() in all callers of set_viewport_no_notify()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Samuel Pitoiset [Fri, 28 Jul 2017 13:47:21 +0000 (15:47 +0200)]
mesa: make _mesa_check_init_viewport() static
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Kenneth Graunke [Fri, 28 Jul 2017 20:40:49 +0000 (13:40 -0700)]
gallium: Fix Thomas's email address
Commit
877128505431adaf817dc8069172ebe4a1cdf5d8 misspelled Hellstrom.
Kenneth Graunke [Fri, 28 Jul 2017 20:37:57 +0000 (13:37 -0700)]
i965: s/Tungsten Graphics/VMware/ in brw_bufmgr.c.
In commit
877128505431adaf817dc8069172ebe4a1cdf5d8, José replaced the
Tungsten Graphics copyright notices with VMware, as Tungsten is gone.
I later imported brw_bufmgr.c, reintroducing a Tungsten copyright.
This commit does the equivalent of José's change to the new file.
Kenneth Graunke [Fri, 28 Jul 2017 20:26:42 +0000 (13:26 -0700)]
i965: Reformat the copyright header in brw_bufmgr.c
This reformats the copyright header to match what we use in most of the
newer parts of the driver. There are a few minor alterations: we change
"COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS" to the standard
"AUTHORS OR COPYRIGHT HOLDERS", and move the permission notice to the
proper place (it should be in the middle, so "next paragraph" actually
refers to something).
Both of these changes match the OSI's MIT License text:
https://opensource.org/licenses/MIT
I copied this from genX_state_upload.c.
Marek Olšák [Tue, 4 Jul 2017 14:11:16 +0000 (16:11 +0200)]
radeonsi: update dirty_level_mask only when flushing or unbinding framebuffer
This fixes corruption with bindless textures in Dawn Of War 3.
The do_update_surf_dirtiness mechanism was complicated and dirty_level_mask
was only updated after the first draw call. The problem is bindless textures
are checked for decompression every draw call and we would only decompress
after the first draw call. The solution is to set dirtiness after the last
draw call to the framebuffer, so the (unconditional) decompression of
bindless textures happens at the right time.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Fri, 28 Jul 2017 14:33:26 +0000 (16:33 +0200)]
Revert "drirc: whitelist glthread for Mount and Blade Warband"
This reverts commit
a7617a49fbde2fcfccdab22886aeabdbf8abb8e4.
glthread disables itself automatically and therefore has no effect
on the game.
Samuel Pitoiset [Thu, 27 Jul 2017 14:06:00 +0000 (16:06 +0200)]
st/mesa: remove useless st_bufferobj_validate_usage()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Samuel Pitoiset [Thu, 27 Jul 2017 14:05:59 +0000 (16:05 +0200)]
st/mesa: remove st_cache.h
It contains unused prototypes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Samuel Pitoiset [Thu, 27 Jul 2017 15:12:09 +0000 (17:12 +0200)]
st/glsl_to_tgsi: fix getting the image type for array of structs
Since array splitting for AoA is disabled, we have to retrieve
the type of the first non-array type when an array of images is
declared inside a structure. Otherwise, it will hit an assert
in glsl_type::sampler_index() because it expects either a sampler
or an image type.
This fixes a regression in the following piglit test:
arb_bindless_texture/compiler/images/arrays-of-struct.frag
Fixes:
57165f2ef8 ("glsl: disable array splitting for AoA")
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Tue, 25 Jul 2017 19:39:20 +0000 (21:39 +0200)]
mesa: fix mismatch when returning 64-bit bindless uniform handles
The slower convert-and-copy process performs a bad conversion
because it converts the value to signed 64-bit integer, but
bindless uniform handles are considered unsigned 64-bit.
This fixes "Check glUniform*() with mixed texture units/handles"
from arb_bindless_texture-uniform piglit.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Thu, 27 Jul 2017 14:05:41 +0000 (16:05 +0200)]
mesa: remove gl_sync_object::Type field
This is useless.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Thu, 27 Jul 2017 14:05:40 +0000 (16:05 +0200)]
mesa: drop fence type parameter from NewSyncObject()
This is useless.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Thu, 27 Jul 2017 00:45:00 +0000 (02:45 +0200)]
radeonsi: rely on CLEAR_STATE for clearing UCP and blend color registers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 27 Jul 2017 00:41:30 +0000 (02:41 +0200)]
radeonsi: rely on CLEAR_STATE for resetting the framebuffer and sample mask
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 27 Jul 2017 00:40:34 +0000 (02:40 +0200)]
radeonsi: use CLEAR_STATE to initialize some registers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 27 Jul 2017 23:52:13 +0000 (01:52 +0200)]
st/mesa: release sampler views when redefining a texture in st_context_teximage
Noticed randomly.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Thu, 27 Jul 2017 03:51:48 +0000 (04:51 +0100)]
radv: for stencil only set Z tile mode index to same value
On SI this was causing a hang in
dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint
This was due to not handling the tile mode index for depth like
I fixed previously for new GPUs.
Fixes:
01d0c5a9 (radv: fix stencil regression since new addrlib import)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 28 Jul 2017 01:04:35 +0000 (11:04 +1000)]
virgl: drop precise modifier.
The host doesn't understand this yet, so drop it for now.
Fixes: virgl regressions.
Fixes:
af22adee4f (tgsi: add precise flag to tgsi_instruction)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Tue, 25 Jul 2017 15:34:52 +0000 (17:34 +0200)]
st/mesa: always unconditionally revalidate main framebuffer after SwapBuffers
This fixes the black Feral launcher window.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101867
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Nicolai Hähnle [Fri, 14 Jul 2017 13:10:58 +0000 (15:10 +0200)]
radeonsi: bail out instead of crashing if the main shader part failed to compile
Reviewed: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 14 Jul 2017 12:33:49 +0000 (14:33 +0200)]
radeonsi: update a comment for merged shaders
Reviewed: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 14 Jul 2017 11:32:20 +0000 (13:32 +0200)]
radeonsi/gfx9: dump previous stage LLVM IR for merged shaders
Reviewed: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 26 Jul 2017 11:53:45 +0000 (13:53 +0200)]
radeonsi: make sure TCS main output VGPRs don't alias inputs
Avoids an unnecessary move introduce by "radeonsi/gfx9: always wrap GS
and TCS in an if-block (v2)"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 14 Jul 2017 12:33:37 +0000 (14:33 +0200)]
radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)
With merged ESGS shaders, the GS part of a wave may be empty, and the
hardware gets confused if any GS messages are sent from that wave. Since
S_SENDMSG is executed even when EXEC = 0, we have to wrap even
non-monolithic GS shaders in an if-block, so that the entire shader and
hence the S_SENDMSG instructions are skipped in empty waves.
This change is not required for TCS/HS, but applying it there as well
simplifies the logic a bit.
Fixes GL45-CTS.geometry_shader.rendering.rendering.*
v2: ensure that the TCS epilog doesn't run for non-existing patches
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 14 Jul 2017 11:31:49 +0000 (13:31 +0200)]
radeonsi/gfx9: fix vertex idx in ES with multiple waves per threadgroup
Cc: mesa-stable@lists.freedesktop.org
Reviewed: Marek Olšák <marek.olsak@amd.com>
George Kyriazis [Sat, 22 Jul 2017 04:23:04 +0000 (23:23 -0500)]
swr: fix transform feedback logic
The shader that is used to copy vertex data out of the vs/gs shaders to
the user-specified buffer (streamout or SO shader) was not using the
correct offsets.
Adjust the offsets that are used just for the SO shader:
- Make sure that position is handled in the same special way
as in the vs/gs shaders
- Use the correct offset to be passed in the core
- consolidate register slot mapping logic into one function, since it's
been calculated in 2 different places (one for calcuating the slot mask,
and one for the register offsets themselves
Also make room for all attibutes in the backend vertex area.
Fixes:
- all vtk GL2PS tests
- 18 piglit tests (16 ext_transform_feedback tests,
arb-quads-follow-provoking-vertex and primitive-type gl_points
v2:
- take care of more SGV slots in slot mapping logic
- trim feState.vsVertexSize
- fix GS interface and incorporate GS while calculating vsVertexSize
Note that vsVertexSize is used in the core as the one parameter that
controls vertex size between all stages, so it has to be adjusted appropriately
for the whole vs/gs/fs pipeline.
Also note that GS and SO is not fully implemented. This will be addressed
later.
fixes:
- fixes total of 20 piglit tests
CC: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 26 Jul 2017 20:17:49 +0000 (15:17 -0500)]
swr/rast: non-regex knob fallback code for gcc < 4.9
gcc prior to 4.9 didn't implement <regex>, causing a startup crash
in the swr knob parameter reading code.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Timothy Arceri [Wed, 26 Jul 2017 22:53:08 +0000 (08:53 +1000)]
mesa: check that buffer object is not NULL before initializing it
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Thu, 27 Jul 2017 06:49:55 +0000 (16:49 +1000)]
glsl: small builtin inline tidy up
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Tue, 25 Jul 2017 06:09:40 +0000 (16:09 +1000)]
virgl: encode index buffer offset.
Fixes arb_vertex_buffer_object-combined-vertex-index
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
Michel Dänzer [Thu, 27 Jul 2017 02:12:24 +0000 (11:12 +0900)]
st/mesa: Fix inversed test in st_api_destroy_drawable
Fixes a drawable leak.
Fixes:
bbc29393d3be ("st/mesa: create framebuffer iface hash table per
st manager")
Bugzilla: https://bugs.freedesktop.org/101930
Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Wed, 26 Jul 2017 01:34:54 +0000 (02:34 +0100)]
radv/ac: port SI TC L1 write corruption fix.
This ports
72e46c988 to radv.
radeonsi: apply a TC L1 write corruption workaround for SI
Fixes:
f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 26 Jul 2017 02:25:24 +0000 (03:25 +0100)]
radv/winsys: fix padding command stream for SI
We were adding pad to size after creating the object, so we could
submit a CS bigger than the bo created for it.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 26 Jul 2017 01:32:39 +0000 (02:32 +0100)]
radv/ac: realign SI workaround with radeonsi.
This ports:
da7453666ae
radeonsi: don't apply the Z export bug workaround to Hainan
to radv.
Just noticed in passing.
Fixes:
f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Thu, 15 Jun 2017 01:54:29 +0000 (18:54 -0700)]
i965/clear: Don't perform redundant depth clears
We already have this little optimization for color clears. Now that
we're actually tracking whether or not a slice has any fast-clear
blocks, it's easy enough to add for depth clears too.
Improves performance of GFXBench 4 TRex at 1920x1080 by:
- Skylake GT4: 0.905932% +/- 0.0620197% (n = 30)
- Apollolake: 0.382434% +/- 0.1134730% (n = 25)
v2: (by Ken) Rebase and drop intel_mipmap_tree.c changes, as they're
no longer necessary (other patches already landed to do that part)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 15 Jun 2017 01:54:28 +0000 (18:54 -0700)]
i965: Only do depth resolves prior to clearing when needed
When changing the clear value, we need to resolve any fast cleared data.
Previously, we were performing resolves on every slice with HiZ enabled.
We only need to resolve slices that a) have fast clear data, and b)
aren't about to be cleared to the new color. In the latter case, we
were actually doing a resolve, and then a fast clear - when we could
skip both, causing the existing fast cleared area to be updated to the
new clear value for no additional work.
This patch stops using intel_miptree_prepare_access in favor of a more
optimal open coded loop that knows about our clear operation.
v2: (by Ken) Rebase on islification, write a real commit message.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Mon, 24 Jul 2017 18:44:46 +0000 (11:44 -0700)]
i965: Expose get_num_logical_layers outside of intel_mipmap_tree.c.
I want to use it in brw_clear.c.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Marek Olšák [Mon, 24 Jul 2017 22:08:55 +0000 (00:08 +0200)]
ac/surface: fix hybrid graphics where APU=GFX9, dGPU=older
v2: don't do it for compressed textures (bpp = 0)
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Marek Olšák [Mon, 24 Jul 2017 21:56:30 +0000 (23:56 +0200)]
radeonsi: decrease the number of compiler threads
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 25 Jul 2017 15:29:58 +0000 (17:29 +0200)]
gallium/radeon: make S_FIXED function signed and move it to shared code
This fixes a bug uncovered by:
2412c4c81ea0488df865817a0de91ec46e359b72
util: Make CLAMP turn NaN into MIN.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 25 Jul 2017 15:33:05 +0000 (17:33 +0200)]
st/mesa: also clamp and quantize per-unit lod bias
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 25 Jul 2017 16:28:06 +0000 (18:28 +0200)]
st/mesa: fix unconditional return in st_framebuffer_iface_remove
Noticed by James Legg @ Feral.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Wed, 26 Jul 2017 13:21:45 +0000 (15:21 +0200)]
drirc: whitelist glthread for Mount and Blade Warband
From 25-26 min fps to 31, used the game in conjuction with a mod (full
invasion 2) beaumaris castle map and 200 bots.
Grigori Goronzy [Wed, 19 Jul 2017 21:51:55 +0000 (23:51 +0200)]
egl: move KHR_no_error vs debug/robustness check further down
We'll fail to flag an error if the context flags appear after the
no-error attribute in the context attribute list.
Delay the check to after attribute parsing to fix this.
Fixes:
4909519a665 ("egl: Add EGL_KHR_create_context_no_error support")
Cc: mesa-stable@lists.freedesktop.org
[Emil Velikov: add fixes/stable tags, commit message polish]
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:29 +0000 (18:45 -0400)]
radv: rename physical_device->uuid[] to cache_uuid[]
We have a few UUIDs, so lets be more specific.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Nicolai Hähnle [Tue, 25 Jul 2017 12:32:03 +0000 (14:32 +0200)]
radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+
The number of supported waves per thread group has been reduced to 16
with gfx9. Trying to use 32 waves causes hangs, and barriers might
not work correctly with > 16 waves.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 25 Jul 2017 14:47:27 +0000 (16:47 +0200)]
radeonsi: fix detection of DRAW_INDIRECT_MULTI on SI
The firmware version numbers for SI were wrong. The new numbers are probably
too conservative (we don't have a definitive answer by the firmware team),
but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on
Tahiti (by Gustaw) and on Verde (by myself).
While this is technically adding a feature, it's a feature we thought we had
for a long time. The change is small enough and we're early enough in the 17.2
release cycle that it should still go in.
Reported-by: Gustaw Smolarczyk <wielkiegie@gmail.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Iago Toral Quiroga [Fri, 21 Jul 2017 06:32:24 +0000 (08:32 +0200)]
anv: only expose up to 28 vertex attributes
The EU limit of 128 GRFs should allow 32 vertex elements of 4 GRFs.
However, the maximum allowed value of "Vertex URB Entry Read Length"
in SIMD8 is 15. And 15 * 8 = 120 gives us a limit of 30 vertex elements.
Because we also need to reserve a vertex buffer to upload
VertexIndex/InstanceIndex and another to upload DrawID when needed,
we can only expose 28.
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Iago Toral Quiroga [Wed, 19 Jul 2017 10:49:33 +0000 (12:49 +0200)]
anv/cmd_buffer: fix off by one error in assertion
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Tue, 25 Jul 2017 17:27:03 +0000 (10:27 -0700)]
i965: Shut up Coverity warning about HiZ buffers.
Here the AUX_USAGE_* mode indicates that we have HiZ, so we will have
a HiZ buffer. But Coverity doesn't know that, so it thinks it might
be NULL because we checked hiz_buf != NULL earlier.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 25 Jul 2017 17:22:01 +0000 (10:22 -0700)]
i965: Fix = vs == in MCS aux usage assert.
Caught by Coverity (CID 1415680).
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 25 Jul 2017 17:16:16 +0000 (10:16 -0700)]
i965: Fix offset addition in get_isl_surf.
Increase the value, not the pointer to the stack variable.
Caught by Coverity (CID 1415574). Not shipped in a real release.
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:17 +0000 (18:45 -0400)]
mesa/st: fix inconsistent indentation of st_cb_bufferobjects.c
No changes, just re-indent.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Timothy Arceri [Fri, 21 Jul 2017 00:23:47 +0000 (10:23 +1000)]
compiler: move glsl_interface_packing enum to shader_enums.h
This allows us to drop the duplicate gl_uniform_block_packing enum.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 20 Jul 2017 00:06:32 +0000 (10:06 +1000)]
mesa/st: fix unused variable warnings
Reviewed-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 20 Jul 2017 00:04:40 +0000 (10:04 +1000)]
mesa/st: move st_pipe_format_to_mesa_format() call to where its used
Reviewed-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 20 Jul 2017 00:03:28 +0000 (10:03 +1000)]
gallium/util: fix unused variable warning
Reviewed-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 25 Jul 2017 23:13:33 +0000 (09:13 +1000)]
mesa: drop useless assert
NewBufferObj() is called when the shared state is allocated so we
wouldn't get this far if it was NULL.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Tue, 25 Jul 2017 13:16:14 +0000 (23:16 +1000)]
mesa: call binding functions directly from glDeleteBuffers
This avoids useless error checking.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Tue, 25 Jul 2017 13:34:06 +0000 (23:34 +1000)]
mesa: move static binding functions above _mesa_DeleteBuffers()
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Tue, 25 Jul 2017 13:06:03 +0000 (23:06 +1000)]
mesa: don't try to re-generate the default buffer
It should have been created by this point.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Eric Anholt [Thu, 13 Jul 2017 19:42:49 +0000 (12:42 -0700)]
broadcom/vc4: Switch the V3D 2.1 XML over to restricted address fields.
This keeps the flags out of v3d_decode.c's output. In the generated code,
only the unpack functions see any change (where they now get the
restricted start value), and vc4 doesn't use the unpack functions yet.
Eric Anholt [Thu, 13 Jul 2017 19:40:58 +0000 (12:40 -0700)]
broadcom/genxml: Support address fields with <32 bits
I was writing the XML such that the address field overlapped various flags
in the alignment bits, which caused pain when trying to unpack for decode.
Instead, keep the XML matching the docs (address fields don't overlap),
and just infer the appropriate shift value during decode.
During pack, the address is just applied to the appropriate bits
already, ignoring the sub-byte start/end fields.
Eric Anholt [Thu, 4 May 2017 21:44:38 +0000 (14:44 -0700)]
broadcom/vc4: Use the RA callback to improve register selection's choices.
We simply pick r4 if available (anything else would force a MOV), then
round-robin through accumulators (avoids physical regfile RAW delay
slots), then round-robin through the physical regfile.
The effect on instruction count is pretty impressive:
total instructions in shared programs: 76563 -> 74526 (-2.66%)
instructions in affected programs: 66463 -> 64426 (-3.06%)
and we could probably do better with a little heuristic of "if we're going
to choose a physical reg, and other operands of instructions using this as
a src have the same physical regfile, then use the other regfile".
Eric Anholt [Fri, 23 Oct 2015 21:12:27 +0000 (22:12 +0100)]
ra: Add a callback for selecting a register from what's available.
VC4 has had a tension, similar to pre-Sandybridge Intel, where we want to
use low-numbered registers (more parallelism on Intel, fewer delay slots
on vc4), but in order to give instruction scheduling the most freedom to
avoid delays we want to round-robin between registers of the same cost.
Our two heuristics so far have chosen one end or the other of that
tradeoff.
The callback, instead, hands the driver the set of registers that are
available, and the driver gets to make its own choice. This will be used
in vc4 to round-robin between registers of the same cost, and might be
used in the future for improving bank selection.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Thu, 4 May 2017 22:49:39 +0000 (15:49 -0700)]
ra: Don't put a node in its own adjacency set.
All the paths looping over adjacency had guards against considering
themselves (the non-obvious one was ra_any_neighbors_conflict(), which has
in_stack set).
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Fri, 23 Oct 2015 20:46:40 +0000 (21:46 +0100)]
ra: Pull the body of a loop out to a helper function.
I was going to indent this code another level, and decided it would be
easier to read as a helper.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Mon, 24 Jul 2017 21:45:49 +0000 (14:45 -0700)]
broadcom/vc4: Scissor blits performed using the rendering engine.
Without this, a BlitFramebuffer would mark the whole framebuffer as being
changed (so we emit loads/stores of all of it) rather than just the
modified subset.
Eric Anholt [Mon, 24 Jul 2017 19:34:23 +0000 (12:34 -0700)]
broadcom/vc4: Prefer blit via rendering to the software fallback.
I don't know how I managed to leave this here for so long. Found when
working on a 1:1 overlapping blit extension for X11.
Cc: mesa-stable@lists.freedesktop.org
Eric Anholt [Wed, 12 Jul 2017 22:56:00 +0000 (15:56 -0700)]
broadcom/vc4: Switch the Viewport Center fields to a fixed-point representation.
This gets us automatic CL decoding to a floating-point value, and drops a
magic number from the emit code. 250x250 shader runner tests now say they
have a center of 125.0 instead of 2000.
Eric Anholt [Wed, 12 Jul 2017 21:22:02 +0000 (14:22 -0700)]
broadcom/vc4: Use the XML decoder for CL dumping.
The VC4_DEBUG_CL output goes from:
0x00000010 0x00000010: 0x06 VC4_PACKET_START_TILE_BINNING
0x00000011 0x00000011: 0x38 VC4_PACKET_PRIMITIVE_LIST_FORMAT
0x00000012 0x00000012: 0x12
0x00000013 0x00000013: 0x66 VC4_PACKET_CLIP_WINDOW
0x00000014 0x00000014: 0x00
0x00000015 0x00000015: 0x00
0x00000016 0x00000016: 0x00
0x00000017 0x00000017: 0x00
0x00000018 0x00000018: 0xfa
0x00000019 0x00000019: 0x00
0x0000001a 0x0000001a: 0xfa
0x0000001b 0x0000001b: 0x00
to:
0x00000010 0x00000010: 0x06 Start Tile Binning
0x00000011 0x00000011: 0x38 Primitive List Format
Data Type: 1 (16-bit index)
Primitive Type: 2 (Triangles List)
0x00000013 0x00000013: 0x66 Clip Window
Clip Window Height in pixels: 250
Clip Window Width in pixels: 250
Clip Window Bottom Pixel Coordinate: 0
Clip Window Left Pixel Coordinate: 0
v2: Squash in robher's fixes for Android
Eric Anholt [Wed, 12 Jul 2017 20:15:34 +0000 (13:15 -0700)]
broadcom/genxml: Introduce a V3D packet/struct decoder.
This is copied from Intel's XML decoder, modified to handle V3D's
byte-oriented packets.
v2: Squash in robher's fixes for Android
Eric Anholt [Fri, 3 Feb 2017 21:30:42 +0000 (13:30 -0800)]
broadcom: add editorconfig
This is the same 8-space style used in the vc4 and vc5 gallium drivers.
Eric Anholt [Wed, 12 Jul 2017 20:22:46 +0000 (13:22 -0700)]
intel/decoder: Reuse the gen_make_gen() helper.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Anholt [Wed, 12 Jul 2017 20:11:34 +0000 (13:11 -0700)]
intel/decoder: Reuse the MAX2 macro instead of defining another one.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Brian Paul [Fri, 21 Jul 2017 16:37:36 +0000 (10:37 -0600)]
svga: implement MSAA alpha_to_one feature
The device doesn't directly support this feature so we implement it with
additional shader code which sets the color output(s) w component to
1.0 (or max_int or max_uint).
Fixes 16 Piglit ext_framebuffer_multisample/*alpha-to-one* tests.
v2: only support unorm/float buffers, not int/uint, per Roland.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Fri, 21 Jul 2017 15:38:10 +0000 (09:38 -0600)]
svga: rework the FS white fragments code
When we forcibly write white to FS outputs (for XOR mode emulation)
we were using a temp register. But that's not really necessary.
This also fixes the case of writing white to multiple color buffers.
Subsequent changes will build on this.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Fri, 21 Jul 2017 20:08:01 +0000 (14:08 -0600)]
gallium/util: s/unsigned/enum tgsi_texture_type/
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Kamil Páral [Tue, 25 Jul 2017 19:28:40 +0000 (21:28 +0200)]
drirc: whitelist glthread for Overlord 1+2, Oil Rush, War Thunder, Saints Row 2
Performance delta on Core i5-4570 + Radeon R9 270:
Overlord: +20% in certain locations
Overlord II: +20% in certain locations
Oil Rush: +12% in most locations
War Thunder: +4-9% in benchmarks
Saints Row 2: +10-35% in certain locations
Lionel Landwerlin [Tue, 25 Jul 2017 16:49:22 +0000 (17:49 +0100)]
i965: perf: flush batchbuffers at the beginning of queries
As Chris commented, it makes more sense to have batch buffer flushes
before the query. Usually applications like frame_retrace do a series
of queries and in that case, with flushes at the end of the queries,
we might still have the first query contained in 2 different batchs.
More generally it would be quite usual to have the query contained in
2 batch buffers because we never now what's the fill rate of the
current batch buffer.
If we move the flushing at the beginning of the queries, it's pretty
much guaranteed that queries will be contained in a single batch
buffer (unless the amount of commands is huge, but then it's only fair
to include reloading request times in the measurements).
Fixes:
adafe4b733c02 ("i965: perf: minimize the chances to spread queries across batchbuffers")
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Daniel Stone [Fri, 21 Jul 2017 12:55:42 +0000 (13:55 +0100)]
st/dri2: Return invalid modifier when no driver support
Always initialise whandle.modifier for DRIImage modifier queries, so if
the driver doesn't support it then we return false for the query.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes:
d33fe8b84e45 ("st/dri: enable DRIimage modifier queries")
Daniel Stone [Mon, 24 Jul 2017 13:42:56 +0000 (14:42 +0100)]
st/dri: Check get-handle return value in queryImage
In the DRIImage queryImage hook, check if resource_get_handle() failed
and return FALSE if so.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Michal Srb [Mon, 17 Jul 2017 07:34:44 +0000 (09:34 +0200)]
r600: Add support for B5G5R5A1.
Fixes rendercheck errors when using glamor acceleration in X server.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Leo Liu [Tue, 18 Jul 2017 13:48:02 +0000 (09:48 -0400)]
radeon/vcn: move message buffer to vram for now
To workaround an unknown bug.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Jose Fonseca [Mon, 24 Jul 2017 13:20:03 +0000 (14:20 +0100)]
trace: Correct transfer box size calculation.
For textures we must not approximate the calculation with `stride *
height`, or `slice_stride * depth`, as that can easily lead to buffer
overflows, particularly for partial transfers.
This should address the issue that Bruce Cherniak found and diagnosed.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Samuel Pitoiset [Fri, 21 Jul 2017 13:16:06 +0000 (15:16 +0200)]
mesa: add active_shader_program() helper
To reduce code duplication.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Samuel Pitoiset [Fri, 21 Jul 2017 13:16:05 +0000 (15:16 +0200)]
mesa: add bind_program_pipeline() helper
To reduce code duplication.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tapani Pälli [Mon, 24 Jul 2017 11:10:50 +0000 (14:10 +0300)]
egl: fix whitespace issues from eglimage code
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tapani Pälli [Tue, 25 Jul 2017 05:38:03 +0000 (08:38 +0300)]
util: fix warning/error on 32bit build
Add uintptr_t cast to fix 'cast to pointer from integer of different size'
warning on 32bit build (build error on Android M).
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Constantine Charlamov [Mon, 17 Jul 2017 01:04:51 +0000 (04:04 +0300)]
r600g: constify some args at r600_asm.c
Signed-off-by: Constantine Kharlamov <Hi-Angel@yandex.ru>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Constantine Charlamov [Mon, 17 Jul 2017 01:04:50 +0000 (04:04 +0300)]
r600g: remove unused "bc" args, and one unneeded forward declaration
To ease review just highlight "bc," string.
Signed-off-by: Constantine Kharlamov <Hi-Angel@yandex.ru>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Tue, 25 Jul 2017 00:19:21 +0000 (10:19 +1000)]
radv: only report external semaphore info for opaque fd.
Until we support sync fd, don't report the info.
Fixes CTS dEQP-VK.api.external.semaphore.sync_fd.* from crashing.
Fixes:
eaa56eab6 (radv: initial support for shared semaphores (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Thu, 15 Jun 2017 01:54:27 +0000 (18:54 -0700)]
i965: Simplify HiZ clears a bit
No need for all that switching when we can just assign a nice little
variable with the number of layers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Wed, 12 Jul 2017 23:36:03 +0000 (16:36 -0700)]
i965: Use {} to initialize GENX_* structs.
gen4 have commands which start with KernelStartPointer, which is a
struct, so if we initialize it struct = { 0 }, we get warnings on some
compilers:
"GCC (pre 4.9?) can throw a Wmissing-braces on[1] while clang
-Wmissing-field-initializers [2]." - Emil
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
[2] https://bugs.llvm.org/show_bug.cgi?id=21689
This change works around that and will silence such warnings. It is both
a GCC and a clang extension.
v2:
- Use {} instead of memset macro (Matt)
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>