Simon Glass [Mon, 2 Aug 2021 00:57:11 +0000 (18:57 -0600)]
doc: Update devicedocs including how to add tweaks
This file is about 10 years old and the updates have not covered
everything that has changed, particularly in the last few years. Update
the information and add mention of the u-boot.dtsi files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fix typos.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Mon, 2 Aug 2021 00:57:10 +0000 (18:57 -0600)]
doc: Move devicetree control doc to rST
Move this to rST format, largely unchanged to start with. Add an index
for this topic, as well as an empty intro.
Note this patch does not include updates! Is it just a conversion to the
new format. See the next patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchart <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 5 Aug 2021 18:18:06 +0000 (20:18 +0200)]
doc: fix Latex margins
Adjust the Latex formatting to match Linux v5.13.1:
* add Latex margins
* reformat the code in doc/conf.py to match Linux
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 5 Aug 2021 18:13:41 +0000 (20:13 +0200)]
doc: require Sphinx 2.4.4
Require Sphinx 2.44 to build the documentation.
Remove all code related to earlier versions.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 2 Aug 2021 20:10:04 +0000 (22:10 +0200)]
doc: add pkg-config to the build dependencies
tools/Makefile uses pkg-config.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Fri, 13 Aug 2021 12:37:47 +0000 (08:37 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Enable SeaBIOS support for Crown Bay
- Update SeaBIOS build instructions in the x86 doc
- Enable CONFIG_SPI_FLASH_SMART_HWCAPS for Crown Bay
Bin Meng [Wed, 4 Aug 2021 03:53:39 +0000 (11:53 +0800)]
x86: crownbay: Enable CONFIG_SPI_FLASH_SMART_HWCAPS
Now that the spi-nor fix has been made in u-boot/master via:
commit
87e7219f9c6a ("mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()")
enable CONFIG_SPI_FLASH_SMART_HWCAPS on Intel Crown Bay again.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 3 Aug 2021 12:50:04 +0000 (20:50 +0800)]
doc: x86: Update SeaBIOS build instructions
Update SeaBIOS build instructions using exact command that involves
"make olddefconfig", and mention SeaBIOS release 1.14.0 has been
used for testing.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 3 Aug 2021 12:50:03 +0000 (20:50 +0800)]
x86: crownbay: Enable SeaBIOS support
Enable SeaBIOS support for any kernel that requires legacy BIOS
services.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 12 Aug 2021 13:33:39 +0000 (09:33 -0400)]
Merge tag 'u-boot-rockchip-
20210812' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add Rockchip SFC driver support;
- DTS sync from kernel;
- emmc hs400 support for rk3399;
- Fix for spinore bootdevice and MMC boot order;
Jon Lin [Thu, 5 Aug 2021 08:27:53 +0000 (16:27 +0800)]
rockchip: px30: Support configure SFC
Make px30 SFC clock configurable
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Thu, 5 Aug 2021 08:27:52 +0000 (16:27 +0800)]
rockchip: px30: add support for SFC for Odroid Go Advance
The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Changing the pinctrl to bus2 and setting tx
and rx lines to 2 for this reason.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Thu, 5 Aug 2021 08:26:41 +0000 (16:26 +0800)]
mtd: spi-nor-ids: Add XTX XT25F128B
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
this chip uses a continuation code which I cannot seem to parse, so
there are possibly going to be collisions with chips that use the same
manufacturer/ID.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Thu, 5 Aug 2021 08:26:40 +0000 (16:26 +0800)]
rockchip: px30: add the serial flash controller
Add the serial flash controller to the devicetree for the PX30.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Thu, 5 Aug 2021 08:26:39 +0000 (16:26 +0800)]
rockchip: px30: Add support for using SFC
This patch adds support for setting the correct pin configuration
for the Rockchip Serial Flash Controller found on the PX30.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Thu, 5 Aug 2021 08:26:38 +0000 (16:26 +0800)]
spi: rockchip_sfc: add support for Rockchip SFC
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Gunnarsson [Sun, 25 Jul 2021 14:25:58 +0000 (16:25 +0200)]
rockchip: Fix u-boot-rockchip.bin build
Currently there are a few arm32 rockchip board configs that don't
generate u-boot-rockchip.bin when running make because CONFIG_BINMAN
is not enabled. This patch changes CONFIG_ARCH_ROCKCHIP to also select
CONFIG_BINMAN if CONFIG_SPL and !CONFIG_ARM64.
Example builds that don't generate u-boot-rockchip.bin without this
patch:
export ARCH=arm
export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf-
make kylin-rk3036_defconfig
make
export ARCH=arm
export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf-
make rock_defconfig
make
export ARCH=arm
export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf-
make tinker-rk3288_defconfig
make
Signed-off-by: Johan Gunnarsson <johan.gunnarsson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Thu, 22 Jul 2021 15:20:44 +0000 (16:20 +0100)]
arm: dts: sync the Rockhip 3368 SoCs from Linux
Sync the rk3368 DTs and associated bits from 5.14-rc1.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Thu, 22 Jul 2021 15:20:43 +0000 (16:20 +0100)]
arm: dts: sync the Rockhip 3328 SoCs from Linux
Sync the rk3328 DTs and associated bits from 5.14-rc1.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Thu, 22 Jul 2021 15:20:42 +0000 (16:20 +0100)]
arm: dts: sync the Rockhip 3399 SoCs from Linux
Sync the rk3399 DTs and associated bits from 5.14-rc1.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
(Remove the conflict content for vmarc-som)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Wed, 11 Aug 2021 12:31:56 +0000 (08:31 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flash
- Some CFI flash related fixups (Kconfig & header) (Bin)
- Enable CFI flash support on the QEMU RISC-V virt machine. (Bin)
Tom Rini [Wed, 11 Aug 2021 12:31:25 +0000 (08:31 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Convert GoFlex Home Ethernet and SATA to Driver Model (Tony)
- mvebu: Automatically detect CONFIG_SYS_TCLK (Pavel)
- mvebu: sata_mv: Fix HDD identication during cold start (Tony)
- a37xx: pci: Fix handling PIO config error responses (Pavel)
- Other minor misc changes and board maintainer updates
Tom Rini [Wed, 11 Aug 2021 12:31:13 +0000 (08:31 -0400)]
Merge tag 'u-boot-amlogic-
20210810' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- odroid-n2: fix fdtfile suffix for n2-plus
- sei610 & meson64_android cleanups to prepare android 11 boot support
- use Android BCB mechanism for reboot reason instead of HW reboot flag
- Switch meson64_android boot flow to use abootimg for A/B, AVB and DTBO support
Xiaobo Tian [Tue, 6 Jul 2021 14:43:59 +0000 (22:43 +0800)]
arm64: rk3399: r4s: Remove undesirable MAC address fetching methods for ethernet
Remove the recommended MAC address from the network card.
NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which stores the MAC address.
Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Xiaobo Tian [Tue, 6 Jul 2021 14:43:58 +0000 (22:43 +0800)]
arm64: rk3399: r4s: Inheritance uses the sdmmc definition in dtsi
The host-index-min property is invalid,
so it inherits from the sdmmc definition in dtsi.
Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Xiaobo Tian [Tue, 6 Jul 2021 14:43:57 +0000 (22:43 +0800)]
arm64: rk3399: r4s: correct the LEDS label name
Correct the LEDS label name and remove the board type prefix,
which is actually unnecessary here, removes the redefined system status LED pin.
Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yifeng Zhao [Tue, 29 Jun 2021 08:24:43 +0000 (16:24 +0800)]
rockchip: config: evb-rk3399: add hs400 and SDMA support
This enable hs400 and SDMA support for emmc on evb-rk3399.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yifeng Zhao [Tue, 29 Jun 2021 08:24:42 +0000 (16:24 +0800)]
mmc: rockchip_sdhci: Add support for RK3568
This patch adds support for the RK3568 platform to this driver.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yifeng Zhao [Tue, 29 Jun 2021 08:24:41 +0000 (16:24 +0800)]
mmc: rockchip_sdhci: add phy and clock config for rk3399
Add clock, phy and other configuration, it is convenient to support
new controller. Here a short summary of the changes:
- Add mmc_of_parse to parse dts config.
- Remove OF_PLATDATA related code.
- Reorder header inclusion.
- Add phy ops.
- add ops set_ios_post to modify the parameters of phy when the
clock changes.
- Add execute tuning api for hs200 tuning.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Fri, 25 Jun 2021 13:26:33 +0000 (15:26 +0200)]
ARM: dts: rockchip: update rk3188-radxarock.dts
In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently
had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Fri, 25 Jun 2021 13:26:32 +0000 (15:26 +0200)]
ARM: dts: rockchip: update rk3188.dtsi
In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently
had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3188-u-boot.dtsi file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Fri, 25 Jun 2021 13:26:31 +0000 (15:26 +0200)]
rockchip: rk3188-power: sync power domain dt-binding header from Linux
In order to update the DT for rk3188
sync the power domain dt-binding header.
This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Fri, 25 Jun 2021 13:26:30 +0000 (15:26 +0200)]
ARM: dts: rockchip: update rk3xxx.dtsi
In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. This file has recently had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Fri, 25 Jun 2021 13:26:29 +0000 (15:26 +0200)]
rockchip: rk3188-cru-common: sync clock dt-binding header from Linux
In order to update the DT for rk3066 and rk3188
sync the clock dt-binding header.
This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Artem Lapkin [Wed, 26 May 2021 09:32:27 +0000 (17:32 +0800)]
rk3399: boot_devices fix spinor node name
Problem: board_spl_was_booted_from return wrong boot_devices[3] value
/spi@
ff1d0000 and same-as-spl dont work properly for SPINOR flash
because arch/arm/mach-rockchip/spl-boot-order.c spl_node_to_boot_device
need parse SPINOR flash node as UCLASS_SPI_FLASH
spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
/spi@
ff1d0000 > board_boot_order: could not map node @618 to a boot-device
/sdhci@
fe330000 > /mmc@
fe320000
Solution: just change it to /spi@
ff1d0000/flash@0
spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
/spi@
ff1d0000/flash@0 > /sdhci@
fe330000 > /mmc@
fe320000
Signed-off-by: Artem Lapkin <art@khadas.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Alex Bee [Thu, 17 Jun 2021 09:01:12 +0000 (11:01 +0200)]
rockchip: Fix MMC boot order
Basically all, i.e. rk3036.dtsi, rk3128.dtsi, rk3xxx.dtsi, rk322x.dtsi,
rk3288.dtsi, rk3308-u-boot.dtsi, rk3328-u-boot.dtsi, rk3399-u-boot.dtsi
and px30-u-boot.dtsi Rockchip SoC devicetrees which have mmc indexes
are defining eMMC as mmc0 and sdmmc as mmc1.
This means that the rule to try to boot from the SD card first is ignored,
which as per comment is what we want and is important for distros, which
rely on that.
Fix this by setting the correct mmc index, i.e. first from mmc1 (SD card),
second from mmc0 (eMMC).
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Bin Meng [Sat, 7 Aug 2021 05:00:02 +0000 (13:00 +0800)]
riscv: qemu: Enable MTD NOR flash support
Enable support to the 2 NOR flashes on the QEMU RISC-V virt machine.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Bin Meng [Sat, 7 Aug 2021 05:00:01 +0000 (13:00 +0800)]
flash.h: Remove CONFIG_SYS_FLASH_CFI from flash_info_t
Those embers wrapped with CONFIG_SYS_FLASH_CFI in struct flash_info_t
are unconditionally used in the cfi_flash.c driver.
Drop the #ifdefs in the definition of flash_info_t.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Bin Meng [Sat, 7 Aug 2021 05:00:00 +0000 (13:00 +0800)]
mtd: kconfig: Fix CFI_FLASH dependency
The DM version CFI flash driver is in driver/mtd/cfi_flash.c, which
only gets built when FLASH_CFI_DRIVER is on. If CFI_FLASH is on but
FLASH_CFI_DRIVER is not, nothing is enabled at all.
Fix this dependency by selecting FLASH_CFI_DRIVER when CFI_FLASH is
enabled.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Tue, 10 Aug 2021 06:53:17 +0000 (23:53 -0700)]
arm: kirkwood: Goflex Home: Update board maintainer
Change maintainer to me. Suriyan no longer has this board and wishes
to see someone maintaining it actively.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Tue, 10 Aug 2021 06:10:42 +0000 (23:10 -0700)]
arm: kirkwood: Dockstar: Update board maintainer
Change maintainer to me. Eric no longer has this board and wishes
to see someone maintaining it actively.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 9 Aug 2021 15:44:35 +0000 (17:44 +0200)]
arm: mvebu: Hang if ddr3_init() fails
If ddr3_init() fails then DDR was not initialized and we cannot load and
execute U-Boot. We cannot continue, we cannot do anything in this case, so
hang.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 9 Aug 2021 07:53:13 +0000 (09:53 +0200)]
arm: a37xx: pci: Fix handling PIO config error responses
Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to OS is
allowed only for 4-byte PCI_VENDOR_ID config read request and only when
CRSSVE bit in Root Port PCIe device is enabled. In all other error PCIe
Root Complex must return all-ones.
So implement this logic in pci-aardvark.c driver properly.
aardvark HW does not have Root Port PCIe device and U-Boot does not
implement emulation of this device. So expect that CRSSVE bit is set as
U-Boot can already handle CRS value for PCI_VENDOR_ID config read request.
More callers of pci_bus_read_config() function in U-Boot do not check for
return value, but check readback value. Therefore always fill readback
value in pcie_advk_read_config() function. On error fill all-ones of
correct size as it is required for PCIe Root Complex.
And also correctly propagates error from failed config write request to
return value of pcie_advk_write_config() function. Most U-Boot callers
ignores this return value, but it is a good idea to return correct value
from function.
These issues about return value of failed config read requests, including
special handling of CRS were reported by Lorenzo and Bjorn for Linux kernel
driver pci-aardvark together with quotes from PCIe r4.0 spec, see details:
https://lore.kernel.org/linux-pci/
20210624213345.3617-1-pali@kernel.org/t/#u
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Sun, 1 Aug 2021 03:29:35 +0000 (20:29 -0700)]
arm: mvebu: sata_mv failed to identify HDDs during cold start
During cold start, with some HDDs, mv_sata_identify() does not populate
the ID words on the 1st ATA ID command. In fact, the first ATA ID
command will only power up the drive, and then the ATA ID command
processing is lost in the process.
Tests with:
- Seagate ST9250320AS 250GB HDD and Seagate ST4000DM004-2CV104 4TB HDD.
- Zyxel NSA310S (Kirkwood 88F6702), Marvell Dreamplug (Kirkwood 88F6281),
Seagate GoFlex Home (Kirkwood 88F6281), Pogoplug V4 (Kirkwood 88F6192).
Observation:
- The Seagate ST9250320AS 250GB took about 3 seconds to spin up.
- The Seagate ST4000DM004-2CV104 4TB took about 8 seconds to spin up.
- mv_sata_identify() did not populate the ID words after the call to
mv_ata_exec_ata_cmd_nondma().
- Attempt to insert a long delay of 30 seconds, ie. mdelay(30_000), after
the call to ata_wait_register() inside mv_ata_exec_ata_cmd_nondma() did
not help with the 4TB drive. The ID words were still empty after that 30s
delay.
Patch Description:
- Added a second ATA ID command in mv_sata_identify(), which will be
executed if the 1st ATA ID command did not return with valid ID words.
- Use the HDD drive capacity in the ID words as a successful indicator of
ATA ID command.
- In the scenario where a box is rebooted, the 1st ATA ID command is always
successful, so there is no extra time wasted.
- In the scenario where a box is cold started, the 1st ATA command is the
power up command. The 2nd ATA ID command alleviates the uncertainty of
how long we have to wait for the ID words to be populated by the SATA
controller.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Pali Rohár [Sat, 31 Jul 2021 12:22:56 +0000 (14:22 +0200)]
arm: kirkwood: Do not overwrite CONFIG_SYS_TCLK
Config option CONFIG_SYS_TCLK is set by kw88f6281.h and kw88f6192.h files
to correct SOC/platform value. So do not overwrite it in board config
include files.
Kirkwood 88F6180 and 88F6192 uses 166 MHz TCLK and Kirkwood 88F6281 uses
200 MHz TCLK.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Sat, 31 Jul 2021 12:22:55 +0000 (14:22 +0200)]
arm: mvebu: axp: Set CONFIG_SYS_TCLK globally
This mvebu axp platform always uses fixed 250 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.
Now every #if-#else case of soc.h file defines CONFIG_SYS_TCLK, so remove
useless default CONFIG_SYS_TCLK value from the end of soc.h file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Sat, 31 Jul 2021 12:22:54 +0000 (14:22 +0200)]
arm: mvebu: msys: Set CONFIG_SYS_TCLK globally
This mvebu msys platform always uses fixed 200 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Sat, 31 Jul 2021 12:22:53 +0000 (14:22 +0200)]
arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR register
Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Sat, 31 Jul 2021 12:22:52 +0000 (14:22 +0200)]
arm: mvebu: a38x: Detect CONFIG_SYS_TCLK from SAR register
Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Fri, 30 Jul 2021 03:02:43 +0000 (20:02 -0700)]
arm: kirkwood: GoFlex Home: Use Ethernet PHY name and address from device tree
In DM Ethernet, the old "egiga0" name is no longer valid,
so replace these with Ethernet PHY names from device tree. Also, read
Ethernet PHY address from device tree.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Fri, 30 Jul 2021 03:02:42 +0000 (20:02 -0700)]
arm: kirkwood: GoFlex Home: Add DM SATA configs
Enable DM SATA in board file.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Fri, 30 Jul 2021 03:02:41 +0000 (20:02 -0700)]
arm: kirkwood: GoFlex Home: Add DM Ethernet, remove IDE, and add DM SATA configs
Add DM_ETH, SATA_MV and associated configs to goflexhome_defconfig.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Tue, 10 Aug 2021 19:08:46 +0000 (15:08 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Guillaume La Roque [Thu, 5 Aug 2021 15:17:28 +0000 (17:17 +0200)]
configs: sei510/610: android bootflow via abootimg
Activate the following Kconfig options:
* AVB for Android Verified Boot support
* ADTIMG for merging DTBOs
* ABOOTIMG for extracting Android boot image
Also rework the partitioning tables:
- add a misc partition to handle BCB messages
- add a dtbo partition to store various DTBOs
- add a vbmeta partition for AVB hashes
- Merge vendor and system into the "super" partition
Note: avb support is disables by default. To activate it:
=> setenv force_avb 1;
=> saveenv;
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Mattijs Korpershoek [Thu, 5 Aug 2021 15:17:27 +0000 (17:17 +0200)]
configs: sei510/sei610: don't use hard-coded gpt uuids
doc/README.gpt states:
> The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
> enabled. A random uuid will be used if omitted or they point to an empty/
> non-existent environment variable. The environment variable will be
> set to the generated UUID. The 'gpt guid' command reads the current
> value of the uuid_disk from the GPT.
Since we have CONFIG_RANDOM_UUID=y, remove the hard-coded uuids
and use meaningful variable names instead.
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Mattijs Korpershoek [Thu, 5 Aug 2021 15:17:26 +0000 (17:17 +0200)]
configs: sei510/sei610: reformat PARTS_default
There is a mix of spaces and tabs at the leading \. This makes updating
theses lines harder.
Add a single space before each \ for some consistency.
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Guillaume La Roque [Thu, 5 Aug 2021 15:17:25 +0000 (17:17 +0200)]
configs: meson64_android: boot android via abootimg
Since Android 10, we are required to use a "dtbo" partition which
includes the various device-tree overlays [1].
It's also possible to provide a "dtb" partition.
This is supported via the "abootimg" command.
On Yukawa, the assumption is that we have only a "dtbo" partition, which
includes all board dtbs and their dtbos [2]
[1] https://source.android.com/devices/architecture/dto/partitions
[2] https://android.googlesource.com/device/amlogic/yukawa/+/refs/heads/master/build/tasks/dtimages.mk#16
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Mattijs Korpershoek [Thu, 5 Aug 2021 15:17:24 +0000 (17:17 +0200)]
configs: meson64_android: define BOOT_CMD macro
BOOT_CMD might be different based on CONFIG_CMD_ABOOTIMG.
To prepare for abootimg support, extract the boot command
to a dedicated macro.
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Mattijs Korpershoek [Thu, 5 Aug 2021 15:17:23 +0000 (17:17 +0200)]
configs: meson64_android: implement A/B slot support
Implement A/B slot selection using the U-Boot ab_select command.
Keep support for non A/B.
Not: We need to redefine the recovery partition label, as RecoveryOS
is included in the boot image for A/B systems [1]
[1] https://source.android.com/devices/tech/ota/ab/ab_implement#recovery
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Mattijs Korpershoek [Thu, 5 Aug 2021 15:17:22 +0000 (17:17 +0200)]
configs: meson64_android: implement AVB support
AVB (Android Verified Boot) is well supported in U-Boot already.
Add support for it in meson64_android.
This is controlled by the "force_avb" environment variable and the
CONFIG_CMD_AVB option.
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Mattijs Korpershoek [Thu, 5 Aug 2021 15:17:21 +0000 (17:17 +0200)]
configs: meson64_android: increase SYS_MALLOC_LEN to 128M for AVB
To prepare for AVB support, increase SYS_MALLOC_LEN to 128M.
This value has been found by testing the following on khadas vim3l:
=> avb init
=> avb verify
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Mattijs Korpershoek [Thu, 5 Aug 2021 15:17:20 +0000 (17:17 +0200)]
configs: meson64: permit redefining SYS_MALLOC_LEN
Permit redefining SYS_MALLOC_LEN for board specific configs.
This is especially useful for Android with AVB, which requires a malloc
length of 128M.
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Christian Hewitt [Wed, 4 Aug 2021 11:01:07 +0000 (11:01 +0000)]
board: amlogic: odroid-n2: fix fdtfile suffix for n2-plus
The N2+ dtb is meson-g12b-odroid-n2-plus.dtb, not n2_plus, so
correct the suffix provided in the board file. Also align the
board ident string shown during boot to match.
Fixes:
8bc780106c13 ("board: amlogic: odroid: add runtime detection of the N2/N2+/C4/HC4 variants")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tom Rini [Mon, 9 Aug 2021 13:27:26 +0000 (09:27 -0400)]
Merge tag 'u-boot-imx-
20210809' of https://source.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-
20210809
- new SOC: add support for imx8ulp
- Toradex fixes for colibri (vf / imx6 / imx7 / imx8x)
- convert to DM for mx28evk
- Fixes for Gateworks ventana boards
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8639
Tom Rini [Mon, 9 Aug 2021 13:27:06 +0000 (09:27 -0400)]
Merge tag 'dm-pull-8aug21' of https://source.denx.de/u-boot/custodians/u-boot-dm
Use log subsystem for dm_warn()
Various minor bug fixes
Peng Fan [Sat, 7 Aug 2021 08:21:34 +0000 (16:21 +0800)]
imx: cmd: use struct cmd_tbl
cmd_tbl_t is removed, need use struct cmd_tbl
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:01:13 +0000 (16:01 +0800)]
arm: imx: add i.MX8ULP EVK support
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART
Log as below: I would keep some debug info for now, and after we move
to be stable and production launch, we could drop that.
U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)
Normal Boot
upower_init: soc_id=48
upower_init: version:11.11.6
upower_init: start uPower RAM service
user_upwr_rdy_callb: soc=b
user_upwr_rdy_callb: RAM version:12.6
Turn on switches ok
Turn on memories ok
Clear DDR retention ok
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F0 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
complete
De-Skew PLL is locked and ready
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Load image from 0x3a800 by ROM_API
NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94
NOTICE: BL31: Built : 01:56:58, Jun 29 2021
NOTICE: upower_init: start uPower RAM service
NOTICE: user_upwr_rdy_callb: soc=b
NOTICE: user_upwr_rdy_callb: RAM version:12.6
U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)
CPU: Freescale i.MX8ULP rev1.0 at 744 MHz
Reset cause: POR
Boot mode: Single boot
Model: FSL i.MX8ULP EVK
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... ***
Warning - bad CRC, using default environment
In: serial@
293a0000
Out: serial@
293a0000
Err: serial@
293a0000
Net:
Warning: ethernet@
29950000 (eth0) using random MAC address -
96:35:88:62:e0:44
eth0: ethernet@
29950000
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:01:12 +0000 (16:01 +0800)]
arm: dts: add i.MX8ULP dtsi
Add i.MX8ULP dtsi
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:01:11 +0000 (16:01 +0800)]
ddr: Add DDR driver for iMX8ULP
Add iMX8ULP DDR initialization driver which loads the DDR timing
parameters and executes the training procedure.
When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode
to do DDR init
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:01:10 +0000 (16:01 +0800)]
imx8ulp: add upower api support
Add upower api support, this is modified from upower firmware exported
package.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:01:09 +0000 (16:01 +0800)]
imx8ulp: move struct mu_type to common header
Move struct mu_type to common header to make it reusable by upower and
S400
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:01:08 +0000 (16:01 +0800)]
imx8ulp: Add workaround for eMMC boot
When booting from boot part1/2, the image offset should be 0, but
ROM has a bug to return 0x8000. Has to workaround the issue before
ROM fix it.
Use a ROM function to know boot from emmc boot part or user part
So we can set the image offset accordingly.
Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:01:07 +0000 (16:01 +0800)]
imx8ulp: Use DGO_GP5 to get boot config
Since CMC1 MR0 only reflects high 16 bits boot cfg used for AP domian,
it does not connect to low 16 bits for RTD. So we can't get the correct
boot mode.
Change to use DGO_GP5 of SEC_SIM which is set by ROM.
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:01:06 +0000 (16:01 +0800)]
imx8ulp: soc: correct reset cause
The CMC1 SRS reflects the current reset cause, not SSRS.
Then you could get "Reset cause: WARM-WDG" when issue reset in U-Boot.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:01:05 +0000 (16:01 +0800)]
driver: misc: imx8ulp: Add fuse driver for imx8ulp
This driver uses FSB to read some fuses, but not support program fuse.
It only works in SPL (secure mode), u-boot needs traps to ATF to
read them.
Some fuses can read from S400 API and others are from FSB.
Also support program some fuses via S400 API
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:01:04 +0000 (16:01 +0800)]
arm: imx8ulp: add iomuxc support
Add i.MX8ULP iomuxc support
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:01:03 +0000 (16:01 +0800)]
arm: imx8ulp: add dummy imx_get_mac_from_fuse
Add imx_get_mac_from_fuse for enet build pass
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:01:02 +0000 (16:01 +0800)]
arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domain
Configure DCNANO and MIPI_DSI to be controlled by AD for single boot
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:01:01 +0000 (16:01 +0800)]
arm: iMX8ULP: Add boot device relevant functions
Read from ROM API to get current boot device.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:01:00 +0000 (16:01 +0800)]
arm: imx8ulp: Probe the S400 MU device in arch init
Need probe the S400 MU device in arch_cpu_init_dm, so we can use
S400 API in u-boot
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:59 +0000 (16:00 +0800)]
imx8ulp: unify rdc functions
Unify rdc function to rdc.c
Update soc.c to use new rdc function
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:58 +0000 (16:00 +0800)]
arm: imx8ulp: release trdc and assign lpav from RTD to APD
Rlease LPAV from RTD to APD
Release gpu2D/3D to APD
Set TRDC MBC2 MEM1 for iomuxc0 access
Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c
and MODE pins. we have to open iomuxc0 access for A35 core (domain 7)
in single boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:57 +0000 (16:00 +0800)]
arm: imx8ulp: add trdc release request
Add TRDC release request, then we could configure resources to be
accessible by A35 Domain.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:56 +0000 (16:00 +0800)]
arm: imx8ulp: add rdc support
There is xrdc inside i.MX8ULP, we need to configure permission to make
sure AP non-secure world could access the resources.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:55 +0000 (16:00 +0800)]
arm: imx8ulp: release and configure XRDC at early phase
Since S400 will set the memory of SPL image to R/X. We can't write
to any data in SPL image.
1. Set the parameters save/restore only for u-boot, not for SPL. to
avoid write data.
2. Not use MU DM driver but directly call MU API to send release XRDC
to S400 at early phase.
3. Configure the SPL image memory of SRAM2 to writable (R/W/X)
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:54 +0000 (16:00 +0800)]
drivers: misc: s400_api: Update API for fuse read and write
Add API to support fuse read and write
Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:53 +0000 (16:00 +0800)]
drivers: misc: imx8ulp: Update S400 API for release RDC
The RDC API is updated to add a field for XRDC or TRDC
Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:52 +0000 (16:00 +0800)]
drivers: misc: imx8ulp: Add S400 API for image authentication
Add S400 API for image authentication
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:51 +0000 (16:00 +0800)]
drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6
According to latest S400 API doc, the the success indicate value is
changed to 0xd6. So update the driver codes.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:50 +0000 (16:00 +0800)]
arm: imx8ulp: Update the reset vector in u-boot
Because we have set reset vector to ATF in SPL, have to set it back
to ROM for any reset in u-boot
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:49 +0000 (16:00 +0800)]
arm: imx8ulp: disable wdog3
Disable wdog3 which is configured by ROM
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:48 +0000 (16:00 +0800)]
arm: imx8ulp: Enable full L2 cache in SPL
SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.
So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:47 +0000 (16:00 +0800)]
arm: imx8ulp: soc: Change to use CMC1 to get bootcfg
CMC1 also has a MR register for bootcfg
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:46 +0000 (16:00 +0800)]
drivers: mmc: fsl_esdhc_imx: support i.MX8ULP
i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:45 +0000 (16:00 +0800)]
arm: imx8ulp: add clock support
Add i.MX8ULP clock support
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:44 +0000 (16:00 +0800)]
driver: serial: fsl_lpuart: support i.MX8ULP
i.MX8ULP lpuart has same register layout as i.MX7ULP and i.MX8
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:43 +0000 (16:00 +0800)]
pinctrl: Add pinctrl driver for imx8ulp
Add pinctrl driver for i.MX8ULP
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:42 +0000 (16:00 +0800)]
net: fec_mxc: support i.MX8ULP
Support i.MX8ULP in fec_mxc
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Ye Li [Sat, 7 Aug 2021 08:00:41 +0000 (16:00 +0800)]
driver: misc: Add MU and S400 API to communicate with Sentinel
Add MU driver and S400 API. Need enable MISC driver to work
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:40 +0000 (16:00 +0800)]
arm: imx: move container Kconfig under mach-imx
Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig
public to both.
Signed-off-by: Peng Fan <peng.fan@nxp.com>