agx: Make partial DCE optional

Our dead code elimination pass does two things:

1. delete instructions that are entirely unnecessary
2. delete unnecessary destinations of necessary instructions

To deal with pass ordering issues, we sometimes want to do #1 without #2.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21674>

agx: Don't set lower_pack_split

We should handle nir_op_unpack_32_2x16_split_* natively, since we can generate
better code with agx_subdivide (coalescing the ops away) than the bitshift
lowering.

That said, we do need some extra instructions for the floating point
conversions.

No shader-db changes (which makes sense because we're targetting the GLES3.0
shader-db, which doesn't have the packing GLSL functions).

The real motivation of this change isn't optimizing some GLSL pack functions,
though, it's avoiding a code regression from using NIR's memory bit size
lowering in a future MR. That lowering will turn things like "load i16vec4" into
"load i32vec2 + unpack_32_2x16", so we need to be able to coalesce that unpack.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21674>

ci: Disable Collabora LAVA farm

Looks like a power or network issue.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21851>

ci: take valve farm offline

It seems to be experiencing networking issues

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21851>

ci: Actually run Piglit on LAVA

At some point in a refactoring long ago, our 'Piglit' runs on arm64
started actually being dEQP-GLES2 runs. Oh dear.

Surprisingly, there are a number of expectation changes; added every
fail I saw from a long overnight stress test.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21851>

pan/mdg: Remove reference to removed macro

This will soon be more confusing than helpful.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

panfrost: Remove MALI_POSITIVE macro

Now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

panfrost: Inline the last MALI_POSITIVE use

Big shrug on this one.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

panfrost: Remove FBD tag enum from XML

This was a hack to avoid modelling the full data structure.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

panfrost: Use framebuffer pointer XML

Rather than manipulating the raw pointers. This is cleaner.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

panfrost: Add XML for framebuffer pointers

We shouldn't have to open-code these. They are real data structures, model them
as such in the architecture XML files.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

panfrost: Handle fixed-point packing in GenXML

Minimum/maximum LOD and LOD bias are unsigned and signed fixed point formats
respectively. They are not unsigned integers. Introduce fixed-point types into
our GenXML and use them in the XML, rather than packing in sidebands. This makes
the XML more correct and fixes pretty-printing of texture and sampler
descriptors.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

panfrost: Don't use DECODE_FIXED16 for sample position

Strictly this is a signed fixed-point, anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

docs/panfrost: Move description of instancing

Connor Abbott wrote a nice explanation of how instance divisors work on Mali.
Let's add it to the driver docs instead of letting it languish in a forgotten
header file.

This is mostly pasted from the existing header in tree, with a few local changes
applied.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

panfrost: Remove some unused definitions

Nowadays, formats are defined with GenXML, not the old panfrost-job.h, so most
of the format #defines in panfrost-job.h are unused. That said, a few are still
in use as a backdoor for compressed format queries to avoid a GenXML dependency.
That's not great but cleaning that up isn't the subject of this MR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>

intel/perf: Hide extended metrics by default

XE architecture enables many more metrics, perhaps too many for
the average user. Reduce reported metrics to smaller subset,
known as non-extended metrics, by default. Can re-enable extended
metrics with env var INTEL_EXTENDED_METRICS=1

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21841>

asahi,agx: Implement buffer textures with gnarly NIR

Implement buffer textures in full generality.  There are a few issues here:

* OpenGL requires buffer textures support a minimum size of 65536 elements,
  however 1D textures in AGX are (at most) 8192 elements.

* OpenGL 4.0 (and OpenGL ES) require buffer textures to support the "RGB32"
  texture formats. These are 3 packed channels of 32-bits each. In general,
  non-power-of-two texel sizes are problematic. AGX does not support any such
  formats and we rely on the GL frontend to lower to a padded format (RGBX) if
  necessary. Such a lowering cannot work for buffer textures, however, so we
  need to find a way to implement RGB32 buffer textures.

We solve these issues in the follow way:

* Use 2D texture descriptors for buffer textures, with a large fixed
  power-of-two size along one axis. Then large texel indices may be accessed at
  a small vec2 texel coordinate, and since the fixed dimension is a
  power-of-two, that vector may be recovered by simply shifting and masking.
  This effectively avoids size restriction. We do need to clamp texel indices to
  the buffer size to avoid faulting on OOB reads, since we may read past the end
  of the buffer (if the app binds a non-page-aligned offset into the buffer).

* Use a general purpose memory load for RGB32 buffer textures. Lower the texture
  load instruction to a memory load from the buffer and some address arithmetic.
  There's no format conversion needed for RGB32, other than maybe filling in a
  format-appropriate alpha, so this is straightforward. Again, we need to clamp
  the texel index for robustness with OOB reads.

Each of these solutions brings its own problem.

* Using 2D textures instead of 1D requires physically rounding up the buffer
  size when packing the descriptor, so we can no longer implement textureSize()
  by reading off the texture descriptor like normal.

* We don't know at compile-time whether a given texture load will read from an
  RGB32 buffer texture or not, so we need to emit code for both. In Vulkan, we
  can't key the shader to this property, either, since it's descriptor set state
  and not pipeline state.

And each of these problems in turn brings its own solution:

* The texture descriptor is linear, so the "compression buffer address" field is
  ignored by the hardware. We stash the real buffer size there so that
  textureSize becomes a load from the texture descriptor like usual, without
  requiring a sideband (which would complicate bindless textures).

* If we determine a texture descriptor contains RGB32 data, then it will never
  be interpreted by the hardware and hence does not need to be a valid texture
  descriptor. So, we extend the hardware's format enum to contain a
  software-defined RGB32 format enum. Then, when lowering texture buffer loads,
  we either read it as a typed RGB32 memory load or as a texture load depending
  on the value of the format field in the texture descriptor.

All of this is accomplished with a big NIR pass generating a pile of strange
looking code. But it should be good enough in practice for this silly feature.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21672>

asahi, agx: Implement dummy samplers

In NIR, texelFetch (txf) does not use a sampler, but in AGX, it does -- even
though the contents of the sampler are semantically irrelevant. Rather than
requiring the state tracker to bind a sampler anyway (indicated for texture
buffers with PIPE_CAP_TEXTURE_BUFFER_SAMPLER), just add a dummy sampler
ourselves if txf is used and there are otherwise no samplers. This is helpful
because PIPE_CAP_TEXTURE_BUFFER_SAMPLER isn't honoured by Rusticl or seemingly
mesa/st's PBO code, and after implementing this dummy sampler workaround in
Panfrost for Rusticl, I realized this CAP is silly and shouldn't exist in the
first place. (And I regret pushing for its reinclusion.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21672>

ci/baremetal: Wrap artifact download curl with xtrace

Setting `set -x`can be useful to known via trace which URL baremetal
used to download artifacts.
Today its only printed the command with the environment variables.

Also, this commit fixes multiple `section_end` for the related Gitlab
sections.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21804>

ci: Fix release build use for performance jobs

This commit ensures that we are using mesa release builds in performance
jobs.

To achieve that, some modifications were made on top of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21492.

- Append the `BUILDTYPE` variable into the S3 artifact name
  (MINIO_ARTIFACT_NAME environment variable) to allow for better
  artifact management.

- The ./artifacts directory has been added to the list of artifact
  directories for build-common. This ensures that the debian-release and
  debian-arm64-release jobs are the only ones necessary for running
  performance jobs. These jobs only produce artifacts via
  prepare-artifacts.sh when we are under performance workflow.

- Make lava-submit.sh behave similar to baremetal jobs regarding
  MINIO_ARTIFACT_NAME variable. For example, users can now easily
  differentiate between mesa-arm64.tar.zstd and
  mesa-arm64-release.tar.zstd by looking inside the `Downloading
  artifacts from s3` Gitlab section.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21804>

iris: Move i915 submit_batch() to i915 backend

No changes in behavior intented here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21700>

iris: Add batch_check_for_reset() to kmd backend

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21700>

iris: Add gem_mmap() to kmd backend

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21700>

build: Block build of HASVK, Crocus and i915 in non-x86 architectures

HASVK, Crocus and i915 drivers only supports integrated GPUs.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21773>

intel/perf: Disable it for Xe KMD

Xe still don't have support for performance metrics.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21773>

iris: Don't mark protected bo as reusable

The check in alloc_bo_from_cache() was skiping any try to get a bo
from cache but after use a protected bo was still being put in some
cache bucket and could be used for cases that don't require a
protected bo.

Using a protected bo in cases that don't require it can have
performance implications.

So here returning NULL when trying to get a cache bucket for a
protected bo, this will cause bo->real.reusable to be set to false
avoiding the bo to be reused.

Fixes: 9402ac8023a0 ("iris: handle protected BO creation")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21824>

asahi: Don't allow linear depth/stencil buffers

We don't have a way to tell the ZLS hardware to use linear buffers, so if a
buffer could be used for depth/stencil, we have to twiddle. This isn't a problem
in practice, since depth/stencil buffers can't be shared across processes or
mapped directly as linear.

Fixes faults in depthstencil-render-miplevels, which was picking linear for one
buffer because of a STAGING bind flag. But that won't work :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21753>

ci/android: Use a more aggressive timeout for the job

This job sometimes - very, very, rarely - fails to start Cuttlefish,
the Android VM environment. Given that we don't have any structural
monitoring and restarting (unlike LAVA/BM/B2C) for this, just stick a
more aggressive timeout on the job, so it'll be retried if it fails to
start.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21837>

nir/lower_int64: Optionally lower ufind_msb using uadd_sat

v2: Fix inverted condition for applying the optimization. Noticed by
Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

nir/algebraic: Optimize some ifind_msb to ufind_msb

On Intel platforms, the uclz lowering if ufind_msb is either one
instruction better (Gfx7 and newer) or two instructions better (all
older platforms) than the ifind_msb implementations.

On platforms that use lower_find_msb_to_reverse, there should be no
difference.

All Haswell and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19938662 -> 19938634 (<.01%)
instructions in affected programs: 850 -> 822 (-3.29%)
helped: 2 / HURT: 0

total cycles in shared programs: 858467067 -> 858465538 (<.01%)
cycles in affected programs: 10080 -> 8551 (-15.17%)
helped: 2 / HURT: 0

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

nir: Restrict ufind_msb and ufind_msb_rev to 32- or 64-bit sources

4d802df3aac353970aae93699223fb15b24f8408 loosened the type restrictions
on these opcodes to enable support for 64-bit ballot operations.  In
doing so, it enabled 8-bit and 16-bit sizes as well.

It's impossible to get these sizes through GLSL or SPIR-V.  None of the
lowering in nir_opt_algebraic can handle non-32-bit sizes.  Almost no
drivers can handle non-32-bit sizes.

It doesn't seem possible to enforce anything other than "one bit size"
or "all bit sizes" in nir_opcodes.py.  The only way it seems possible to
enforce this is in nir_validate.  This is not ideal, but it be what it
be.

v2: Remove restriction on find_lsb. It is acutally possible to get this
via GLSL by doing findLSB() on a lowp value. findMSB declares its
parameter as highp, so that path is still impossible.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

nir/algebraic: Do not generate 8- or 16-bit find_msb

The next commit will add validation to restrict this instruction (and
others) to only 32-bit or 64-bit sources.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

nir/builder: Do not generate 8- or 16-bit find_msb

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

nir: intel/compiler: Move ufind_msb lowering to NIR

Fossil-db results:

All Intel platforms had similar results. (Ice Lake shown)
Cycles in all programs: 9098346105 -> 9098333765 (-0.0%)
Cycles helped: 6

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

nir/algebraic: Only lower ufind_msb with 32-bit sources

The 31-ufind_msb_rev(x) lowering only produces the correct result for
32-bit sources. ufind_msb_rev can also have 64-bit sources, and most
platforms are expected to lower this to 32-bit instructions with extra
logic operations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

intel/compiler: Tighter src and dest size bounds checking for some opcodes

Enforce the sizes listed in the Skylake PRM:

BFREV:
    source types: *D
    destination types: *D

CBIT:
    source types: UB, UW, UD
    destination types: UD

FBH:
    source types: D, UD
    destination types: UD

FBL:
    source types: UD
    destination types: UD

LZD:
    source types: D, UD
    destination types: UD

v2: Update BFREV commit message documentation. Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

nir: intel/compiler: Move ifind_msb lowering to NIR

Unlike ufind_msb, ifind_msb is only defined in NIR for 32-bit values, so
no @32 annotation is required.

No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

intel/compiler: Lower find_lsb in NIR

No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

nir: ifind_msb_rev can only have int32 sources

Just like ifind_msb.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>

zink: fix stipple pattern in oblique lines

Stipple lines now appear correctly when they are oblique.

Previously the number of steps of the stipple counter between two vertices
was calculated as the euclidian distance between them in screen space, however
the length occupied by pixel along a line is only `1` for lines that are either
vertical or horizontal and will be anywhere between `1` and `sqrt(2)`
for other cases.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21290>

agx: Handle indirect texture/samplers

Get the texture/sampler index from the texture/sampler_offset source (which
is an offset from 0 thanks to the lower_index_to_offset lowering) and feed it in
as corresponding 16-bit texture instruction sources.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21704>

agx: Pack indirect texture/sampler handles

For indirect indexing into the binding table. Note this does not handle packing
the bindless forms, since that's a bit more involved.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21704>

docs/zink: fixup wording of the GL 4.6 requirements

Seems the copy-pasta was strong in this one. Whoops!

Fixes: 5deac5c1565 ("docs: document zink GL 4.6 requirements")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21813>

docs/zink: remove some trailing spaces

These went unnoticed until now, let's fix them.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21813>

docs/zink: use vk-feat role for features

This gives us links to the features, instead of just mentioning them.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21813>

docs: implement new vk-feat role

This makes it easy to link to a specific Vulkan feature from the docs.
Useful for the Zink docs.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21813>

symbols-check: support OSes based on GNU toolchain

Some of the symbols listed in PLATFORM_SYMBOLS are not only specific
to Linux, but rather specific to the GNU toolchain. Hence, use them
when inspecting ELF binaries produced by a GNU toolchain: this means
on Hurd ('GNU'), and on e.g. kFreeBSD ('GNU/kFreeBSD').

Signed-off-by: Pino Toscano <toscano.pino@tiscali.it>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21825>

Revert "Revert "ci: disable mesa-swrast runner jobs""

This reverts commit 7ae0d9d2e8a9f0993b056a332e6182e5c655be73.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21836>

v3dv: split out broadcom_shader_stage_to_gl() calls to improve readability

This is an inline function with a compile-constant switch, so I expect
the compiler wouldn't produce any better code like this, but for humans
it's easier to read when function calls are not embedded into other
function calls.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21835>

meson: inline gtest_test_protocol now that it's always 'gtest'

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21485>

meson: allow feature options to take true/false to mean enabled/disabled

This reduces the pain of Meson having picked inconsistent value names.

See also https://github.com/mesonbuild/meson/pull/11279 where Meson devs
argue that allowing `foo=false` could be interpreted by users to mean
either `disabled` or `auto`, which I personally don't see.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21485>

meson: bump minimum version to 0.60

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21485>

intel/compiler: Add swsb_stall debug option

When enabled, on gfx12 plus, we will add the sync nop instruction after
each instruction to make sure that current instruction depends on the
previous instruction explicitly.

This option will help us to get a hint if something is missing or broken
in software scoreboard pass.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21797>

agx: Fix clang-formatting

Not sure how this one slipped in.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21828>

Revert "ci: disable mesa-swrast runner jobs"

This reverts commit aef0f3efdfbcaaea78f2eb2315b064d92117abae.

We've got a new set of runners now (mesa-swrast-4, 5, and 7 because
counting is hard)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21826>

iris: trace frames with u_trace

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21648>

docs: fix invalid link

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21648>

intel/eu: Simplify brw_F32TO16 and brw_F16TO32

Now that we aren't using them on Gfx8+ we can drop a lot of cruft.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>

intel/fs: Move packHalf2x16 handling to lower_pack()

This mainly lets the software scoreboarding pass correctly mark the
instructions, without needing to resort to fragile manual handling in
the generator.

We can also make small improvements.  On Gfx 8LP-12.0, we no longer have
the restrictions about DWord alignment, so we can simply write each half
into its intended location, rather than writing it to the low DWord and
then shifting it in place.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>

intel/fs: Use F32TO16/F16TO32 helpers in fquantize16 handling

I originally thought that we were intentionally emitting the legacy
opcodes here to make them opaque to the optimizer, so that it wouldn't
eliminate the explicit type conversions, as they're actually required
to do the quantization.  But...we don't actually optimize those away
currently anyway.  So...go ahead and use the helpers for consistency.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>

Revert "intel/fs: Fix inferred_sync_pipe for F16TO32 opcodes"

With the previous patch, we no longer need to special case this, as we
emit a MOV with an HF source, rather than F16TO32 with an UW source,
on all platforms that need scoreboarding.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>

intel/fs: Use new F16TO32 helpers for unpack_half_split_* opcodes

This gets us a MOV at the IR level on Gfx8+ which should be more
optimizable than F16TO32.  It also removes confusion about which
pipe which the instruction will run on.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>

intel/fs: Delete a TODO about using brw_F32TO16.

We can just use the new builder helpers to get the optimization
advantages of a MOV on Gfx8+ while also getting the necessary F32TO16
on Gfx7.x and yet not worry too hard about it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>

intel/fs: Add builder helpers for F32TO16/F16TO32 that work on Gfx7.x

These take care of emitting the F32TO16/F16TO32 instructions on Gfx7.x
but otherwise just emit a type converting MOV on Gfx8+.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>

intel/fs: Fix inferred_sync_pipe for F16TO32 opcodes

For converting half-float to float, we currently emit BRW_OPCODE_F16TO32
with a UW source, to match legacy Gfx7 behavior.  In the generator, this
becomes a MOV with a HF source on Gfx8+.  Unfortunately, this UW source
confuses the scoreboarding pass into thinking it's an integer source,
leading to incorrect SWSB annotations on Alchemist.

We should ultimately fix the IR to stop being so...legacy...here, but
this is the simplest fix for stable branches.

Fixes misrendering in Elden Ring and likely Sekiro: Shadows Die Twice.

Cc: mesa-stable
Tested-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8018
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8375
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>

intel: use generated workaround helpers for Wa_1409600907

Wa_1409600907 was enabled for gen12+.  It should not be applied for
platforms after gen12.0.  Use generated helpers to ensure application
to all relevant platforms.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21743>

radv: set RADEON_FLAG_GTT_WC for external mem on vram

We used to set RADEON_FLAG_GTT_WC when wsi_info is set.  This changes it
to set the flag for any external mem on vram, extending the logic for
apps using external memory directly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21803>

ci/weston: add background PID

Needed for process tracking for LAVA.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21711>

ci/weston: before testing, verify that XWayland is really running

When Xorg already running, Weston XWayland should pick DISPLAY=:1

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21711>

ci/lava: implement the priority

Before: kernelci 38; Mesa3D 75

Priority now:
 - 38 ‒ kernelci
 - 40 ‒ after merge and performance
 - 50 ‒ user runs
 - 75 ‒ marge-bot (MUST be prioritized)

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21812>

ci/radv: Lower stoney CTS load

CTS runs on stoney are currently taking ~20min to complete, which seems
to have begun with the upgrade to CTS 1.3.5.0. This is a bit too long in
and of itself, but it means that - assuming zero contention - a job that
has to be retried because the machine hung can take 40 minutes.

Aim to drop this to 15min turnaround by lowering the overall fraction
from 1/8th of the CTS to 1/11th.

As the jobs we run have been reshuffled, this adds a lot more expected
fails. As most of them categorise easily into patterns, group the
failures together in the file. Non-strict wide lines has passed since we
last ran it; the other failures all group into existing classes seen
for a long time.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21791>

ci/zink: Add flake seen in the wild

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21820>

ci: disable mesa-swrast runner jobs

Temporarily.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21815>

ci/fdno: Add a618 Vulkan flakes

It looks like descriptors are generically a bit broken, which takes out
a massive number of tests periodically.

The pipeline-library tests also have some unknowable issues.

cf. #8219

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21740>

aco: use bitfield_array for temporary neg/abs/opsel

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21766>

aco: access neg/abs as int in usesModifiers

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21766>

aco: use array indexing for opsel/opsel_lo/opsel_hi

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21766>

aco: use integer access for neg_lo/neg_hi

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21766>

aco: copy abs/neg with assignment

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21766>

intel/isl: disable TILE64 for YCRCB formats

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21723>

ci/radv: Drop raven quick_shader load

It currently takes ~21 minutes to complete. That's not quick.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21793>

v3dv/ci: add a test to the known failures

New test since the 1.3.5 update, and running it on older mesa it would
have always failed, so it's not a regression
-> let's just mark it as a known failure

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21792>

zink: Pass the cmdbuf to the end of the marker, too.

Otherwise the end wanders off to some unrelated cmdbuf.

Fixes: 271ebdd735e4 ("zink: pass cmdbuf to debug marker begin")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21799>

ci/zink: fixup the zink-lvp job

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8501
Fixes: 4cc0cec47357 ("ci: implement unified sections")

Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21796>

drirc: set `zink_emulate_point_smooth` for Quake II

Quake II uses GL_POINT_SMOOTH to render particles.
Zink currently requires `zink_emulate_point_smooth` to support that feature.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21731>

zink: handle point_smooth emulation

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21731>

nir: handle output beeing written to deref in `nir_lower_point_smooth`

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21731>

zink/nir_to_spirv: add support for `nir_intrinsic_load_point_coord`

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21731>

zink: add `lower_point_smooth` to `zink_fs_key`

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21731>

zink: add `zink_emulate_point_smooth` driconf

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21731>

zink: fix line smooth lowering

Fixes: 80285db9efe1 ("zink: lower smooth-lines if not supported")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21731>

docs: update calendar for 22.3.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21795>

docs/relnotes: add sha256sum for 22.3.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21795>

docs: add release notes for 22.3.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21795>

docs/relnotes: add 23.0.0 to relnotes.rst

I used an old version of the script to generate the notes, which didn't
generate this. It is being kept separate instead of being squashed so
that the commits on the 23.0 branch and those on main match

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21500>

docs: Add sha256 sum for 23.0.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21500>

docs: add release notes for 23.0.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21500>

docs: Add calendar entries for 23.0 release.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21500>

osmesa: add exported symbols check

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1308>

anv+hasvk: Use driconf to disable 16-bit for zink.

The HW can technically execute 16-bit operations, but the restrictions on
16-bit ALU ops are so great that it ends up not being a win for
GLES-on-Vulkan to lower mediump to 16-bit operations, at least with the
current state of the Intel compiler.  This brings zink-on-anv in line with
iris and angle-on-anv for mediump behavior (ANGLE uses RelaxedPrecision,
which we ignore).

Perf on some angle traces on my brya (ADL) and i9-9900K (CFL):

ADL zink pubg_mobile_battle_royale:  +13.4574% +/- 5.2046% (n=5)
CFL zink pubg_mobile_battle_royale:  +29.5332% +/- 0.646585% (n=6)
ADL zink aztec_ruins_high:           +5.78027% +/- 4.80645% (n=4)
CFL zink aztec_ruins_high:           -1.10641% +/- 0.140562% (n=12)
ADL zink trex_200:                   +5.86956% +/- 2.09633% (n=10)
CFL zink trex_200:                   +9.72136% +/- 0.749261% (n=10)

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21775>