Samuel Pitoiset [Fri, 1 Feb 2019 14:30:31 +0000 (15:30 +0100)]
radv: fix build
Fixes:
9b9ccee4d64 ("radv: take LDS into account for compute shader occupancy stats")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 1 Feb 2019 11:04:39 +0000 (22:04 +1100)]
radv: take LDS into account for compute shader occupancy stats
Ported from
d205faeb6c96.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Timothy Arceri [Fri, 1 Feb 2019 10:16:54 +0000 (21:16 +1100)]
ac/radv/radeonsi: add ac_get_num_physical_sgprs() helper
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Gurchetan Singh [Thu, 31 Jan 2019 16:47:47 +0000 (08:47 -0800)]
docs: add GL_EXT_texture_compression_s3tc_srgb to release notes
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Gurchetan Singh [Wed, 30 Jan 2019 18:48:19 +0000 (10:48 -0800)]
st/mesa: expose EXT_texture_compression_s3tc_srgb
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Gurchetan Singh [Wed, 30 Jan 2019 18:26:50 +0000 (10:26 -0800)]
i965: Set flag for EXT_texture_compression_s3tc_srgb
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Gurchetan Singh [Wed, 30 Jan 2019 02:46:11 +0000 (18:46 -0800)]
mesa/main: Expose EXT_texture_compression_s3tc_srgb
Required for the following test:
bin/compressedteximage GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT
pass when emulating GL on GLES.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Timothy Arceri [Thu, 31 Jan 2019 04:59:18 +0000 (15:59 +1100)]
st/glsl_to_nir: remove dead local variables
Without this we do not end up with a deterministic NIR because
temporary register variables are added in random order. NIR must
be deterministic because we use it to produce a sha for the
radeonsi backends disk cache.
This fixes the shader cache for a bunch of shaders.
Another positive is that this results in a large reduction in the
size of the NIR that the state tracker stores to the disk cache.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dylan Baker [Tue, 29 Jan 2019 19:25:30 +0000 (11:25 -0800)]
meson: remove -std=c++11 from intel/tools
for meson all C++ code is already compiled as C++11, so it's
unnecessary. It's also the wrong way to do this, if we really needed
this the correct way is to set:
```meson
executable(
...
override_options : ['cpp_std=c++11'],
)
```
Which ensures not only that the correct syntax for the current
compiler is used, but also that meson doesn't create arguments like
`-std=c++14 ... -std=c++11`
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Tue, 29 Jan 2019 19:24:14 +0000 (11:24 -0800)]
meson: fix style in intel/tools
The `:` in options should always have one space before and after `foo
: bar`, and lists do not get spaces around the braces: `[foo]` not `[
foo ]`
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Tue, 29 Jan 2019 19:22:53 +0000 (11:22 -0800)]
meson: remove build_by_default : true
Which is and has always been the default. This is largely an artifact
of how the building of these tools was controlled when the meson build
was originally created.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Emil Velikov [Thu, 31 Jan 2019 21:17:38 +0000 (21:17 +0000)]
docs: update calendar, add news item and link release notes for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 31 Jan 2019 21:08:36 +0000 (21:08 +0000)]
docs: add sha256 checksums for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
7475d7727f172387ac3d069887f3095dcb884649)
Emil Velikov [Thu, 31 Jan 2019 20:58:09 +0000 (20:58 +0000)]
docs: add release notes for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
190a79f462710f04d67eaefe498ef6ae5b7f5b1a)
[Emil: drop VERSION hunk]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
VERSION
Neha Bhende [Tue, 29 Jan 2019 19:21:00 +0000 (12:21 -0700)]
st/mesa: Fix topogun-1.06-orc-84k-resize.trace crash
We need to initialize all fields in rs->prim explicitly while
creating new rastpos stage.
Fixes:
bac8534267 ("st/mesa: allow glDrawElements to work with GL_SELECT
feedback")
v2: Initializing all fields in rs->prim as per Ilia.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dylan Baker [Wed, 30 Jan 2019 18:02:41 +0000 (10:02 -0800)]
android,autotools,i965: Fix location of float64_glsl.h
Android.mk and autotools disagree about where generated files should
go, which wasn't a problem until we wanted to build a dist
tarball. This corrects the problem by changing the output and include
paths to be the same on android and autotools (meson already has the
correct include path).
Fixes:
7d7b30835cfb9eb89beca9fb8593d0954f79b84d
("automake: Fix path to generated source")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Marek Olšák [Wed, 30 Jan 2019 19:20:03 +0000 (14:20 -0500)]
gallium: allow more PIPE_RESOURCE_ driver flags
radeonsi has 8 and will probably have 9 soon.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Eric Anholt [Wed, 30 Jan 2019 19:17:35 +0000 (11:17 -0800)]
v3d: Fix image_load_store clamping of signed integer stores.
This was copy-and-paste fail, that oddly showed up in the CTS's
reinterprets of r32f, rgba8, and srgba8 to rgba8i, but not r32ui and r32i
to rgba8i or reinterprets to other signed int formats.
Fixes:
6281f26f064a ("v3d: Add support for shader_image_load_store.")
Eric Anholt [Wed, 30 Jan 2019 17:33:53 +0000 (09:33 -0800)]
mesa: Skip partial InvalidateFramebuffer of packed depth/stencil.
One of the CTS cases tries to invalidate just stencil of packed
depth/stencil, and we incorrectly lost the depth contents.
Fixes dEQP-GLES3.functional.fbo.invalidate.whole.unbind_read_stencil
Fixes:
0c42b5f3cb90 ("mesa: wire up InvalidateFramebuffer")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Thu, 31 Jan 2019 14:56:19 +0000 (09:56 -0500)]
freedreno: more fixing release tarball
Fixes:
aa0fed10d35 freedreno: move ir3 to common location
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 31 Jan 2019 13:03:43 +0000 (08:03 -0500)]
freedreno: fix release tarball
Fixes:
b4476138d5a freedreno: move drm to common location
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Emmanuel Gil Peyrot [Sun, 27 Jan 2019 20:46:56 +0000 (21:46 +0100)]
docs: make bugs.html easier to find
Thanks to Yann Kervran for the report and suggestions.
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Dave Airlie [Mon, 21 May 2018 23:32:42 +0000 (09:32 +1000)]
virgl: ARB_query_buffer_object support
v1.1: fix size define.
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Dave Airlie [Tue, 8 Jan 2019 06:50:28 +0000 (16:50 +1000)]
virgl: enable elapsed time queries
GL underneath always has GL_TIME_ELAPSED so always enable these.
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Dylan Baker [Wed, 30 Jan 2019 17:44:24 +0000 (09:44 -0800)]
automake: Add --enable-autotools to distcheck flags
Fixes:
e68777c87ceed02ab199b32f941778c3cf97c794
("autotools: Deprecate the use of autotools")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Marek Olšák [Wed, 30 Jan 2019 19:31:48 +0000 (14:31 -0500)]
radeonsi: fix a comment typo in si_fine_fence_set
Marek Olšák [Wed, 30 Jan 2019 17:49:30 +0000 (12:49 -0500)]
r600: add -Wstrict-overflow=0 to meson to silence the warning
same as radeonsi
Marek Olšák [Mon, 28 Jan 2019 21:55:11 +0000 (16:55 -0500)]
winsys/amdgpu: remove amdgpu_drm.h definitions
trivial
Marek Olšák [Sat, 5 Jan 2019 00:30:48 +0000 (19:30 -0500)]
radeonsi: unify error paths in si_texture_create_object
Marek Olšák [Tue, 8 Jan 2019 16:51:22 +0000 (11:51 -0500)]
radeonsi: merge & rename texture BO metadata functions
Marek Olšák [Tue, 15 Jan 2019 02:21:28 +0000 (21:21 -0500)]
radeonsi: enable dithered alpha-to-coverage for better quality
same as AMDVLK.
GL_NV_alpha_to_coverage_dither_control allows controlling this behavior.
The default is implementation-dependent.
Dylan Baker [Mon, 28 Jan 2019 18:50:31 +0000 (10:50 -0800)]
gallium: wrap u_screen in extern "C" for c++
Some drivers (notabily SWR) are written in C++, and as such they need
access to C headers with extern "C". So lets add that.
Gert Wollny [Thu, 24 Jan 2019 11:38:05 +0000 (12:38 +0100)]
mesa/core: Enable EXT_texture_sRGB_R8 also for desktop GL
As of Nov/30/2018 the extension is also valid for OpenGL >= 1.2, so
enable it accordingly and also add the required view class entry.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Wed, 30 Jan 2019 11:07:29 +0000 (12:07 +0100)]
radv/winsys: fix hash when adding internal buffers
This fixes serious stuttering in Shadow Of The Tomb Raider.
Fixes:
50fd253bd6e ("radv/winsys: Add priority handling during submit.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Erik Faye-Lund [Thu, 1 Nov 2018 12:28:25 +0000 (13:28 +0100)]
mesa: expose NV_conditional_render on GLES
The extension spec has been updated to include GLES 2 support, so let's
enable it there.
v2: fixup ABI-check as well
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Ernestas Kulik [Thu, 30 Aug 2018 16:02:46 +0000 (19:02 +0300)]
v3d: Fix leak in resource setup error path
Reported by Coverity: in the case of unsupported modifier request, the
code does not jump to the “fail” label to destroy the acquired resource.
CID: 1435704
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes:
45bb8f295710 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.")
Ernestas Kulik [Thu, 30 Aug 2018 16:02:47 +0000 (19:02 +0300)]
vc4: Fix leak in HW queries error path
Reported by Coverity: in the case where there exist hardware and
non-hardware queries, the code does not jump to err_free_query and leaks
the query.
CID: 1430194
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes:
9ea90ffb98fb ("broadcom/vc4: Add support for HW perfmon")
Eric Anholt [Wed, 30 Jan 2019 00:02:51 +0000 (16:02 -0800)]
v3d: Fix a release build set-but-unused compiler warning.
Eric Anholt [Tue, 29 Jan 2019 01:12:48 +0000 (17:12 -0800)]
v3d: Always enable the NEON utile load/store code.
I can't imagine the new HW block being paired with a v6 CPU, so don't
bother with the CPU detection that vc4 had to do.
Improves 1024x1024 TexImage on my 7278 by 47.3229% +/- 0.679632%
Emil Velikov [Tue, 29 Jan 2019 17:25:17 +0000 (17:25 +0000)]
vc4: Declare the last cpu pointer as being modified in NEON asm.
Earlier commit addressed 7 of the 8 instances available.
v2: Rebase patch back to master (by anholt)
Cc: Carsten Haitzler (Rasterman) <raster@rasterman.com>
Cc: Eric Anholt <eric@anholt.net>
Fixes:
300d3ae8b14 ("vc4: Declare the cpu pointers as being modified in NEON asm.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Tue, 29 Jan 2019 23:32:16 +0000 (15:32 -0800)]
docs: Add relnotes stub for 19.1
Dylan Baker [Tue, 29 Jan 2019 23:30:25 +0000 (15:30 -0800)]
bump version for 19.0 branch
Dylan Baker [Tue, 29 Jan 2019 22:25:46 +0000 (14:25 -0800)]
automake: Add include dir for nir src directory
Fixes:
6281f26f064ada36b57d45feb68d8e7d783198c9
("v3d: Add support for shader_image_load_store.")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Dylan Baker [Tue, 29 Jan 2019 22:19:00 +0000 (14:19 -0800)]
automake: Add float64.glsl to dist tarball
Fixes:
b63a1f8e40b6705d6a1d806fbd38dcd197d4229b
("glsl: Create file to contain software fp64 functions")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Dylan Baker [Tue, 29 Jan 2019 17:52:39 +0000 (09:52 -0800)]
automake: Fix path to generated source
Fixes:
b63a1f8e40b6705d6a1d806fbd38dcd197d4229b
("glsl: Create file to contain software fp64 functions")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Sun, 27 Jan 2019 20:38:19 +0000 (12:38 -0800)]
nir: Optimize double-precision lower_round_even()
Use the trick of adding and then subtracting 2**52 (52 is the number of
explicit mantissa bits a double-precision floating-point value has) to
implement round-to-even.
Cuts the number of instructions on SKL of the piglit test
fs-roundEven-double.shader_test from 109 to 21.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Mon, 28 Jan 2019 15:56:11 +0000 (10:56 -0500)]
ac: use the correct LLVM processor name on Raven2
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Eric Anholt [Tue, 29 Jan 2019 22:00:27 +0000 (14:00 -0800)]
v3d: Fix the autotools build.
Noticed while looking at the gitlab-CI MR.
Jonathan Marek [Wed, 23 Jan 2019 20:07:31 +0000 (15:07 -0500)]
freedreno: fix sysmem rendering being used when clear is used
This batch->cleared value is only used to decide to use sysmem rendering
or not, so it should include any buffers that are affected by a clear.
This is required because the a2xx fast clear doesn't work with sysmem
rendering. The a22x "normal" clear path doesn't work with sysmem either.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Jonathan Marek [Mon, 21 Jan 2019 16:04:47 +0000 (11:04 -0500)]
freedreno: fix depth usage logic
Depth can be used even when there is no restore/resolve of depth. This
happens when the depth buffer is invalidated after rendering to avoid
the resolve operation.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Jonathan Marek [Mon, 21 Jan 2019 16:32:30 +0000 (11:32 -0500)]
freedreno: fix invalidate logic
Set dirty bits on invalidate to trigger invalidate logic in fd_draw_vbo.
Also, resource_written for color needs to be after the invalidate logic.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Jonathan Marek [Mon, 21 Jan 2019 16:29:59 +0000 (11:29 -0500)]
mesa/st: wire up DiscardFramebuffer
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Thu, 1 Nov 2018 15:10:46 +0000 (11:10 -0400)]
mesa: wire up InvalidateFramebuffer
And before someone actually starts implementing DiscardFramebuffer()
lets rework the interface to something that is actually usable.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Jonathan Marek [Mon, 21 Jan 2019 16:02:11 +0000 (11:02 -0500)]
st/dri: invalidate_resource depth/stencil before flush_resource
This allows freedreno to be aware of the depth invalidate when flushing
batches on flush_resource.
AFAIK, the only other driver which might care about this change is vc4,
where I think it should help by allowing the depth invalidate to work with
GALLIUM_HUD.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Mario Kleiner [Wed, 13 Jun 2018 04:04:15 +0000 (06:04 +0200)]
egl/wayland-drm: Only announce formats via wl_drm which the driver supports.
Check if a pixel format is supported by the Wayland servers gpu driver
before exposing it to the client via wl_drm, so we avoid reporting formats
to the client which the server gpu can't handle.
Restrict this reporting to the new color depth 30 formats for now, as the
ARGB/XRGB8888 and RGB565 formats are probably supported by every gpu under
the sun.
Atm. this is mostly useful to allow proper PRIME renderoffload for depth
30 formats on the typical Intel iGPU + NVidia dGPU "NVidia Optimus" laptop
combo.
Tested on Intel, AMD, NVidia with single-gpu setup and on a Intel + NVidia
Optimus setup.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Mario Kleiner [Wed, 13 Jun 2018 04:04:14 +0000 (06:04 +0200)]
egl/wayland: Allow client->server format conversion for PRIME offload. (v2)
Support PRIME render offload between a Wayland server gpu and a Wayland
client gpu with different channel ordering for their color formats,
e.g., between Intel drivers which currently only support ARGB2101010
and XRGB2101010 import/display and nouveau which only supports ABGR2101010
rendering and display on nv-50 and later.
In the wl_visuals table, we also store for each format an alternate
sibling format which stores colors at the same precision, but with
different channel ordering, e.g., ARGB2101010 <-> ABGR2101010.
If a given client-gpu renderable format is not supported by the server
for import, but the alternate format is supported by the server, expose
the client-gpu renderable format as a valid EGLConfig to the client. At
eglSwapBuffers time, during the blitImage() detiling blit from the client
backbuffer to the linear buffer, the client format is converted to the
server supported format. As we have to do a copy for PRIME anyway,
this channel swizzling conversion comes essentially for free.
Note that even if a server gpu in principle does support sampling
from the clients native format, this conversion will be a performance
advantage if it allows to convert to the servers preferred format
for direct scanout, as the Wayland compositor may then be able to
directly page-flip a fullscreen client wl_buffer onto the primary
plane, or onto a hardware overlay plane, avoiding an extra data copy
for desktop composition.
Tested so far under Weston with: nouveau single-gpu, Intel single-gpu,
AMD single-gpu, "Optimus" Intel server iGPU for display + NVidia
client dGPU for rendering.
v2: Implement minor review comments by Eric Engestrom: Add some
comment and assert, and some style fixes for clarity.
No functional change.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Jason Ekstrand [Fri, 16 Nov 2018 16:46:27 +0000 (10:46 -0600)]
intel/fs: Use split sends for surface writes on gen9+
Surface reads don't need them because they just have the one address
payload. With surface writes, on the other hand, we can put the address
and the data in the different halves and avoid building the payload all
together.
The decrease in register pressure and added freedom in register
allocation resulting from this change reduces spilling enough to improve
the performance of one customer benchmark by about 2x.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Tue, 29 Jan 2019 05:24:24 +0000 (23:24 -0600)]
intel/fs: Add interference between SENDS sources
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 16 Nov 2018 03:05:08 +0000 (21:05 -0600)]
intel/fs: Support SENDS in SHADER_OPCODE_SEND
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 16 Nov 2018 21:17:25 +0000 (15:17 -0600)]
intel/disasm: Properly disassemble split sends
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Thu, 15 Nov 2018 21:17:06 +0000 (15:17 -0600)]
intel/eu: Add support for the SENDS[C] messages
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Thu, 15 Nov 2018 23:40:32 +0000 (17:40 -0600)]
intel/inst: Indent some code
We're about to add some more if cases so let's have the giant re-indent
in it's own patch to make review easier.
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 16 Nov 2018 19:03:31 +0000 (13:03 -0600)]
intel/inst: Fix the ia16_addr_imm helpers
These have clearly never seen any use.... On gen8, the bottom 4 bits are
missing so we need to shift them off before we call set_bits and shift
again when we get the bits. Found by inspection.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 16 Nov 2018 20:49:25 +0000 (14:49 -0600)]
intel/disasm: Rework SEND decoding to use descriptors
Instead of fetching the information out of the instruction directly,
fetch the descriptor and then pluck the information out of the
descriptor. The current scheme works ok for SEND but with SENDS, it all
falls to pieces because the descriptor is completely shuffled around.
This commit doesn't actually convert everything. One notable exception
is URB messages which don't even use descriptors in emit_urb_WRITE yet.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Sat, 17 Nov 2018 00:45:46 +0000 (18:45 -0600)]
intel/eu: Add more message descriptor helpers
We want to be able to extract data from descriptors as well as unify a
bit of the descriptor construction.
One of the unifications we do is to unify the read/write and dataport
descriptors. On gen4-5, read/write are substantially different and the
read descriptors change between gen4 and gen4.x. On gen6, they unified
layouts between read, write, and dataport. Then, on gen8, they added
one bit to the message type field but left it reserved MBZ for
read/write messages. This commit chooses to treat that as if they
expanded the field everywhere and just didn't have enough enum values
for read/write to bother with the extra bit.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 16 Nov 2018 22:25:12 +0000 (16:25 -0600)]
intel/eu/validate: SEND restrictions also apply to SENDC
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Thu, 15 Nov 2018 21:05:57 +0000 (15:05 -0600)]
intel/eu: Use GET_BITS in brw_inst_set_send_ex_desc
It's a bit more readable
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Thu, 1 Nov 2018 21:04:01 +0000 (16:04 -0500)]
intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Tue, 30 Oct 2018 20:47:39 +0000 (15:47 -0500)]
intel/fs: Use SHADER_OPCODE_SEND for texturing on gen7+
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Wed, 31 Oct 2018 14:52:33 +0000 (09:52 -0500)]
intel/fs: Use a logical opcode for IMAGE_SIZE
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Tue, 30 Oct 2018 17:23:44 +0000 (12:23 -0500)]
intel/fs: Use SHADER_OPCODE_SEND for surface messages
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Mon, 29 Oct 2018 20:06:14 +0000 (15:06 -0500)]
intel/fs: Add a generic SEND opcode
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Mon, 29 Oct 2018 21:09:30 +0000 (16:09 -0500)]
intel/eu: Rework surface descriptor helpers
This commit pulls the surface descriptor helpers out into brw_eu.h and
makes them no longer depend on the codegen infrastructure. This should
allow us to use them directly from the IR code instead of the generator.
This change is unfortunately less mechanical than perhaps one would like
but it should be fairly straightforward.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Thu, 1 Nov 2018 19:15:58 +0000 (14:15 -0500)]
intel/eu: Add has_simd4x2 bools to surface_write functions
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Thu, 1 Nov 2018 18:40:31 +0000 (13:40 -0500)]
intel/fs: Take an explicit exec size in brw_surface_payload_size()
Instead of magically falling back to SIMD8 for atomics and typed
messages on Ivy Bridge, explicitly figure out the exec size and pass
that into brw_surface_payload_size.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Wed, 31 Oct 2018 15:18:21 +0000 (10:18 -0500)]
intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()
Like all the other sends, it's just mlen * REG_SIZE.
Fixes:
3cbc02e4693 "intel: Use TXS for image_size when we have..."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Mon, 29 Oct 2018 22:17:43 +0000 (17:17 -0500)]
intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITS
If you pass a bool in as the value to set, the C standard says that it
gets converted to an int prior to shifting. If you try to set a bool to
bit 31, this lands you in undefined behavior. It's better just to add
the explicit cast and let the compiler delete it for us.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 25 Jan 2019 19:30:36 +0000 (13:30 -0600)]
intel/fs: Get rid of fs_inst::equals
There are piles of fields that it doesn't check so using it is a lie.
The only reason why it's not causing problem is because it has exactly
one user which only uses it for MOV instructions (which aren't very
interesting) and only on Sandy Bridge and earlier hardware. Just get
rid of it and inline it in the one place that it's actually used.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Rob Clark [Tue, 29 Jan 2019 17:29:16 +0000 (12:29 -0500)]
freedreno: minor cleanups
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 29 Jan 2019 17:23:28 +0000 (12:23 -0500)]
freedreno: stop frob'ing pipe_resource::nr_samples
Previously we tried to normalize nr_samples to MAX2(1, nr_samples) to
avoid having to deal with 0 vs 1 everywhere. But this causes problems
in mesa/st, for example st_finalize_texture() will think there is a
nr_samples mismatch and recreate the texture. Somehow this manifests
as corrupt x11 font rendering on generations that do not support MSAA
(but apparently works fine on a5xx and a6xx which do support MSAA.)
Fixes:
cf0c7258ee0 freedreno/a5xx: MSAA
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 29 Jan 2019 17:22:08 +0000 (12:22 -0500)]
freedreno/a6xx: fix blitter nr_samples check
nr_samples for non-MSAA case could be either zero or one.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 29 Jan 2019 17:21:19 +0000 (12:21 -0500)]
freedreno/a5xx: fix blitter nr_samples check
nr_samples for non-MSAA case could be either zero or one.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Bas Nieuwenhuizen [Mon, 28 Jan 2019 01:09:07 +0000 (02:09 +0100)]
radv: Enable VK_EXT_memory_priority.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Mon, 28 Jan 2019 00:23:14 +0000 (01:23 +0100)]
radv/winsys: Add priority handling during submit.
Switched to the raw bo list api to avoid having to use 2 arrays for
everything.
This was introduced in libdrm 2.4.97 which we already depend upon.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Sun, 27 Jan 2019 23:28:05 +0000 (00:28 +0100)]
radv/winsys: Set winsys bo priority on creation.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Mon, 28 Jan 2019 16:41:07 +0000 (17:41 +0100)]
radv: re-enable fast depth clears for 16-bit surfaces on VI
This has been disabled some months ago because it introduced
rendering issues with Shadow Of Warrier II (DXVK). This game is
no longer affected, I wonder if
824cfc1ee5e ("radv: rework the
TC-compat HTILE hardware bug with COND_EXEC") fixed the problem.
I checked The Forest on my Polaris, and it renders fine too.
According to Phillip, this gives +5.5% with Rise Of The Tomb
Raider and DXVK. This is because DXVK uses 16-bit depth surfaces
while the native port from Feral uses 32-bit depth surfaces.
Unfortunately, Shadow Of The Tomb Raider isn't affected because
it clears each layer of a D16 array texture individually. So it
doesn't hit the fast clear path.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Anholt [Mon, 28 Jan 2019 19:39:12 +0000 (11:39 -0800)]
vc4: Enable NEON asm on meson cross-builds.
The core Mesa with_asm_arch and USE_ARM_ASM flags are disabled for meson
cross-builds because of the need to run host binaries on the build system.
vc4 doesn't need to do that, so skip with_asm_arch to enable NEON on my
cross-builds.
Fixes:
ebcb4c2156e9 ("meson: Enable VC4's NEON assembly support.")
Carsten Haitzler (Rasterman) [Tue, 8 Jan 2019 16:28:30 +0000 (16:28 +0000)]
vc4: Declare the cpu pointers as being modified in NEON asm.
Otherwise, the compiler is free to reuse the register containing the input
for another call and assume that the value hasn't been modified. Fixes
crashes on texture upload/download with current gcc.
We now have to have a temporary for the cpu2 value, since outputs must be
lvalues.
(commit message by anholt)
Fixes:
4d30024238ef ("vc4: Use NEON to speed up utile loads on Pi2.")
Carsten Haitzler (Rasterman) [Tue, 8 Jan 2019 16:05:25 +0000 (16:05 +0000)]
vc4: Use named parameters for the NEON inline asm.
This makes the asm code more intelligible and clarifies the functional
change in the next commit.
(commit message and commit squashing by anholt)
Jonathan Marek [Mon, 28 Jan 2019 02:05:33 +0000 (21:05 -0500)]
kmsro: Add freedreno renderonly support
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Jonathan Marek [Mon, 28 Jan 2019 15:09:39 +0000 (10:09 -0500)]
freedreno: a2xx: add perfcntrs
Based on a5xx perfcntrs implementation.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Jonathan Marek [Wed, 23 Jan 2019 20:03:55 +0000 (15:03 -0500)]
freedreno: a2xx: minor solid_vertexbuf fixups
The big thing here is the 0x60 offset for the mem2gmem copy which I missed
in my last patch.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Jonathan Marek [Mon, 28 Jan 2019 17:49:54 +0000 (12:49 -0500)]
freedreno: a2xx: clear fixes and fast clear path
This fixes the depth/stencil clear on a20x, and adds a fast clear path.
The fast clear path is only used for a20x, needs performance tests on a22x.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Jonathan Marek [Wed, 19 Dec 2018 04:33:54 +0000 (23:33 -0500)]
freedreno: a2xx: a20x hw binning
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Jonathan Marek [Mon, 28 Jan 2019 13:01:28 +0000 (08:01 -0500)]
freedreno: update a2xx registers
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Timothy Arceri [Mon, 28 Jan 2019 06:15:34 +0000 (17:15 +1100)]
glsl: use remap location when serialising uniform program resource data
This allows us to avoid expensive string compares since we already have
a map to the pointers.
These compares were taking ~30 seconds for a single shader compile
in Godot due to it using 64,000+ uniforms.
Fixes:
c4cff5f40254 ("glsl: add basic support for resource list to shader cache")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109229
Vinson Lee [Sat, 26 Jan 2019 08:21:06 +0000 (00:21 -0800)]
meson: Fix typo.
meson.build:166:21: ERROR: Unknown method "verson_compare" for a string.
Fixes:
c1efa240c91e ("meson: Add warnings and errors when using ICC")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Jonathan Marek [Fri, 23 Nov 2018 15:58:11 +0000 (10:58 -0500)]
freedreno: a2xx: enable early-Z testing
Enable earlyZ when alpha test is disabled.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Jonathan Marek [Wed, 23 Jan 2019 22:43:28 +0000 (17:43 -0500)]
freedreno: a2xx: ir2 cleanup
Reviewed-by: Rob Clark <robdclark@gmail.com>
Rob Herring [Thu, 24 Jan 2019 20:03:54 +0000 (14:03 -0600)]
Switch imx to kmsro and remove the imx winsys
The kmsro winsys is equivalent to the imx winsys, so we can switch
to it and remove the imx one.
Signed-off-by: Rob Herring <robh@kernel.org>