Louis Dionne [Wed, 14 Jun 2023 21:05:00 +0000 (14:05 -0700)]
[libc++][NFC] Consistently qualify malloc and free calls with std::
Louis Dionne [Wed, 14 Jun 2023 20:59:45 +0000 (13:59 -0700)]
[libc++] Make libc++ and libc++abi's definitions of operator new be exact copies
This allows mechanically copying any changes made to `operator new`
from libc++ into libc++abi as-is. This is also a step towards
de-duplicating this code entirely.
Differential Revision: https://reviews.llvm.org/D153035
Timm Bäder [Thu, 4 May 2023 13:31:24 +0000 (15:31 +0200)]
[clang][Interp] Check inc/dec family of ops for initialization
Differential Revision: https://reviews.llvm.org/D149846
Alan Hu [Fri, 16 Jun 2023 00:56:39 +0000 (20:56 -0400)]
[OCaml] Rename link_modules' to link_modules
Commit 434e956 renamed link_modules to link_modules' for unclear reasons.
Based on the commit's diff, the author possibly intended to have two
functions, link_modules to bind to LLVMLinkModules and link_modules' to
bind to LLVMLinkModules2. However, there is only one function. link_modules'
appears in LLVM 3.8 onwards.
Differential Revision: https://reviews.llvm.org/D153090
Haojian Wu [Fri, 16 Jun 2023 13:15:07 +0000 (15:15 +0200)]
[clangd] Remove unused includes in IncludeCleaner.cpp, NFC
Nikita Popov [Fri, 16 Jun 2023 12:58:33 +0000 (14:58 +0200)]
[InstCombine][AArch64] Fix phi insertion point
Fix the issue reported at https://reviews.llvm.org/rG724f4a5bac25#inline-9083,
by specifying the correct insertion point for the new phi.
Nikita Popov [Fri, 16 Jun 2023 12:50:04 +0000 (14:50 +0200)]
[InstCombine] Regenerate test checks (NFC)
Simon Pilgrim [Fri, 16 Jun 2023 12:31:50 +0000 (13:31 +0100)]
[GlobalISel][X86] Add handling of scalar G_USUBE opcodes
Extend the G_UADDE handling to also support G_USUBE
Hans Wennborg [Thu, 15 Jun 2023 13:01:36 +0000 (15:01 +0200)]
[X86] Fix callee side of receiving byval args on the stack
See the discussion in
https://discourse.llvm.org/t/generic-llvm-ir-windows-x64-argument-passing-issue-in-llvm-11-0-0-and-later/71350
D51842 implemented byval lowering for Win64. D83175 made the call
lowering honor the "from now on treat this as a regular pointer" comment
also when the argument gets passed on the stack. However, it didn't
update the callee side.
Differential revision: https://reviews.llvm.org/D153020
Viktoriia Bakalova [Thu, 15 Jun 2023 12:44:07 +0000 (12:44 +0000)]
[clangd] Skip function parameter decls when evaluating variables on hover.
Differential Revision: https://reviews.llvm.org/D153015
Guray Ozen [Fri, 16 Jun 2023 11:52:29 +0000 (13:52 +0200)]
[mlir][nvvm] Introduce `mbarrier.arrive`
It introduces `mbarrier.arrive` that are in ptx78.
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D153021
Guray Ozen [Fri, 16 Jun 2023 08:14:00 +0000 (10:14 +0200)]
[mlir][nvvm] Introduce `mbarrier.inval`
Introduce support for PTX's `mbarrier.inval` .
Contiunation of D151334
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D151338
Guray Ozen [Fri, 16 Jun 2023 08:03:30 +0000 (10:03 +0200)]
[mlir][nvvm] Implement `mbarrier.init`
NV GPUs provides split arrive/wait barriers that one can syncronize a subgroup of threads in CTA. It is particularly important for Hopper GPUs and allows tracking engines like TMA. See for more details:
https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier
This initial implementation sets the foundation for future enhancements and additions.
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D151334
Jay Foad [Fri, 16 Jun 2023 10:01:29 +0000 (11:01 +0100)]
[MC] Use regunits instead of MCRegUnitIterator. NFC.
Differential Revision: https://reviews.llvm.org/D153122
Benjamin Kramer [Fri, 16 Jun 2023 11:20:32 +0000 (13:20 +0200)]
Nikita Popov [Thu, 15 Jun 2023 07:13:18 +0000 (09:13 +0200)]
[CGTypes] Remove recursion protection
With opaque pointers, it should no longer be necessary to protect
against recursion when converting Clang types to LLVM types, as
recursion can only be introduced via pointer types.
Differential Revision: https://reviews.llvm.org/D152999
Jaroslav Sevcik [Fri, 16 Jun 2023 10:35:41 +0000 (12:35 +0200)]
[lldb] Remove unused directive from test for D153043
Simon Pilgrim [Fri, 16 Jun 2023 10:45:36 +0000 (11:45 +0100)]
[GlobalISel][X86] Add s8/s16/s64 handling of G_UADDE opcodes
Nikita Popov [Fri, 16 Jun 2023 10:41:23 +0000 (12:41 +0200)]
[Clang] Fix compare-record.c test on s390x (NFC)
s390x looks through pointers when determining the "externally
visible vector ABI". For that reason, the test shows different
behavior just on that platform.
Adjust the test in the reverse direction of what I originall did:
Make sure that the type behind the pointer is always queried, by
dereferencing the pointer.
Jay Foad [Fri, 16 Jun 2023 10:38:56 +0000 (11:38 +0100)]
[AMDGPU] Regenerate a few checks
Takuya Shimizu [Fri, 16 Jun 2023 10:26:53 +0000 (19:26 +0900)]
[clang][Sema] Provide source range to several Wunused warnings
When the diagnosed function/variable is a template specialization, the source range covers the specialization arguments.
e.g.
```
warning: unused function 'func<int>' [-Wunused-function]
template <> int func<int> () {}
^~~~~~~~~
```
This comes in line with the printed text in the warning message. In the above case, `func<int>`
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D152707
LLVM GN Syncbot [Fri, 16 Jun 2023 10:20:24 +0000 (10:20 +0000)]
[gn build] Port
f873029386dd
Job Noorman [Fri, 16 Jun 2023 09:49:19 +0000 (11:49 +0200)]
[BOLT] Add minimal RISC-V 64-bit support
Just enough features are implemented to process a simple "hello world"
executable and produce something that still runs (including libc calls).
This was mainly a matter of implementing support for various
relocations. Currently, the following are handled:
- R_RISCV_JAL
- R_RISCV_CALL
- R_RISCV_CALL_PLT
- R_RISCV_BRANCH
- R_RISCV_RVC_BRANCH
- R_RISCV_RVC_JUMP
- R_RISCV_GOT_HI20
- R_RISCV_PCREL_HI20
- R_RISCV_PCREL_LO12_I
- R_RISCV_RELAX
- R_RISCV_NONE
Executables linked with linker relaxation will probably fail to be
processed. BOLT relocates .text to a high address while leaving .plt at
its original (low) address. This causes PC-relative PLT calls that were
relaxed to a JAL to not fit their offset in an I-immediate anymore. This
is something that will be addressed in a later patch.
Changes to the BOLT core are relatively minor. Two things were tricky to
implement and needed slightly larger changes. I'll explain those below.
The R_RISCV_CALL(_PLT) relocation is put on the first instruction of a
AUIPC/JALR pair, the second does not get any relocation (unlike other
PCREL pairs). This causes issues with the combinations of the way BOLT
processes binaries and the RISC-V MC-layer handles relocations:
- BOLT reassembles instructions one by one and since the JALR doesn't
have a relocation, it simply gets copied without modification;
- Even though the MC-layer handles R_RISCV_CALL properly (adjusts both
the AUIPC and the JALR), it assumes the immediates of both
instructions are 0 (to be able to or-in a new value). This will most
likely not be the case for the JALR that got copied over.
To handle this difficulty without resorting to RISC-V-specific hacks in
the BOLT core, a new binary pass was added that searches for
AUIPC/JALR pairs and zeroes-out the immediate of the JALR.
A second difficulty was supporting ABS symbols. As far as I can tell,
ABS symbols were not handled at all, causing __global_pointer$ to break.
RewriteInstance::analyzeRelocation was updated to handle these
generically.
Tests are provided for all supported relocations. Note that in order to
test the correct handling of PLT entries, an ELF file produced by GCC
had to be used. While I tried to strip the YAML representation, it's
still quite large. Any suggestions on how to improve this would be
appreciated.
Reviewed By: rafauler
Differential Revision: https://reviews.llvm.org/D145687
Alexey Lapshin [Thu, 15 Jun 2023 08:23:41 +0000 (10:23 +0200)]
[DWARFLinker][Reland] Handle DW_OP_GNU_push_tls_address while check for variable location.
The D147066 changed the way how DWARF location expressions are handled.
Now expressions are parsed and their operands are analysed. New handling
misses the DW_OP_GNU_push_tls_address extention. This patch adds handling
DW_OP_GNU_push_tls_address while checking for addresses.
Differential Revision: https://reviews.llvm.org/D153010
Cullen Rhodes [Fri, 16 Jun 2023 09:27:20 +0000 (09:27 +0000)]
[mlir][ArmSME] Insert intrinsics to enable/disable ZA
This patch adds two LLVM intrinsics to the ArmSME dialect:
* llvm.aarch64.sme.za.enable
* llvm.aarch64.sme.za.disable
for enabling the ZA storage array [1], as well as patterns for inserting
them during legalization to LLVM at the start and end of functions if
the function has the 'arm_za' attribute (D152695).
In the future ZA should probably be automatically enabled/disabled when
lowering from vector to SME, but this should be sufficient for now at
least until we have patterns lowering to SME instructions that use ZA.
N.B. The backend function attribute 'aarch64_pstate_za_new' can be used
manage ZA state (as was originally tried in D152694), but it emits calls
to the following SME support routines [2] for the lazy-save mechanism
[3]:
* __arm_tpidr2_restore
* __arm_tpidr2_save
These will soon be added to compiler-rt but there's currently no public
implementation, and using this attribute would introduce an MLIR
dependency on compiler-rt. Furthermore, this mechanism is for routines
with ZA enabled calling other routines with it also enabled. We can
choose not to enable ZA in the compiler when this is case.
Depends on D152695
[1] https://developer.arm.com/documentation/ddi0616/aa
[2] https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#sme-support-routines
[3] https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#the-za-lazy-saving-scheme
Reviewed By: awarzynski, dcaballe
Differential Revision: https://reviews.llvm.org/D153050
Alexey Lapshin [Fri, 16 Jun 2023 09:37:11 +0000 (11:37 +0200)]
Revert "[DWARFLinker] Handle DW_OP_GNU_push_tls_address while check for variable location."
This reverts commit
e89738451a3830d80fcf23554fd0b297bca60266.
Ivan Kosarev [Fri, 16 Jun 2023 09:25:49 +0000 (10:25 +0100)]
[AMDGPU][GFX11] Add test coverage for 16-bit conversions, part 15.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D152908
Cullen Rhodes [Fri, 16 Jun 2023 09:14:53 +0000 (09:14 +0000)]
[mlir][ArmSME] Extend streaming-mode pass to support enabling ZA
This patch extends the 'enable-arm-streaming' pass with a new option to
enable the ZA storage array by adding the 'arm_za' attribute to
'func.func' ops.
A later patch will insert `llvm.aarch64.sme.za.enable` at the beginning
of 'func.func' ops and `llvm.aarch64.sme.za.disable` before
`func.return` statements when lowering to LLVM dialect.
Currently the pass only supports enabling ZA with streaming-mode on but
the SME LDR, STR and ZERO instructions can access ZA when not in
streaming-mode (section B1.1.1, IDGNQM [1]), so it may be worth making
these options independent in the future.
N.B. This patch is generally useful in the context of SME enablement in
MLIR, but it will help enable writing an integration test for rewrite
pattern that lowers `vector.transfer_write` -> `zero {za}` (D152508).
[1] https://developer.arm.com/documentation/ddi0616/aa
Reviewed By: awarzynski, dcaballe
Differential Revision: https://reviews.llvm.org/D152695
Ivan Kosarev [Fri, 16 Jun 2023 09:07:50 +0000 (10:07 +0100)]
[AMDGPU][GFX11] Add test coverage for 16-bit conversions, part 11.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D152904
Jianjian GUAN [Fri, 16 Jun 2023 02:09:22 +0000 (10:09 +0800)]
[RISCV][NFC] Simplify code.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D153095
Alexey Lapshin [Thu, 15 Jun 2023 08:23:41 +0000 (10:23 +0200)]
[DWARFLinker] Handle DW_OP_GNU_push_tls_address while check for variable location.
The D147066 changed the way how DWARF location expressions are handled.
Now expressions are parsed and their operands are analysed. New handling
misses the DW_OP_GNU_push_tls_address extention. This patch adds handling
DW_OP_GNU_push_tls_address while checking for addresses.
Differential Revision: https://reviews.llvm.org/D153010
Théo Degioanni [Fri, 16 Jun 2023 08:34:59 +0000 (08:34 +0000)]
[mlir][llvm] Add memcpy support for mem2reg/sroa.
This revision introduces SROA and mem2reg support for the family of
memcpy-like intrinsics (memcpy, memcpy.inline and memmove).
The mem2reg implementation transforms memcpys of full types into loads
and store. Memcpy between two promotable slots always disappear.
The SROA implementation transforms memcpys of *entire* aggregate types
into memcpys of all of their fields.
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D152898
Weining Lu [Fri, 16 Jun 2023 01:08:26 +0000 (09:08 +0800)]
[LoongArch] Some cleanup and readability improvements to LoongArchISelLowering.cpp, NFC
Haojian Wu [Thu, 15 Jun 2023 13:38:03 +0000 (15:38 +0200)]
[include-cleaner] Reorder SymbolReference fields to avoid padding space, NFC
This will bring down the size from 40 bytes to 32 bytes.
Differential Revision: https://reviews.llvm.org/D153018
Timm Bäder [Tue, 14 Mar 2023 10:08:16 +0000 (11:08 +0100)]
[clang][Interp] Handle LambdaExprs
Differential Revision: https://reviews.llvm.org/D146030
Pavel Kosov [Thu, 8 Jun 2023 16:14:00 +0000 (19:14 +0300)]
[llvm-exegesis] Use MCJIT only for execution
Initially, llvm-exegesis was generating the benchmark code for the
host CPU to execute it inside its own process. Thus, MCJIT was reused
for fetching function's bytes to fill the assembled_snippet field in
the benchmark report.
Later, the --mtriple and --benchmark-phase command line options were
introduced that are handy for testing snippet generation even if
snippet execution is not possible. In that setup, MCJIT is asked to
parse an object file for a foreign CPU or operating system that is
probably not guaranteed to succeed and was actually observed to fail
in https://reviews.llvm.org/D145763.
This commit implements a much simplified function's code fetching,
assuming the benchmark function is the only function in the object file
and it spans across the entire text section (note that MCJIT-based code
has more or less the same assumption - see TrackingSectionMemoryManager
class).
~~~
Huawei RRI, OS Lab
Reviewed By: courbet
Differential Revision: https://reviews.llvm.org/D148921
Kadir Cetinkaya [Fri, 26 May 2023 21:14:41 +0000 (23:14 +0200)]
[clang] Don't create import decls without -fmodules
When modules are disabled, there's no loaded module for these import
decls to point at. This results in crashes when there are modulemap
files but no -fmodules flag (this configuration is used for layering
check violations).
This patch makes sure import declarations are introduced only when
modules are enabled, which makes this case similar to textual headers
(no import decls are created for #include of textual headers from a
modulemap).
Differential Revision: https://reviews.llvm.org/D152274
Craig Topper [Fri, 16 Jun 2023 07:02:15 +0000 (00:02 -0700)]
[RISCV] Fix spelling Compess->Compress. Fix 80 columns. NFC
Jonas Hahnfeld [Thu, 15 Jun 2023 07:39:20 +0000 (09:39 +0200)]
Remove clang/ModuleInfo.txt
The script build-for-llvm-top.sh and LLVM's ModuleInfo.txt are gone
since a long time (commit
d20ea7dc59 in November 2011), and llvm-top
itself has even been removed from llvm-archive (it can be found here:
https://github.com/llvm/llvm-archive/tree/
cab7f8f160f0bd8d20d9a4036aa4083f2bc2740a/llvm-top
) so delete Clang's ModuleInfo.txt as well.
Differential Revision: https://reviews.llvm.org/D152995
Pavel Labath [Fri, 16 Jun 2023 07:09:41 +0000 (09:09 +0200)]
Revert "[lldb] Rate limit progress reports -- different approach [WIP-ish]"
This reverts commit
c30853460da7446f92bc1e516f9cbe2c5df6e136, which I
pushed accidentally -- sorry.
Pavel Labath [Fri, 16 Jun 2023 07:05:27 +0000 (09:05 +0200)]
[lldb] Fix MainLoopTest for changes in D152712
Pavel Labath [Wed, 7 Jun 2023 09:52:45 +0000 (11:52 +0200)]
[lldb] Rate limit progress reports -- different approach [WIP-ish]
Have the Progress class spawn a thread to periodically send progress
reports.
The reporting period could be made configurable, but for now I've
hardcoded it to 100ms. (This is the main WIP part)
It could be argued that creating a thread for progress reporting adds
overhead, but I would counter that by saying "If the task is so fast
that creating a thread noticably slows it down, then it really doesn't
need progress reporting".
For me, this speeds up DWARF indexing by about 1.5% (which is only
slightly above the error bars), but I expect it will have a much bigger
impact in situations where printing a single progress update takes a
nontrivial amount of time.
Differential Revision: https://reviews.llvm.org/D152364
Fangrui Song [Fri, 16 Jun 2023 06:26:25 +0000 (23:26 -0700)]
[RISCV] relaxDwarfCallFrameFragment: remove unneeded relocations for relaxation
If `evaluateAsAbsolute(Value, Layout.getAssembler())` returns true, we
know the address delta is a constant and can suppress relocations
(usually SET6/SUB6).
While here, replace two evaluateKnownAbsolute calls (subtle; avoid if possible)
with evaluateAsAbsolute.
Jaroslav Sevcik [Thu, 15 Jun 2023 16:10:25 +0000 (18:10 +0200)]
[lldb] Fix handling of cfi_restore in the unwinder
Currently, lldb's unwinder ignores cfi_restore opcodes for registers
that are not set in the first row of the unwinding info. This prevents
unwinding of failed assertion in Chrome/v8 (https://github.com/v8/v8).
The attached test is an x64 copy of v8's function that failed to unwind
correctly (V8_Fatal).
This patch changes handling of cfi_restore to reset the location if
the first unwind table row does not map the restored register.
Differential Revision: https://reviews.llvm.org/D153043
Carlos Alberto Enciso [Fri, 16 Jun 2023 05:19:45 +0000 (06:19 +0100)]
[LICM] Sunk instructions with invalid source location.
Building the given test case with 'clang -O2 -g' the call to
'getInOrder' is sunk out of the loop by LICM, but the source
location is not dropped.
Reviewed By: aprantl, fdeazeve
Differential Revision: https://reviews.llvm.org/D152691
Jake Egan [Fri, 16 Jun 2023 05:22:21 +0000 (01:22 -0400)]
[AIX][tests] Temporarily disable test index-with-module.m
This test is failing on AIX due to patch D151938. Disable it for now to get the bot green while we investigate.
Serguei Katkov [Fri, 16 Jun 2023 04:12:53 +0000 (11:12 +0700)]
[CGP] Additional tests for removing operand of assume. NFC.
Jake Egan [Fri, 16 Jun 2023 04:32:26 +0000 (00:32 -0400)]
[AIX] Disable test for missing DWARF section
This new test is failing on AIX due to an unsupported DWARF section, so disable it (same rationale as patch D111336).
Kazuki Sakamoto [Fri, 16 Jun 2023 00:33:36 +0000 (17:33 -0700)]
[lldb][TerminalTest] Fix assertion failure
D152712 replaced `llvm::sys::RetryAfterSignal(-1, ::open)` with
`FileSystem::Instance().Open` for bionic in PseudoTerminal::OpenSecondary, and
FileSystem::Instance() is failing with assertion on arm Linux.
The assertion should be FileSystem re-initialization check, therefore the
hypothesis is that TerminalTest tests are initializing FileSystem instance
repeatedly.
Use SubsystemRAII<FileSystem> to ensure tearing down the FileSystem instance.
Differential Revision: https://reviews.llvm.org/D153091
Fangrui Song [Fri, 16 Jun 2023 03:40:14 +0000 (20:40 -0700)]
[MC][test] Add some label difference tests
Sergei Barannikov [Mon, 12 Jun 2023 02:03:21 +0000 (05:03 +0300)]
[RegAlloc] Simplify RegAllocEvictionAdvisor::canReassign (NFC)
Use range-based for loops.
The return type has been changed to bool because the method is only
used in boolean contexts.
Reviewed By: mtrofin
Differential Revision: https://reviews.llvm.org/D152665
Sergei Barannikov [Sun, 21 May 2023 01:28:33 +0000 (04:28 +0300)]
[MC] Add MCRegisterInfo::regunits for iteration over register units
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D152098
Sergei Barannikov [Sun, 11 Jun 2023 19:32:23 +0000 (22:32 +0300)]
[MC] Merge MC[Sub,Super]RegIterator with mc_[sub,super]_reg_iterator
Turn MC*RegIterator into fully qualified iterators by deriving them from
iterator_adaptor_base. This makes mc_*_reg iterators redundant.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D152655
tianleli [Fri, 16 Jun 2023 01:15:43 +0000 (09:15 +0800)]
[DAG] Unroll opereand when its type is illegal for ldexp.
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D152997
Bing1 Yu [Fri, 16 Jun 2023 01:42:36 +0000 (09:42 +0800)]
Revert "[CodeGen] Disable default copy ctor and copy assignment operator for class Array"
This reverts commit
466678b5202052dcd38fdfc3f764fb5d5de7c34b.
Fangrui Song [Fri, 16 Jun 2023 01:35:51 +0000 (18:35 -0700)]
[MC] Improve .subsection diagnostic
Jason Molenda [Fri, 16 Jun 2023 00:37:42 +0000 (17:37 -0700)]
lldb [NFC] Add logging to Process when address masks are updated
To aid in integration testing/debugging. Verifying that the address
mask/addressable bits values from different sources are correctly
registered by lldb.
Kai Sasaki [Thu, 15 Jun 2023 23:59:31 +0000 (08:59 +0900)]
[mlir][doc] Fix the layout of the table for the tosa.cast permissible operations
We can make the table for the `tosa.cast` permissible operations readable by utilizing the markdown table format.
{
F27924602}
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D152992
Aart Bik [Thu, 15 Jun 2023 21:10:24 +0000 (14:10 -0700)]
[mlir][sparse] enhance element-wise fusion heuristics
We prevent merging a sparse-in/dense-out with dense-in
kernels because the result is usuall not sparsifiable.
Dense kernels and sparse kernels are still fused, obviously.
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D153077
Kun Wu [Thu, 15 Jun 2023 23:48:06 +0000 (23:48 +0000)]
[mlir][sparse][gpu] recognizing sddmm pattern in GPU libgen path
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D151582
Evgenii Stepanov [Wed, 14 Jun 2023 23:58:20 +0000 (16:58 -0700)]
[scudo] Disable OddEvenTags by default.
Scudo has zero-tagged headers between any two allocation that will catch
a linear buffer overflow of up to 16 bytes. OddEvenTags extends this
guarantee to one chunk of the given SizeClass at the cost of the reduced
entropy for all heap tags (i.e. lower chance to catch use-after-free and
large overflows).
Given that the first 16 bytes are already deterministic, I feel this is
a bad tradeoff.
Differential Revision: https://reviews.llvm.org/D152984
Leonard Chan [Thu, 15 Jun 2023 23:14:05 +0000 (23:14 +0000)]
[compiler-rt] Go back to using the 32-bit allocator for Fuchsia+RISCV64
Due to logic in the 64-bit allocator, the smallest allocation we can
zx_vmar_allocate is 2^37 bytes, but this is too large to allocate for
the standalone lsan allocator on a 39-bit VMA. This leads to the
zx_vmar_allocate call when initially setting up the allocator to fail.
This is similar to what android experiences on a 64-bit system with a
small vma. (See sanitizer_allocator_test.cpp).
This effectively reverts
f6c4808d95221a5838e14474d95c6fe85bb1488a and
has Fuchsia use the 32-bit allocator for RISCV.
Kirill Stoimenov [Thu, 15 Jun 2023 22:59:37 +0000 (22:59 +0000)]
[Sanitizers] Remove unused parameter from COMMON_INTERCEPTOR_MUNMAP_IMPL
This was a result of copy/paste from the MMAP interceptor which uses the parameter to swtich between mmap and mmap64.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D152980
Fangrui Song [Thu, 15 Jun 2023 23:12:10 +0000 (16:12 -0700)]
[MC] Remove unneeded special cases from AttemptToFoldSymbolOffsetDifference
Alfred Persson Forsberg [Thu, 15 Jun 2023 23:08:57 +0000 (00:08 +0100)]
[scudo] Do not compile timing.cpp if LLVM_LIBC_INCLUDE_SCUDO=on
Temporary hack until LLVM libc supports inttypes.h print format macros
timing.h uses the PRId64 macro which is not included in llvm libc yet
Bug: https://github.com/llvm/llvm-project/issues/63317
Reviewed By: michaelrj, thesamesam, Chia-hungDuan
Differential Revision: https://reviews.llvm.org/D152979
NAKAMURA Takumi [Thu, 15 Jun 2023 23:00:00 +0000 (08:00 +0900)]
[CGCall] Prune ArgStruct [-Wunused-variable]
It has been unused since
b92ccc355acb
Vladislav Dzhidzhoev [Thu, 15 Jun 2023 10:22:16 +0000 (12:22 +0200)]
Reland "[DebugMetadata][DwarfDebug] Fix DWARF emisson of function-local imported entities (3/7)"
Got rid of non-determinism in MetadataLoader.cpp.
Authored-by: Kristina Bessonova <kbessonova@accesssoftek.com>
Differential Revision: https://reviews.llvm.org/D144004
Jason Molenda [Thu, 15 Jun 2023 22:39:01 +0000 (15:39 -0700)]
Add a fatal error for debug builds when disagreement about stepping
On one CI bot we're seeing a failure where the kernel reports that
we have completed an instruction step (via a mach exception) and
lldb doesn't think the thread was doing an instruction step. It
takes the conservative approach of stopping at this point, breaking
tests.
This patch adds an llvm fatal error for debug builds where it will
log the state of the thread and the AArch64 ESR, to confirm what
the hardware reported as the exception so we can double check the
kernel's interpretation.
I'll change this to an lldbassert without the runtime details in
the string once we have an idea what is happening. the hope is
that this will get hit on the CI bot soon.
Differential Revision: https://reviews.llvm.org/D153079
Chia-hung Duan [Thu, 8 Jun 2023 03:20:52 +0000 (03:20 +0000)]
[scudo] Group MappedUser/AllocatedUser into PagesInfo (NFC)
Create a new PagesInfo to contain all the information about pages. This
is the preparation of adding new lock for page operations.
Note that primary32 hasn't switched to MemMap. Will add PagesInfo later
when we move to MemMap in primary32.
Differential Revision: https://reviews.llvm.org/D149142
Chia-hung Duan [Thu, 8 Jun 2023 03:20:40 +0000 (03:20 +0000)]
[scudo] Group poppedBlocks/pushedBlocks into BlocksInfo (NFC)
Create a new BlocksInfo to contain a list of blocks, poppedBlocks and
pushedBlocks. This is the preparation of adding new lock for operations
on freelist.
Differential Revision: https://reviews.llvm.org/D149143
Oleksii Odynochenko [Thu, 15 Jun 2023 20:52:22 +0000 (13:52 -0700)]
[llvm-cov] Normalize paths by removing dots
We were producing inconsistent results when a file appeared multiple
times in gcno/gcda files if the instances had differing relative paths.
This patch unifies filenames, so coverage results are merged.
Patch by Oleksii Odynochenko. Thanks!
Differential Revision: https://reviews.llvm.org/D152453
Craig Topper [Thu, 15 Jun 2023 22:18:47 +0000 (15:18 -0700)]
[RISCV] Prevent vsetvli insertion from deleting some vsetvli instructions
If the result register is used, it is not safe to delete.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D153076
Fangrui Song [Thu, 15 Jun 2023 22:07:04 +0000 (15:07 -0700)]
[MC] Remove unneeded isUndefined() for isSymbolRefDifferenceFullyResolved. NFC
The only caller `AttemptToFoldSymbolOffsetDifference` has performed the same
checks.
Alex Langford [Fri, 26 May 2023 22:50:26 +0000 (15:50 -0700)]
[lldb][NFCI] Remove use of ConstString from IOHandler
None of these need to be in the ConstString StringPool. For the most
part they are constant strings and do not require fast comparisons.
I did change IOHandlerDelegateMultiline slightly -- specifically, the
`m_end_line` member always has a `\n` at the end of it now. This was so
that `IOHandlerGetControlSequence` can always return a StringRef. This
did require a slight change to `IOHandlerIsInputComplete` where we must
drop the newline before comparing it against the input parameter.
Differential Revision: https://reviews.llvm.org/D151597
Alex Langford [Fri, 9 Jun 2023 19:31:56 +0000 (12:31 -0700)]
[lldb] Symtab::SectionFileAddressesChanged should clear the file address map instead of name map
Currently, `SectionFileAddressesChanged` clears out the `name_to_index`
map and sets `m_file_addr_to_index_compute` to false. This is strange,
as these two fields are used for different purposes. What we should be
doing is clearing the file address to index mapping.
There are 2 bugs here:
1. If we call SectionFileAddressesChanged after the name indexes have
been computed, we end up with an empty name to index map, so lookups
will fail. This doesn't happen today because we don't initialize the
name indexes before calling this, but this is a refactor away from
failing in this way.
2. Because we don't clear `m_file_addr_to_index` but still set it's
computed flag to false, it ends up with twice the amount of
information. One entry will be correct (since it was recalculated),
one entry will be outdated.
rdar://
110192434
Differential Revision: https://reviews.llvm.org/D152579
Simon Pilgrim [Thu, 15 Jun 2023 21:40:42 +0000 (22:40 +0100)]
[GlobalISel][X86] Add i128 add/sub test coverage for narrowing on x86_64 triples
Simon Pilgrim [Thu, 15 Jun 2023 19:06:58 +0000 (20:06 +0100)]
[GlobalIsel][X86] Avoid IMPLICIT_DEF in irregular types for CTTZ/CTLZ legalization tests
IMPLICIT_DEF can lead to some pretty weird G_UNMERGE_VALUES of long lists of s1 values, try to use a real source value instead
Artem Belevich [Thu, 15 Jun 2023 21:26:21 +0000 (14:26 -0700)]
[CUDA] Updated CUDA versions mentioned in CompileCudaWithLLVM.rst
Kazuki Sakamoto [Mon, 12 Jun 2023 15:30:45 +0000 (08:30 -0700)]
[lldb][Android] Use a lambda for calls to ::open in RetryAfterSignal
lldb-server for Android does not build with NDK r21 and above due to
RetryAfterSignal and Bionic ::open mismatch.
https://github.com/llvm/llvm-project/issues/54727
Apply the LLVM patch to LLDB.
https://github.com/llvm/llvm-project/commit/
0a0e411204a2baa520fd73a8d69b664f98b428ba
> In Bionic, open can be overloaded for _FORTIFY_SOURCE support, causing
> compile errors of RetryAfterSignal due to overload resolution. Wrapping
> the call in a lambda avoids this.
Differential Revision: https://reviews.llvm.org/D152712
Arthur Eubanks [Thu, 15 Jun 2023 21:06:15 +0000 (14:06 -0700)]
[SimplifyCFG] Add textual pass params for FoldTwoEntryPHINode and SimplifyCondBranch
Philip Reames [Thu, 15 Jun 2023 21:00:57 +0000 (14:00 -0700)]
[RISCV][InsertVSETVLI] Treat vmv.v.i as-if it were vmv.s.x when VL=1, and inactive lanes are undefined
A vmv.v.i/x splats the immediate to all active lanes. For the active lanes, this is the same as vmv.s.x which inserts one scalar into the low lane. If we can ignore all the inactive lanes (because they are known undefined), then the two are semantically equivalent. We already reason about compatible VL/VTYPE combinations for vmv.s.x, apply the same logic to vmv.v.i.
Unlike a vmv.s.x, we do need to be careful not to increase LMUL. A splat instruction is probably linear in LMUL, so restrict this to LMUL1.
Differential Revision: https://reviews.llvm.org/D152845
Peiming Liu [Thu, 15 Jun 2023 21:04:46 +0000 (21:04 +0000)]
[mlir][sparse] using stable_sort to make sure the compiled code are consistent between different builds configuration
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D153074
Aart Bik [Wed, 14 Jun 2023 22:18:00 +0000 (15:18 -0700)]
[mlir][sparse] proper in-place SDDMM with spy function
This specific operation matches the cuSPARSE SDDMM semantics exactly.
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D152969
Arthur Eubanks [Thu, 15 Jun 2023 20:55:42 +0000 (13:55 -0700)]
[SimplifyCFG] Check optforfuzzing attribute during in the pass implementation
Instead of setting the SimplifyCFGOptions options at the beginning of the pass.
Otherwise it always gets overriden by the pass and the value in SimplifyCFGOptions is ignored.
Fangrui Song [Thu, 15 Jun 2023 20:52:20 +0000 (13:52 -0700)]
[MC] Remove an unneeded special case from MCObjectStreamer::flushPendingLabels
We always pass a non-null F to flushPendingLabels. Wait a bit before changing
the parameter to use a reference.
Joseph Huber [Thu, 15 Jun 2023 20:12:10 +0000 (15:12 -0500)]
[libc][obvious] Actually return the value from `malloc` for NVPTX
Switching to this interface we neglected to actually write the output
from the malloc call to the RPC buffer. Fix this so the tests pass
again.
Differential Revision: https://reviews.llvm.org/D153069
Pranav Kant [Thu, 15 Jun 2023 19:50:08 +0000 (19:50 +0000)]
David Green [Thu, 15 Jun 2023 19:46:20 +0000 (20:46 +0100)]
[ARM] Fix for invalid register in ReplaceConstByVPNOTs
This ensures a removed register does not get reused as we replace constant vpt
values.
Fangrui Song [Thu, 15 Jun 2023 19:35:06 +0000 (12:35 -0700)]
[M68k] Use parseOptionalToken. NFC
Fangrui Song [Thu, 15 Jun 2023 19:31:14 +0000 (12:31 -0700)]
[CSKY] Use parseOptionalToken. NFC
Many code paths are untested.
Some "expected ..." messages are adjusted, otherwise NFC.
LLVM GN Syncbot [Thu, 15 Jun 2023 19:11:21 +0000 (19:11 +0000)]
[gn build] Port
3a7876f6e2b0
Amir Ayupov [Thu, 15 Jun 2023 19:08:07 +0000 (12:08 -0700)]
[BOLT] Sort BranchData in DataAggregator
Align perf reader to fdata behavior by sorting BranchData after reading samples,
in the same way as DataReader:
https://github.com/llvm/llvm-project/blob/
20c66a0c66340f44f04b6526e45bcc5d872d480a/bolt/lib/Profile/DataReader.cpp#L1239
Namely, that order affects CallSiteInfo annotations which determine the
construction order of CallGraph, which in turn affects function reordering.
Reviewed By: #bolt, rafauler
Differential Revision: https://reviews.llvm.org/D152731
Craig Topper [Thu, 15 Jun 2023 19:03:25 +0000 (12:03 -0700)]
Recommit "[SelectionDAG][RISCV] Add very basic PromoteIntegerResult/Op support for VP_SIGN/ZERO_EXTEND."
I have fixed an existing DAGCombiner bug that caused the previous assertion failure.
See
7163539466d7e8930416e55dd9fd29891f8239f2.
Original message
We don't have VP_ANY_EXTEND or VP_SIGN_EXTEND_INREG yet so I've
deviated a little from the non-VP lowering.
My goal was to fix the crashes that occurs on these test cases without this patch.
Reviewed By: fakepaper56
Differential Revision: https://reviews.llvm.org/D152854
Fangrui Song [Thu, 15 Jun 2023 19:01:16 +0000 (12:01 -0700)]
[LoongArch] Use parseOptionalToken. NFC
Mehdi Amini [Thu, 15 Jun 2023 18:57:35 +0000 (20:57 +0200)]
Fix MLIR build with SHARED_LIBS=ON, add missing cmake dependency
Fangrui Song [Thu, 15 Jun 2023 18:51:52 +0000 (11:51 -0700)]
[Xtensa] Use parseOptionalToken. NFC
Craig Topper [Thu, 15 Jun 2023 18:42:21 +0000 (11:42 -0700)]
[DAGCombiner] When combining (sext_inreg (zext X), VT) -> (sext X) don't pass along the sext_inreg VT.
ISD::SIGN_EXTEND is only supposed to have one operand, but we
were creating it with 2 operands.
Since we basically never check for extra operands this went
unnoticed.
Zequan Wu [Thu, 15 Jun 2023 18:45:19 +0000 (14:45 -0400)]
Louis Dionne [Tue, 13 Jun 2023 17:44:51 +0000 (10:44 -0700)]
[libc++][NFC] Reformat params.py
After the Black reformatting changes, the code became pretty hard to
read and inconsistently formatted. This fixes that.
Differential Revision: https://reviews.llvm.org/D152839
Fangrui Song [Thu, 15 Jun 2023 18:45:22 +0000 (11:45 -0700)]
[MSP430] Use parseOptionalToken. NFC