docs: add missing ACO_DEBUG=force-waitdeps

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22688>

docs: rename ACO_DEBUG=noscheduling to ACO_DEBUG=nosched

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22688>

egl: Clear EGL_WINDOW_BIT for non-double-buffered EGLConfigs

EGL windows are not required to support single-buffered rendering,
and it's awful, so let's not.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22685>

radv: reserve command buffer index for SQTT

These indexes are used to match command buffers with queue events.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22670>

ac/sqtt: add a helper to get cmdbuf IDs per queue

These will be used by RADV to implement queue event timings.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22670>

ac/sqtt: add rgp_sqtt_marker_cb_id definition

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22670>

aco: don't move exec reads around exec writes

Fixes flickering and blocky plants in Jedi: Fallen Order.

Also fixes flickering squares in The Last of Us Part 1.

fossil-db (navi21):
Totals from 92 (0.07% of 135636) affected shaders:
Instrs: 35324 -> 35354 (+0.08%); split: -0.03%, +0.11%
CodeSize: 189568 -> 189668 (+0.05%); split: -0.03%, +0.08%
Latency: 345305 -> 346529 (+0.35%); split: -0.02%, +0.37%
InvThroughput: 78632 -> 78625 (-0.01%)
SClause: 1955 -> 1972 (+0.87%); split: -0.61%, +1.48%
Copies: 1311 -> 1304 (-0.53%); split: -0.69%, +0.15%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8883
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8878
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22696>

bump VVL to 1.3.248

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22672>

intel/tools: add ability to dump out raw kernels data

Useful for debug.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22703>

r300: add CI list of known rv370 dEQP failures

We don't have CI, but its still convenient for local testing.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22705>

r300: fix unconditional KIL on R300/R400

  0: KIL -none.1111

Negate is not allowed for texturing opcodes, so the incorrect swizzle
was detected, however later optimization, where we try to rewrite incorrect
swizzles from constant (immediate) registers by adding a new ones with
correct order was interfering and not handling this correctly, so we
ended with

CONST[0] = {    -1.0000    -1.0000    -1.0000    -1.0000 }
  0: KIL const[0].xyz-w;

Even if it would get the swizzle right, texturing opcodes can't read from
constant registers, so just skip it and let this be handled by a later
part which inserts an extra mov instead.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Fixes: a8e1e5b5c2aeb7c2fb4eff2203a026090f0853b9
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22704>

radv/ci: document another vkcts flake on vega10

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22702>

docs: correct spelling of "frame"

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: correct spelling of "tagged"

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: correct spelling of "source"

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: toplevel -> top-level

This is how we spell it elsewhere.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: vlan -> VLAN

VLAN is an abbreviation, so let's spell it in all-caps for clarity.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: use correct tick for "doesn't"

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: perfetto -> Perfetto

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: Anv -> ANV

We're usually spelling ANV in allcaps, so let's do that here as well.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: cma -> CMA

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: did't -> didn't

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: codepath -> code-path

This is consistent with how we spell this elsewhere in the docs.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: backfacing -> back-facing

This is consistent with how the OpenGL spec spells it.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: statechanges -> state changes

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

docs: renderpass -> render pass

The Vulkan spec spells render pass in two words, so let's do the same.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22286>

glsl: remove ir_state_slot::swizzle

Same story as with the NIR counterpart in the previous commit.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22620>

nir: remove nir_state_slot::swizzle

This is only ever written to, never read from. Let's just get rid of it!

This also saves us a few needless includes.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22620>

zink: use EXT_shader_object to implement generic separate shader precompile

this adds precompile for all separate shader stages (+tcs,tes,geom)
using separate shaders, which should eliminate stuttering for games
using it (e.g., Tomb Raider)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: fix longstanding TODO for generated tcs

with dynamic pcp this doesn't matter, and this should only be reached
in async mode if dynamic pcp is available

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: handle all stages in fixup_io_locations()

this makes the handling a bit more complex, as both input and output
need to be handled for most stages, and also the per-component handling
gets trickier

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: move separate shader creation to shader CSO creation

this is a more logical place for it and also enables u_blitter
shaders to be fast-linked

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: use a more standardized loop for initing separate shader program descriptors

this should be identical to previous behavior

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: assign separate shader prog stages from ctx->shader_stages

this is functionally equivalent given the checks above which already
restrict which stages can be passed

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: move some shader CSO functions around

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: switch to a regular loop to wait on precompile shader fences

even if these aren't done yet, it'll still be faster to wait than
to start compiling new pipelines now

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: streamline separate shader descriptor update

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: simplify separate shader prog init a little

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: use intermediate variable for separate shader db resize check

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

zink: use intermediate variable for separate shader descriptor update loop

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>

aco,radv: remove unused aco compile options

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

aco,ac/llvm,radv,radeonsi: handle ps bc optimization in nir for radv

The side effect is removing the aco/llvm backend bc optimization code
and linear/persp_centroid variable.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

ac/nir/ps: remove used nir_variable if created

RADV won't do this, so remove them at last.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

radv: implement nir_load_barycentric_optimize_amd

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

ac/llvm: remove output variable declaration for radv ps

radv ps does not support epilog when llvm, so outputs will always
be lowered to exports in nir.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

aco,radv: lower outputs to exports when nir for monolithic ps

Remove the compiler backend code for outputs to exports.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

aco: support nir_export_amd with ps targets

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

ac/nir/ps: add no_color_export option

For radv which always do ps lower but may use epilog or not.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

ac/nir/ps: use nir_export_dual_src_blend_amd when aco

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

aco: implement nir_export_dual_src_blend_amd

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

aco: move create_fs_dual_src_export_gfx11 above

Will be used in visit_intrinsic(), content is not changed.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

nir: add nir_export_dual_src_blend_amd intrinsic

For GFX11 export dual source blend outputs when ACO.
ACO need a pseudo instruction to emit a block of
code which can't be done in nir currently.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

ac/nir/ps: fix null export write mask miss set to 0xf

Fixes: c1821544562 ("ac/nir: add ac_nir_lower_ps")
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>

radv/rt: remove merged VkRayTracingShaderGroupCreateInfoKHR

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>

radv/rt: replace uses of pGroups with radv_ray_tracing_group

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>

radv: Hash pipeline libraries separately

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>

radv/rt: add shader stage indices to radv_ray_tracing_group

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>

radv/rt: rename radv_ray_tracing_module -> radv_ray_tracing_group

This name better reflects the purpose and content of this struct.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>

svga: set PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY for VGPU10 device

Instead of forcing vertex buffer stride to be 4 byte aligned only,
DX10 actually allows the stride to be non 4-byte aligned but the
alignment of an element must be the nearest power of 2 greater or equal to the
width of the element's format, or 4, whichever is less.  So the requirement is
better met with PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY which if set to
TRUE, the sum of vertex element offset + vertex buffer offset + vertex buffer
stride must be aligned to the vertex attributes component size.
Note: PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY cannot be set
with other alignment-requiring CAPs, so we have to return 0 for all the
other alignement CAPs.

This avoids some unnecessary software vertex translate fallback.

cc: mesa-stable

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22689>

intel/dev: report stepping for TGL systems

Workaround 14010672564 requires a check for the TGL B0 stepping.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>

intel/dev: update mesa_defs.json from defect database

These modifications represent:

 * changes to defects made since Feb 16, 2023
 * changes to automated processing of defect state

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>

glx: add fail check for current context in another thread

The GLX spec for glXMakeCurrent (3.3):
"If ctx is current to some other thread, then glXMakeCurrent will generate
a BadAccess error"

The GLX spec for glXCopyContext (3.3):
"If the destination context is current for some thread then a BadAccess
error is generated"

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7961
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22546>

radv/rt: properly destroy radv_ray_tracing_lib_pipeline on error

Also return the correct error code.

Fixes: 4dafb69d61820c4a9b71856e62797b51f13df91c ('radv/rt: defer library_pipeline allocation')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22684>

ci/zink: Try to update TGL results for new MSAA behavior.

A few fixes, but mostly tons of new GPU hangs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22691>

ci/crocus: Note a recent regression.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22691>

ci/lima: Skip ppgtt_memory_alignment that flaked a job with the oomkiller.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22691>

ci/panfrost: Drop tex3d-maxsize on g52.

Implicated in 3 job-level flakes where Xorg got killed yesterday.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22691>

ci: add a660 firmware into rootfs

Until we bump to Debian 12 (bookworm).

Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22604>

ci/lava: add support for HDK 888 firmware

Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22604>

ci/lava: implement fastboot support

Based on work from Tomeu Vizoso.

Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22604>

ci: add Adreno 660 on sm8350 chipset (HDK 888)

Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22604>

aux/draw: fix memory leak related to ureg_get_tokens()

Indeed, the function nir_to_tgsi() returns an ureg_get_tokens() allocated
object which is assigned locally. The ureg_get_tokens() allocated object
should be freed.

For instance, this issue is triggered with a llvm enabled lima,
"piglit/bin/gl-1.0-rendermode-feedback -auto -fbo":
Direct leak of 512 byte(s) in 1 object(s) allocated from:
    #0 0x7faeaa4500 in __interceptor_realloc (/usr/lib64/libasan.so.6+0xa4500)
    #1 0x7fa4a88f1c in tokens_expand ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:239
    #2 0x7fa4a88f1c in get_tokens ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:262
    #3 0x7fa4a900f4 in copy_instructions ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2079
    #4 0x7fa4a900f4 in ureg_finalize ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2129
    #5 0x7fa4a91dfc in ureg_get_tokens ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2206
    #6 0x7fa4b20a2c in nir_to_tgsi_options ../src/gallium/auxiliary/nir/nir_to_tgsi.c:4011
    #7 0x7fa4a0c914 in draw_create_vertex_shader ../src/gallium/auxiliary/draw/draw_vs.c:77

Fixes: b5e782f5f431 ("aux/draw: use nir_to_tgsi for draw shader in llvm path")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21924>

radv: Don't leak the RT prolog binary

Fixes: 063d0c90 ("radv: Combine all the parts together with a main loop for an RT pipeline.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22535>

radv/rt: Plug some memory leaks during shader creation

nir_inline_function actually clones instructions instead of moving them.
Free the shaders explicitly after inserting them instead.

Fixes: 207ce6d658 ("radv: Add helper to inline shaders into the main shader.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22535>

zink: print the type of shader when dumping

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22692>

nouveau/codegen: Check nir_dest_num_components

instead of reaching into a union and pulling out garbage when
the dest is a reg

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8863
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22674>

freedreno/a6xx: Change a618 tile_align_h back to 32

Commit 60bc7c0e221 ("freedreno: Specify GMEM tile alignment per GPU")
changed the tile_align_h from 32 to 16 (which _should_ be the correct
value).  But this is causing failure in android 9 skqp dstreadshuffle.
(But not, seemingly, with the android 11 version of skia+skqp, which
picks the same tile size.  So this is likely papering something over.)

For now, to unblock things, revert back to the previous tile_align_h.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22683>

freedreno: Fix resource tracking vs rebind/invalidate

We can now no longer rely on certain dirty bits to re-trigger draw time
resource tracking.  We need to use the new fd_dirty*_resource() APIs.

Fixes `org.skia.skqp.SkQPRunner#gles_recordopts` on android 9.

Fixes: 0a62a874fc5 ("freedreno: Re-work dirty-resource tracking")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22683>

radv/rmv: Fix import memory

For some import memory, it is valid to specify zero size.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22532>

radv/rmv: Fix creating RT pipelines

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22532>

ci/dzn: Run almost the full CTS

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22639>

dzn: Re-design custom buffer descriptors

Previously, custom buffer descriptors were owned by a descriptor set. Now,
custom buffer descriptors are owned by the buffer. Additionally, we respect
the app-provided sizes when they're smaller than the buffer size, even if
robustness is not enabled, so that size queries work correctly.

This new design fixes several issues:
* Descriptor set copies were broken when they involved custom descriptors,
  because the original descriptor set owned the lifetime of the custom
  descriptor, the new one was just borrowing it. If those lifetimes didn't
  line up, problems would arise.
* A single buffer with the same sub-view placed in multiplel descriptor sets
  would allocate multiple slots, when it only really needed one.
* Custom buffer descriptors now lower the base offset to 0 to allow merging
  multiple overlapping (ending at the same upper bound) descriptors. Since
  the shader is already doing an offset add, making it nonzero is free.
* Dynamic buffer descriptors were incorrect before. The size passed into the
  descriptor set is supposed to be the size from the *dynamic* offset, not the
  size from the static offset. By allocating/populating the descriptor when
  placed into the set, it prevented larger offsets from working correctly. This
  buffer-owned design prevents cmdbufs from having to own lifetime of custom
  descriptors.

Fixes dEQP-VK.ssbo.unsized_array_length.float_offset_explicit_size

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22639>

dzn: Handle depth bias for point fill mode emulation

Fixes dEQP-VK.draw.renderpass.depth_bias.depth_bias_triangle_list_point

This is not complete, there's no slope scale or clamp handling, but it
does handle static or dynamic (though dynamic is untested).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22639>

dzn: Handle opaque BC1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22639>

dzn: Use unrestricted copy alignments when available

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22639>

ci/windows: Update Agility SDK to 1.610.2

Otherwise non-normalized sampling coords are unintentionally disabled

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22639>

zink: fix store subsitution in `lower_pv_mode_gs_store`

Previously it was assumed that between the and the variable there was
only one deref.

To handle all cases a new function is introduced that recreates a chain
of derefs.

Fixes: 5a4083349f3 ("zink: add provoking vertex mode lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22678>

nir/zink: use sysvals in `nir_create_passthrough_gs`

Previously the passthrough gs shader loaded some values with uniform
loads using sevaral hardcoded values.

This was not flexible for other drivers and started becoming too
unflexible for zink itself.

Use system values instead and use a lowering pass in zink.

Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22667>

pvr: Add PVR_DW_TO_BYTES()

We use dwords (32 bit) quite a bit around the code base. Previously
we used '* 4', '<< 2', or '* sizeof(uint32_t)' to go from dwords to
bytes. The conversion isn't always clear when other operations
happen in the same line, which can leave one wondering where the
multiplication came from.
PVR_DW_TO_BYTES() should make the code more obvious as well as
making the conversion more consistent.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22658>

anv: implement state cache invalidate for Wa_16013063087

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>

anv: cleanup bitmask construction for PIPELINE_SELECT

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>

iris: implement state cache invalidate for Wa_16013063087

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>

broadcom/compiler: return early for SFU op latency calculation

Since we are returning a fixed latency for these check for them
earlier and return early if they match.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22675>

broadcom/compiler: fix incorrect ALU checks

We had a bunch of cases where we would check ALU parameters without
first checking if the ALU op was valid.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22675>

radeonsi: implement fw based mcbp

Some chips support firmware based mcbp. If supported this means
radeonsi needs to allocate 3 buffers and pass them to the firmware.

From there, the firmware will handle mcbp and register shadowing
on its own so we don't need to insert LOAD packet in the preamble.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986>

amd: determine info->has_fw_based_shadowing

The shadow_size value will be 0 if unsupported.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986>

amd: update amdgpu_drm.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986>

venus: fix the RHEL8 build by using syscall for gettid

src/virtio/vulkan/vn_common.c: In function ‘vn_ring_monitor_acquire’:
src/virtio/vulkan/vn_common.c:129:16: error: implicit declaration of function ‘gettid’; did you mean ‘getgid’? [-Werror=implicit-function-declaration]
  129 |    pid_t tid = gettid();

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22489>

ci/valve: Add a workaround for finding libdrm on navi21s.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22495>

ci/zink: Drop anv/lvp validation exceptions that should be fixed in the CTS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22495>